source: rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-early.c @ 6c454104

4.11
Last change on this file since 6c454104 was 6c454104, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 13, 2012 at 10:50:38 AM

bsp/mpc55xx: Fix no-cache section load

  • Property mode set to 100644
File size: 5.0 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup mpc55xx
5 *
6 * @brief Early initialization code.
7 */
8
9/*
10 * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.com/license/LICENSE.
21 */
22
23#include <bsp.h>
24#include <bsp/start.h>
25#include <bsp/mpc55xx-config.h>
26#include <bsp/linker-symbols.h>
27
28/* This function is defined in start.S */
29BSP_START_TEXT_SECTION void mpc55xx_start_load_section(
30  void *dst,
31  const void *src,
32  size_t n
33);
34
35static BSP_START_TEXT_SECTION void mpc55xx_start_mmu(void)
36{
37  #ifdef MPC55XX_BOOTFLAGS
38    /* If the low bit of bootflag 0 is clear don't change the MMU.  */
39    bool do_mmu_config = (mpc55xx_bootflag_0 [0] & 1) != 0;
40  #else
41    bool do_mmu_config = true;
42  #endif
43
44  if (do_mmu_config) {
45    mpc55xx_start_mmu_apply_config(
46      &mpc55xx_start_config_mmu [0],
47      mpc55xx_start_config_mmu_count [0]
48    );
49  }
50}
51
52static BSP_START_TEXT_SECTION void mpc55xx_start_internal_ram(void)
53{
54  #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
55    /* Initialize internal SRAM to zero (ECC) */
56    bsp_start_zero(
57      (char *) bsp_ram_start + MPC55XX_EARLY_STACK_SIZE,
58      (size_t) bsp_ram_size - MPC55XX_EARLY_STACK_SIZE
59    );
60    #ifdef MPC55XX_HAS_SECOND_INTERNAL_RAM_AREA
61      bsp_start_zero(&bsp_ram_1_start [0], (size_t) bsp_ram_1_size);
62    #endif
63  #else
64    bsp_start_zero(
65      bsp_section_sbss_begin,
66      (size_t) bsp_section_sbss_size
67    );
68    bsp_start_zero(
69      bsp_section_bss_begin,
70      (size_t) bsp_section_bss_size
71    );
72  #endif
73}
74
75static BSP_START_TEXT_SECTION void mpc55xx_start_load_nocache_section(void)
76{
77  mpc55xx_start_load_section(
78    bsp_section_nocache_begin,
79    bsp_section_nocache_load_begin,
80    (size_t) bsp_section_nocache_size
81  );
82  rtems_cache_flush_multiple_data_lines(
83    bsp_section_nocache_begin,
84    (size_t) bsp_section_nocache_size
85  );
86}
87
88static BSP_START_TEXT_SECTION void mpc55xx_start_mode_change(void)
89{
90  #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
91    #ifdef MPC55XX_HAS_MODE_CONTROL
92      uint32_t mctl_key1 = 0x5af0;
93      uint32_t mctl_key2 = 0xa50f;
94      int i = 0;
95
96      /* Clear any pending RGM status */
97      RGM.FES.R = 0xffff;
98      RGM.DES.R = 0xffff;
99
100      /* Make sure XOSC and PLLs are on in RUN0 state */
101      ME.DRUN_MC.R = 0x001f0074;
102      ME.RUN_MC [0].R = 0x001f0074;
103
104      /*
105       * Make sure all peripherals are active in DRUN and RUN0 state.
106       *
107       * FIXME: This might be optimized to reduce power consumtion.
108       */
109      for (i = 0; i < 8; ++i) {
110        ME_RUN_PC_32B_tag run_pc = { .R = ME.RUN_PC [i].R };
111
112        run_pc.B.DRUN = 1;
113        run_pc.B.RUN0 = 1;
114
115        ME.RUN_PC [i].R = run_pc.R;
116      }
117
118      /* Switch to RUN0 state */
119      ME.MCTL.R = 0x40000000 | mctl_key1;
120      ME.MCTL.R = 0x40000000 | mctl_key2;
121
122      while (ME.GS.B.S_MTRANS) {
123        /* Wait for mode switch to be completed */
124      }
125    #endif
126  #endif
127}
128
129static BSP_START_TEXT_SECTION void mpc55xx_start_siu(void)
130{
131  size_t i = 0;
132
133  for (i = 0; i < mpc55xx_start_config_siu_pcr_count [0]; ++i) {
134     const mpc55xx_siu_pcr_config *e = &mpc55xx_start_config_siu_pcr [i];
135     int j = e->index;
136     int n = j + e->count;
137     uint8_t gpdo = e->output;
138     uint16_t pcr = e->pcr.R;
139
140     while (j < n) {
141       SIU.GPDO [j].R = gpdo;
142       SIU.PCR [j].R = pcr;
143       ++j;
144     }
145  }
146}
147
148static BSP_START_TEXT_SECTION void mpc55xx_start_ebi_chip_select(void)
149{
150  #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
151    #ifdef MPC55XX_HAS_EBI
152      size_t i = 0;
153
154      for (i = 0; i < mpc55xx_start_config_ebi_cs_count [0]; ++i) {
155        EBI.CS [i] = mpc55xx_start_config_ebi_cs [i];
156      }
157
158      for (i = 0; i < mpc55xx_start_config_ebi_cal_cs_count [0]; ++i) {
159        EBI.CAL_CS [i] = mpc55xx_start_config_ebi_cal_cs [i];
160      }
161    #endif
162  #endif
163}
164
165static BSP_START_TEXT_SECTION void mpc55xx_start_ebi(void)
166{
167  #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
168    #if defined(MPC55XX_BOARD_GWLCFM)
169      /*
170       * init EBI for Muxed AD bus
171       */
172      EBI.MCR.B.DBM = 1;
173      EBI.MCR.B.AD_MUX = 1; /* use multiplexed bus */
174      EBI.MCR.B.D16_31 = 1; /* use lower AD bus    */
175
176      SIU.ECCR.B.EBDF = 3;  /* use CLK/4 as bus clock */
177    #elif defined(MPC55XX_BOARD_MPC5674FEVB) \
178      || defined(MPC55XX_BOARD_MPC5674F_ECU508)
179      union EBI_MCR_tag mcr = {
180        .B = {
181          .ACGE = 0,
182          .MDIS = 0,
183          .D16_31 = 1,
184          .AD_MUX = 0,
185          .DBM = 0
186        }
187      };
188
189      EBI.MCR.R = mcr.R;
190    #endif
191  #endif
192}
193
194BSP_START_TEXT_SECTION void mpc55xx_start_early(void)
195{
196  mpc55xx_start_watchdog();
197  mpc55xx_start_clock();
198  mpc55xx_start_flash();
199  #if defined(BSP_DATA_CACHE_ENABLED) || defined(BSP_INSTRUCTION_CACHE_ENABLED)
200    mpc55xx_start_cache();
201  #endif
202  mpc55xx_start_internal_ram();
203  mpc55xx_start_load_nocache_section();
204  mpc55xx_start_mmu();
205  mpc55xx_start_mode_change();
206  mpc55xx_start_siu();
207  mpc55xx_start_ebi_chip_select();
208  mpc55xx_start_ebi();
209}
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