1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc55xx |
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5 | * |
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6 | * @brief Early initialization code. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.com/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <bsp.h> |
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24 | #include <bsp/start.h> |
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25 | #include <bsp/mpc55xx-config.h> |
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26 | #include <bsp/linker-symbols.h> |
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27 | |
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28 | /* This function is defined in start.S */ |
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29 | BSP_START_TEXT_SECTION void mpc55xx_start_load_section( |
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30 | void *dst, |
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31 | const void *src, |
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32 | size_t n |
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33 | ); |
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34 | |
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35 | static BSP_START_TEXT_SECTION void mpc55xx_start_mmu(void) |
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36 | { |
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37 | #ifdef MPC55XX_BOOTFLAGS |
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38 | /* If the low bit of bootflag 0 is clear don't change the MMU. */ |
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39 | bool do_mmu_config = (mpc55xx_bootflag_0 [0] & 1) != 0; |
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40 | #else |
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41 | bool do_mmu_config = true; |
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42 | #endif |
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43 | |
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44 | if (do_mmu_config) { |
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45 | mpc55xx_start_mmu_apply_config( |
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46 | &mpc55xx_start_config_mmu [0], |
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47 | mpc55xx_start_config_mmu_count [0] |
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48 | ); |
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49 | } |
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50 | } |
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51 | |
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52 | static BSP_START_TEXT_SECTION void mpc55xx_start_internal_ram(void) |
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53 | { |
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54 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
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55 | /* Initialize internal SRAM to zero (ECC) */ |
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56 | bsp_start_zero( |
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57 | (char *) bsp_ram_start + MPC55XX_EARLY_STACK_SIZE, |
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58 | (size_t) bsp_ram_size - MPC55XX_EARLY_STACK_SIZE |
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59 | ); |
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60 | #ifdef MPC55XX_HAS_SECOND_INTERNAL_RAM_AREA |
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61 | bsp_start_zero(&bsp_ram_1_start [0], (size_t) bsp_ram_1_size); |
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62 | #endif |
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63 | #else |
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64 | bsp_start_zero( |
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65 | bsp_section_sbss_begin, |
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66 | (size_t) bsp_section_sbss_size |
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67 | ); |
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68 | bsp_start_zero( |
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69 | bsp_section_bss_begin, |
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70 | (size_t) bsp_section_bss_size |
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71 | ); |
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72 | #endif |
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73 | } |
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74 | |
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75 | static BSP_START_TEXT_SECTION void mpc55xx_start_load_nocache_section(void) |
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76 | { |
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77 | mpc55xx_start_load_section( |
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78 | bsp_section_nocache_begin, |
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79 | bsp_section_nocache_load_begin, |
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80 | (size_t) bsp_section_nocache_size |
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81 | ); |
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82 | rtems_cache_flush_multiple_data_lines( |
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83 | bsp_section_nocache_begin, |
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84 | (size_t) bsp_section_nocache_size |
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85 | ); |
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86 | } |
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87 | |
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88 | static BSP_START_TEXT_SECTION void mpc55xx_start_mode_change(void) |
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89 | { |
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90 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
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91 | #ifdef MPC55XX_HAS_MODE_CONTROL |
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92 | uint32_t mctl_key1 = 0x5af0; |
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93 | uint32_t mctl_key2 = 0xa50f; |
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94 | int i = 0; |
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95 | |
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96 | /* Clear any pending RGM status */ |
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97 | RGM.FES.R = 0xffff; |
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98 | RGM.DES.R = 0xffff; |
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99 | |
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100 | /* Make sure XOSC and PLLs are on in RUN0 state */ |
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101 | ME.DRUN_MC.R = 0x001f0074; |
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102 | ME.RUN_MC [0].R = 0x001f0074; |
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103 | |
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104 | /* |
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105 | * Make sure all peripherals are active in DRUN and RUN0 state. |
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106 | * |
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107 | * FIXME: This might be optimized to reduce power consumtion. |
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108 | */ |
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109 | for (i = 0; i < 8; ++i) { |
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110 | ME_RUN_PC_32B_tag run_pc = { .R = ME.RUN_PC [i].R }; |
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111 | |
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112 | run_pc.B.DRUN = 1; |
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113 | run_pc.B.RUN0 = 1; |
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114 | |
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115 | ME.RUN_PC [i].R = run_pc.R; |
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116 | } |
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117 | |
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118 | /* Switch to RUN0 state */ |
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119 | ME.MCTL.R = 0x40000000 | mctl_key1; |
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120 | ME.MCTL.R = 0x40000000 | mctl_key2; |
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121 | |
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122 | while (ME.GS.B.S_MTRANS) { |
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123 | /* Wait for mode switch to be completed */ |
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124 | } |
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125 | #endif |
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126 | #endif |
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127 | } |
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128 | |
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129 | static BSP_START_TEXT_SECTION void mpc55xx_start_siu(void) |
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130 | { |
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131 | size_t i = 0; |
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132 | |
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133 | for (i = 0; i < mpc55xx_start_config_siu_pcr_count [0]; ++i) { |
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134 | const mpc55xx_siu_pcr_config *e = &mpc55xx_start_config_siu_pcr [i]; |
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135 | int j = e->index; |
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136 | int n = j + e->count; |
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137 | uint8_t gpdo = e->output; |
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138 | uint16_t pcr = e->pcr.R; |
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139 | |
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140 | while (j < n) { |
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141 | SIU.GPDO [j].R = gpdo; |
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142 | SIU.PCR [j].R = pcr; |
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143 | ++j; |
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144 | } |
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145 | } |
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146 | } |
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147 | |
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148 | static BSP_START_TEXT_SECTION void mpc55xx_start_ebi_chip_select(void) |
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149 | { |
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150 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
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151 | #ifdef MPC55XX_HAS_EBI |
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152 | size_t i = 0; |
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153 | |
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154 | for (i = 0; i < mpc55xx_start_config_ebi_cs_count [0]; ++i) { |
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155 | EBI.CS [i] = mpc55xx_start_config_ebi_cs [i]; |
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156 | } |
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157 | |
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158 | for (i = 0; i < mpc55xx_start_config_ebi_cal_cs_count [0]; ++i) { |
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159 | EBI.CAL_CS [i] = mpc55xx_start_config_ebi_cal_cs [i]; |
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160 | } |
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161 | #endif |
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162 | #endif |
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163 | } |
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164 | |
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165 | static BSP_START_TEXT_SECTION void mpc55xx_start_ebi(void) |
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166 | { |
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167 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
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168 | #if defined(MPC55XX_BOARD_GWLCFM) |
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169 | /* |
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170 | * init EBI for Muxed AD bus |
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171 | */ |
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172 | EBI.MCR.B.DBM = 1; |
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173 | EBI.MCR.B.AD_MUX = 1; /* use multiplexed bus */ |
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174 | EBI.MCR.B.D16_31 = 1; /* use lower AD bus */ |
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175 | |
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176 | SIU.ECCR.B.EBDF = 3; /* use CLK/4 as bus clock */ |
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177 | #elif defined(MPC55XX_BOARD_MPC5674FEVB) || defined(MPC55XX_BOARD_MPC5674F_ECU508) |
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178 | union EBI_MCR_tag mcr = { |
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179 | .B = { |
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180 | .ACGE = 0, |
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181 | .MDIS = 0, |
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182 | .D16_31 = 1, |
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183 | .AD_MUX = 0, |
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184 | .DBM = 0 |
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185 | } |
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186 | }; |
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187 | |
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188 | EBI.MCR.R = mcr.R; |
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189 | #endif |
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190 | #endif |
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191 | } |
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192 | |
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193 | BSP_START_TEXT_SECTION void mpc55xx_start_early(void) |
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194 | { |
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195 | mpc55xx_start_watchdog(); |
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196 | mpc55xx_start_clock(); |
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197 | mpc55xx_start_flash(); |
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198 | #if defined(BSP_DATA_CACHE_ENABLED) || defined(BSP_INSTRUCTION_CACHE_ENABLED) |
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199 | mpc55xx_start_cache(); |
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200 | #endif |
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201 | mpc55xx_start_internal_ram(); |
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202 | mpc55xx_start_load_nocache_section(); |
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203 | mpc55xx_start_mmu(); |
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204 | mpc55xx_start_mode_change(); |
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205 | mpc55xx_start_siu(); |
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206 | mpc55xx_start_ebi_chip_select(); |
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207 | mpc55xx_start_ebi(); |
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208 | } |
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