source: rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-mmu.c @ 4dafa52

4.115
Last change on this file since 4dafa52 was 4dafa52, checked in by Sebastian Huber <sebastian.huber@…>, on 01/28/13 at 11:38:55

bsp/mpc55xx: Fix MMU configuration for RSM6
  • Property mode set to 100644
File size: 7.9 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup mpc55xx
5 *
6 * @brief MMU configuration.
7 */
8
9/*
10 * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.com/license/LICENSE.
21 */
22
23#include <bsp/mpc55xx-config.h>
24
25const struct MMU_tag mpc55xx_start_config_mmu [] = {
26#if defined(MPC55XX_BOARD_GWLCFM)
27  /* External Ethernet Controller 64k */
28  MPC55XX_MMU_TAG_INITIALIZER(5, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
29#elif defined(MPC55XX_BOARD_PHYCORE_MPC5554)
30  /* Arguments macro:       idx,  addr,      size,              x, w, r, io */
31  MPC55XX_MMU_TAG_INITIALIZER(8, 0x20000000, MPC55XX_MMU_8M,    1, 0, 1, 0), /* External FLASH 8M */
32  MPC55XX_MMU_TAG_INITIALIZER(2, 0x21000000, MPC55XX_MMU_4M,    0, 1, 1, 0), /* Lower half SRAM */
33  MPC55XX_MMU_TAG_INITIALIZER(5, 0x21400000, MPC55XX_MMU_4M,    1, 1, 1, 0), /* Upper half SRAM ("debug") */
34  MPC55XX_MMU_TAG_INITIALIZER(6, 0x22000000, MPC55XX_MMU_16M,   0, 1, 1, 1), /* LAN91C111 */
35  MPC55XX_MMU_TAG_INITIALIZER(7, 0x23000000, MPC55XX_MMU_16M,   0, 1, 1, 1), /* FPGA */
36#elif defined(MPC55XX_BOARD_MPC5566EVB)
37  /* Internal flash 3M */
38  MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0),
39  MPC55XX_MMU_TAG_INITIALIZER(6, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0),
40  MPC55XX_MMU_TAG_INITIALIZER(7, 0x00020000, MPC55XX_MMU_64K, 1, 0, 1, 0),
41  MPC55XX_MMU_TAG_INITIALIZER(8, 0x00030000, MPC55XX_MMU_64K, 1, 0, 1, 0),
42  MPC55XX_MMU_TAG_INITIALIZER(9, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
43  MPC55XX_MMU_TAG_INITIALIZER(10, 0x00080000, MPC55XX_MMU_256K, 1, 0, 1, 0),
44  MPC55XX_MMU_TAG_INITIALIZER(11, 0x000c0000, MPC55XX_MMU_256K, 1, 0, 1, 0),
45  MPC55XX_MMU_TAG_INITIALIZER(12, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0),
46  MPC55XX_MMU_TAG_INITIALIZER(13, 0x00200000, MPC55XX_MMU_1M, 1, 0, 1, 0),
47  /* External SRAM 512k */
48  MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_256K, 0, 1, 1, 0),
49  MPC55XX_MMU_TAG_INITIALIZER(14, 0x20040000, MPC55XX_MMU_256K, 0, 1, 1, 0),
50  /* Internal SRAM 128k */
51  MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_64K, 0, 1, 1, 0),
52  MPC55XX_MMU_TAG_INITIALIZER(5, 0x40010000, MPC55XX_MMU_64K, 0, 1, 1, 0),
53  /* External Ethernet Controller 64k */
54  MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
55#elif defined(MPC55XX_BOARD_MPC5674FEVB)
56  /* Internal flash 4M */
57  MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0),
58  MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0),
59  MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, MPC55XX_MMU_128K, 1, 0, 1, 0),
60  MPC55XX_MMU_TAG_INITIALIZER(7, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
61  MPC55XX_MMU_TAG_INITIALIZER(8, 0x00080000, MPC55XX_MMU_512K, 1, 0, 1, 0),
62  MPC55XX_MMU_TAG_INITIALIZER(9, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0),
63  MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, MPC55XX_MMU_2M, 1, 0, 1, 0),
64  /* External SRAM 512k */
65  MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_512K, 0, 1, 1, 0),
66  /* Internal SRAM 256k */
67  MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_128K, 0, 1, 1, 0),
68  MPC55XX_MMU_TAG_INITIALIZER(11, 0x40020000, MPC55XX_MMU_64K, 0, 1, 1, 0),
69  MPC55XX_MMU_TAG_INITIALIZER(12, 0x40030000, MPC55XX_MMU_32K, 0, 1, 1, 0),
70  MPC55XX_MMU_TAG_INITIALIZER(13, 0x40038000, MPC55XX_MMU_16K, 0, 1, 1, 0),
71  MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K, 0, 1, 1, 1),
72  /* External Ethernet controller */
73  MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1)
74#elif defined(MPC55XX_BOARD_MPC5674F_ECU508)
75  #if defined(MPC55XX_NEEDS_LOW_LEVEL_INIT)
76    /* Arguments macro:       idx,  addr,       size,             x, w, r, io */
77
78    /* Internal flash 4M */
79    /* First 64k unused, to detect NULL pointer access */
80    MPC55XX_MMU_TAG_INITIALIZER(1,  0x00000000, MPC55XX_MMU_64K,  1, 0, 1, 0),
81    MPC55XX_MMU_TAG_INITIALIZER(5,  0x00010000, MPC55XX_MMU_64K,  1, 0, 1, 0),
82    MPC55XX_MMU_TAG_INITIALIZER(6,  0x00020000, MPC55XX_MMU_128K, 1, 0, 1, 0),
83    MPC55XX_MMU_TAG_INITIALIZER(7,  0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
84    MPC55XX_MMU_TAG_INITIALIZER(8,  0x00080000, MPC55XX_MMU_512K, 1, 0, 1, 0),
85    MPC55XX_MMU_TAG_INITIALIZER(9,  0x00100000, MPC55XX_MMU_1M,   1, 0, 1, 0),
86    MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, MPC55XX_MMU_2M,   1, 0, 1, 0),
87    /* External SRAM 2M */
88    MPC55XX_MMU_TAG_INITIALIZER(2,  0x20000000, MPC55XX_MMU_2M,   0, 1, 1, 0),
89    /* Internal SRAM 256k */
90    MPC55XX_MMU_TAG_INITIALIZER(3,  0x40000000, MPC55XX_MMU_256K, 0, 1, 1, 0),
91    MPC55XX_MMU_TAG_INITIALIZER(11, 0x40020000, MPC55XX_MMU_64K,  0, 1, 1, 0),
92    MPC55XX_MMU_TAG_INITIALIZER(12, 0x40030000, MPC55XX_MMU_32K,  0, 1, 1, 0),
93    MPC55XX_MMU_TAG_INITIALIZER(13, 0x40038000, MPC55XX_MMU_16K,  0, 1, 1, 0),
94    /* Used as cache-inhibited area (ADC, DSPI queues) */
95    MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K,  0, 1, 1, 1),
96    /* External Ethernet controller */
97    MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_1K,   0, 1, 1, 1),
98    /* External MRAM 128k */
99    MPC55XX_MMU_TAG_INITIALIZER(16, 0x3ffa0000, MPC55XX_MMU_128K, 0, 1, 1, 0),
100    /* External ARCNET controller */
101    MPC55XX_MMU_TAG_INITIALIZER(17, 0x3ffc0000, MPC55XX_MMU_1K,   0, 1, 1, 1)
102    /* Peripheral Bridge A-Registers on MMU-table pos 4 */
103    /* Peripheral Bridge B-Registers on MMU-table pos 0 */
104  #else
105    /* Used as cache-inhibited area (ADC, DSPI queues) */
106    MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K,  0, 1, 1, 1),
107  #endif
108#elif defined(MPC55XX_BOARD_MPC5674F_RSM6)
109  #if defined(MPC55XX_NEEDS_LOW_LEVEL_INIT)
110    /* Arguments macro:       idx,  addr,       size,             x, w, r, io */
111
112    /* Internal flash 4M */
113    /* First 64k unused, to detect NULL pointer access */
114    MPC55XX_MMU_TAG_INITIALIZER(1,  0x00000000, MPC55XX_MMU_64K,  1, 0, 1, 0),
115    MPC55XX_MMU_TAG_INITIALIZER(5,  0x00010000, MPC55XX_MMU_64K,  1, 0, 1, 0),
116    MPC55XX_MMU_TAG_INITIALIZER(6,  0x00020000, MPC55XX_MMU_128K, 1, 0, 1, 0),
117    MPC55XX_MMU_TAG_INITIALIZER(7,  0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0),
118    MPC55XX_MMU_TAG_INITIALIZER(8,  0x00080000, MPC55XX_MMU_512K, 1, 0, 1, 0),
119    MPC55XX_MMU_TAG_INITIALIZER(9,  0x00100000, MPC55XX_MMU_1M,   1, 0, 1, 0),
120    MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, MPC55XX_MMU_2M,   1, 0, 1, 0),
121    /* External MRAM 4M */
122    MPC55XX_MMU_TAG_INITIALIZER(2,  0x20000000, MPC55XX_MMU_4M,   0, 1, 1, 0),
123    /* Internal SRAM 256k */
124    MPC55XX_MMU_TAG_INITIALIZER(3,  0x40000000, MPC55XX_MMU_256K, 0, 1, 1, 0),
125    MPC55XX_MMU_TAG_INITIALIZER(11, 0x40020000, MPC55XX_MMU_64K,  0, 1, 1, 0),
126    MPC55XX_MMU_TAG_INITIALIZER(12, 0x40030000, MPC55XX_MMU_32K,  0, 1, 1, 0),
127    MPC55XX_MMU_TAG_INITIALIZER(13, 0x40038000, MPC55XX_MMU_16K,  0, 1, 1, 0),
128    /* Used as cache-inhibited area (ADC, DSPI queues) */
129    MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K,  0, 1, 1, 1),
130    /* External FPGA */
131    MPC55XX_MMU_TAG_INITIALIZER(15, 0x21000000, MPC55XX_MMU_8M,   0, 1, 1, 1),
132    #if defined(MPC55XX_BOARD_MPC5674F_RSM6_KOMA)
133      /* External Ethernet controller */
134      MPC55XX_MMU_TAG_INITIALIZER(17, 0x23000000, MPC55XX_MMU_1K, 0, 1, 1, 1),
135    #endif
136  #else
137    /* Used as cache-inhibited area (ADC, DSPI queues) */
138    MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K,  0, 1, 1, 1),
139  #endif
140#elif MPC55XX_CHIP_FAMILY == 564
141  /* Internal flash 1M */
142  MPC55XX_MMU_TAG_INITIALIZER(0, 0x00000000, MPC55XX_MMU_1M, 1, 0, 1, 0),
143  /* IO */
144  MPC55XX_MMU_TAG_INITIALIZER(1, 0xffe00000, MPC55XX_MMU_2M, 0, 1, 1, 1),
145  MPC55XX_MMU_TAG_INITIALIZER(2, 0xc3f00000, MPC55XX_MMU_1M, 0, 1, 1, 1),
146  /* Internal SRAM 64k + 64k */
147  MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_64K, 0, 1, 1, 0),
148  MPC55XX_MMU_TAG_INITIALIZER(4, 0x50000000, MPC55XX_MMU_64K, 0, 1, 1, 0)
149#endif
150};
151
152const size_t mpc55xx_start_config_mmu_count [] = {
153  RTEMS_ARRAY_SIZE(mpc55xx_start_config_mmu)
154};
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