1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc55xx |
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5 | * |
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6 | * @brief MMU configuration. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.com/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <bsp/mpc55xx-config.h> |
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24 | |
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25 | const struct MMU_tag mpc55xx_start_config_mmu [] = { |
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26 | #if defined(MPC55XX_BOARD_GWLCFM) |
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27 | /* External Ethernet Controller 64k */ |
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28 | MPC55XX_MMU_TAG_INITIALIZER(5, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1) |
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29 | #elif defined(MPC55XX_BOARD_PHYCORE_MPC5554) |
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30 | /* Arguments macro: idx, addr, size, x, w, r, io */ |
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31 | MPC55XX_MMU_TAG_INITIALIZER(8, 0x20000000, MPC55XX_MMU_8M, 1, 0, 1, 0), /* External FLASH 8M */ |
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32 | MPC55XX_MMU_TAG_INITIALIZER(2, 0x21000000, MPC55XX_MMU_4M, 0, 1, 1, 0), /* Lower half SRAM */ |
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33 | MPC55XX_MMU_TAG_INITIALIZER(5, 0x21400000, MPC55XX_MMU_4M, 1, 1, 1, 0), /* Upper half SRAM ("debug") */ |
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34 | MPC55XX_MMU_TAG_INITIALIZER(6, 0x22000000, MPC55XX_MMU_16M, 0, 1, 1, 1), /* LAN91C111 */ |
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35 | MPC55XX_MMU_TAG_INITIALIZER(7, 0x23000000, MPC55XX_MMU_16M, 0, 1, 1, 1), /* FPGA */ |
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36 | #elif defined(MPC55XX_BOARD_MPC5566EVB) |
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37 | /* Internal flash 3M */ |
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38 | MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0), |
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39 | MPC55XX_MMU_TAG_INITIALIZER(6, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0), |
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40 | MPC55XX_MMU_TAG_INITIALIZER(7, 0x00020000, MPC55XX_MMU_64K, 1, 0, 1, 0), |
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41 | MPC55XX_MMU_TAG_INITIALIZER(8, 0x00030000, MPC55XX_MMU_64K, 1, 0, 1, 0), |
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42 | MPC55XX_MMU_TAG_INITIALIZER(9, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0), |
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43 | MPC55XX_MMU_TAG_INITIALIZER(10, 0x00080000, MPC55XX_MMU_256K, 1, 0, 1, 0), |
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44 | MPC55XX_MMU_TAG_INITIALIZER(11, 0x000c0000, MPC55XX_MMU_256K, 1, 0, 1, 0), |
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45 | MPC55XX_MMU_TAG_INITIALIZER(12, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0), |
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46 | MPC55XX_MMU_TAG_INITIALIZER(13, 0x00200000, MPC55XX_MMU_1M, 1, 0, 1, 0), |
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47 | /* External SRAM 512k */ |
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48 | MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_256K, 0, 1, 1, 0), |
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49 | MPC55XX_MMU_TAG_INITIALIZER(14, 0x20040000, MPC55XX_MMU_256K, 0, 1, 1, 0), |
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50 | /* Internal SRAM 128k */ |
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51 | MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_64K, 0, 1, 1, 0), |
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52 | MPC55XX_MMU_TAG_INITIALIZER(5, 0x40010000, MPC55XX_MMU_64K, 0, 1, 1, 0), |
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53 | /* External Ethernet Controller 64k */ |
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54 | MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1) |
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55 | #elif defined(MPC55XX_BOARD_MPC5674FEVB) |
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56 | /* Internal flash 4M */ |
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57 | MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0), |
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58 | MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0), |
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59 | MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, MPC55XX_MMU_128K, 1, 0, 1, 0), |
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60 | MPC55XX_MMU_TAG_INITIALIZER(7, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0), |
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61 | MPC55XX_MMU_TAG_INITIALIZER(8, 0x00080000, MPC55XX_MMU_512K, 1, 0, 1, 0), |
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62 | MPC55XX_MMU_TAG_INITIALIZER(9, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0), |
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63 | MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, MPC55XX_MMU_2M, 1, 0, 1, 0), |
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64 | /* External SRAM 512k */ |
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65 | MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_512K, 0, 1, 1, 0), |
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66 | /* Internal SRAM 256k */ |
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67 | MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_128K, 0, 1, 1, 0), |
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68 | MPC55XX_MMU_TAG_INITIALIZER(11, 0x40020000, MPC55XX_MMU_64K, 0, 1, 1, 0), |
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69 | MPC55XX_MMU_TAG_INITIALIZER(12, 0x40030000, MPC55XX_MMU_32K, 0, 1, 1, 0), |
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70 | MPC55XX_MMU_TAG_INITIALIZER(13, 0x40038000, MPC55XX_MMU_16K, 0, 1, 1, 0), |
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71 | MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K, 0, 1, 1, 1), |
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72 | /* External Ethernet controller */ |
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73 | MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_64K, 0, 1, 1, 1) |
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74 | #elif defined(MPC55XX_BOARD_MPC5674F_ECU508) |
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75 | #if defined(MPC55XX_NEEDS_LOW_LEVEL_INIT) |
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76 | /* Arguments macro: idx, addr, size, x, w, r, io */ |
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77 | |
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78 | /* Internal flash 4M */ |
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79 | /* First 64k unused, to detect NULL pointer access */ |
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80 | MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0), |
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81 | MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0), |
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82 | MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, MPC55XX_MMU_128K, 1, 0, 1, 0), |
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83 | MPC55XX_MMU_TAG_INITIALIZER(7, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0), |
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84 | MPC55XX_MMU_TAG_INITIALIZER(8, 0x00080000, MPC55XX_MMU_512K, 1, 0, 1, 0), |
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85 | MPC55XX_MMU_TAG_INITIALIZER(9, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0), |
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86 | MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, MPC55XX_MMU_2M, 1, 0, 1, 0), |
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87 | /* External SRAM 2M */ |
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88 | MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_2M, 0, 1, 1, 0), |
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89 | /* Internal SRAM 256k */ |
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90 | MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_256K, 0, 1, 1, 0), |
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91 | MPC55XX_MMU_TAG_INITIALIZER(11, 0x40020000, MPC55XX_MMU_64K, 0, 1, 1, 0), |
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92 | MPC55XX_MMU_TAG_INITIALIZER(12, 0x40030000, MPC55XX_MMU_32K, 0, 1, 1, 0), |
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93 | MPC55XX_MMU_TAG_INITIALIZER(13, 0x40038000, MPC55XX_MMU_16K, 0, 1, 1, 0), |
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94 | /* Used as cache-inhibited area (ADC, DSPI queues) */ |
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95 | MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K, 0, 1, 1, 1), |
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96 | /* External Ethernet controller */ |
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97 | MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, MPC55XX_MMU_1K, 0, 1, 1, 1), |
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98 | /* External MRAM 128k */ |
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99 | MPC55XX_MMU_TAG_INITIALIZER(16, 0x3ffa0000, MPC55XX_MMU_128K, 0, 1, 1, 0), |
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100 | /* External ARCNET controller */ |
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101 | MPC55XX_MMU_TAG_INITIALIZER(17, 0x3ffc0000, MPC55XX_MMU_1K, 0, 1, 1, 1) |
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102 | /* Peripheral Bridge A-Registers on MMU-table pos 4 */ |
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103 | /* Peripheral Bridge B-Registers on MMU-table pos 0 */ |
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104 | #else |
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105 | /* Used as cache-inhibited area (ADC, DSPI queues) */ |
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106 | MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K, 0, 1, 1, 1), |
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107 | #endif |
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108 | #elif defined(MPC55XX_BOARD_MPC5674F_RSM6) |
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109 | #if defined(MPC55XX_NEEDS_LOW_LEVEL_INIT) |
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110 | /* Arguments macro: idx, addr, size, x, w, r, io */ |
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111 | |
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112 | /* Internal flash 4M */ |
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113 | /* First 64k unused, to detect NULL pointer access */ |
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114 | MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, MPC55XX_MMU_64K, 1, 0, 1, 0), |
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115 | MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, MPC55XX_MMU_64K, 1, 0, 1, 0), |
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116 | MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, MPC55XX_MMU_128K, 1, 0, 1, 0), |
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117 | MPC55XX_MMU_TAG_INITIALIZER(7, 0x00040000, MPC55XX_MMU_256K, 1, 0, 1, 0), |
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118 | MPC55XX_MMU_TAG_INITIALIZER(8, 0x00080000, MPC55XX_MMU_512K, 1, 0, 1, 0), |
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119 | MPC55XX_MMU_TAG_INITIALIZER(9, 0x00100000, MPC55XX_MMU_1M, 1, 0, 1, 0), |
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120 | MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, MPC55XX_MMU_2M, 1, 0, 1, 0), |
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121 | /* External MRAM 4M */ |
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122 | MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, MPC55XX_MMU_4M, 0, 1, 1, 0), |
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123 | /* Internal SRAM 256k */ |
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124 | MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_256K, 0, 1, 1, 0), |
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125 | MPC55XX_MMU_TAG_INITIALIZER(11, 0x40020000, MPC55XX_MMU_64K, 0, 1, 1, 0), |
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126 | MPC55XX_MMU_TAG_INITIALIZER(12, 0x40030000, MPC55XX_MMU_32K, 0, 1, 1, 0), |
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127 | MPC55XX_MMU_TAG_INITIALIZER(13, 0x40038000, MPC55XX_MMU_16K, 0, 1, 1, 0), |
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128 | /* Used as cache-inhibited area (ADC, DSPI queues) */ |
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129 | MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K, 0, 1, 1, 1), |
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130 | /* External FPGA */ |
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131 | MPC55XX_MMU_TAG_INITIALIZER(15, 0x21000000, MPC55XX_MMU_8M, 0, 1, 1, 1), |
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132 | #if defined(MPC55XX_BOARD_MPC5674F_RSM6_KOMA) |
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133 | /* External Ethernet controller */ |
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134 | MPC55XX_MMU_TAG_INITIALIZER(17, 0x23000000, MPC55XX_MMU_1K, 0, 1, 1, 1), |
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135 | #endif |
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136 | #else |
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137 | /* Used as cache-inhibited area (ADC, DSPI queues) */ |
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138 | MPC55XX_MMU_TAG_INITIALIZER(14, 0x4003c000, MPC55XX_MMU_16K, 0, 1, 1, 1), |
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139 | #endif |
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140 | #elif MPC55XX_CHIP_FAMILY == 564 |
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141 | /* Internal flash 1M */ |
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142 | MPC55XX_MMU_TAG_INITIALIZER(0, 0x00000000, MPC55XX_MMU_1M, 1, 0, 1, 0), |
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143 | /* IO */ |
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144 | MPC55XX_MMU_TAG_INITIALIZER(1, 0xffe00000, MPC55XX_MMU_2M, 0, 1, 1, 1), |
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145 | MPC55XX_MMU_TAG_INITIALIZER(2, 0xc3f00000, MPC55XX_MMU_1M, 0, 1, 1, 1), |
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146 | /* Internal SRAM 64k + 64k */ |
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147 | MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, MPC55XX_MMU_64K, 0, 1, 1, 0), |
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148 | MPC55XX_MMU_TAG_INITIALIZER(4, 0x50000000, MPC55XX_MMU_64K, 0, 1, 1, 0) |
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149 | #endif |
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150 | }; |
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151 | |
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152 | const size_t mpc55xx_start_config_mmu_count [] = { |
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153 | RTEMS_ARRAY_SIZE(mpc55xx_start_config_mmu) |
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154 | }; |
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