1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc55xx |
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5 | * |
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6 | * @brief EBI chip-select configuration. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <bsp/mpc55xx-config.h> |
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24 | |
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25 | #ifdef MPC55XX_HAS_EBI |
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26 | |
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27 | const struct EBI_CS_tag mpc55xx_start_config_ebi_cs [] = { |
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28 | #if defined(MPC55XX_BOARD_GWLCFM) |
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29 | /* CS0: External SRAM (16 bit, 1 wait states, 512kB, no burst) */ |
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30 | { |
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31 | { |
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32 | .B.BA = 0x20000000>>15, |
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33 | .B.PS = 1, |
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34 | .B.AD_MUX = 1, |
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35 | .B.WEBS = 1, |
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36 | .B.TBDIP = 0, |
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37 | .B.BI = 1, |
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38 | .B.V = 1 |
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39 | }, |
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40 | { |
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41 | .B.AM = 0x1fff0, |
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42 | .B.SCY = 1, |
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43 | .B.BSCY = 0 |
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44 | } |
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45 | }, |
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46 | /* CS1: External USB controller (16 bit, 3 wait states, 32kB, no burst) */ |
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47 | { |
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48 | { |
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49 | .B.BA = 0x22000000>>15, |
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50 | .B.PS = 1, |
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51 | .B.AD_MUX = 1, |
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52 | .B.WEBS = 0, |
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53 | .B.TBDIP = 0, |
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54 | .B.BI = 1, |
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55 | .B.V = 1 |
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56 | }, |
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57 | { |
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58 | .B.AM = 0x1ffff, |
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59 | .B.SCY = 3, |
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60 | .B.BSCY = 0 |
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61 | } |
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62 | }, |
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63 | /* CS2: Ethernet (16 bit, 2 wait states, 32kB, no burst) */ |
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64 | { |
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65 | { |
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66 | .B.BA = 0x22800000>>15, |
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67 | .B.PS = 1, |
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68 | .B.AD_MUX = 1, |
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69 | .B.WEBS = 1, |
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70 | .B.TBDIP = 0, |
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71 | .B.BI = 1, |
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72 | .B.V = 1 |
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73 | }, |
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74 | { |
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75 | .B.AM = 0x1ffff, |
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76 | .B.SCY = 1, |
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77 | .B.BSCY = 0 |
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78 | } |
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79 | }, |
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80 | { /* CS3: MOST Companion. */ |
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81 | { |
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82 | .B.BA = 0x23000000>>15, |
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83 | .B.PS = 1, |
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84 | .B.AD_MUX = 1, |
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85 | .B.WEBS = 0, |
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86 | .B.TBDIP = 0, |
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87 | .B.BI = 1, |
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88 | .B.V = 1 |
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89 | }, |
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90 | |
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91 | { |
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92 | .B.AM = 0x1fff0, |
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93 | .B.SCY = 1, |
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94 | .B.BSCY = 0 |
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95 | } |
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96 | } |
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97 | #elif defined(MPC55XX_BOARD_PHYCORE_MPC5554) |
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98 | /* CS0: External flash. */ |
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99 | { |
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100 | { .R = 0x20000003 }, /* Base 0x2000000, Burst Inhibit, Valid */ |
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101 | { .R = 0xff000050 } |
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102 | }, |
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103 | /* CS1: External synchronous burst mode SRAM. */ |
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104 | { |
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105 | { .R = 0x21000051 }, /* Base 0x2100000, 4-word Burst Enabled, Valid */ |
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106 | { .R = 0xff000000 } /* No wait states. */ |
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107 | }, |
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108 | /* CS2: External LAN91C111 */ |
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109 | { |
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110 | { .R = 0x22000003 }, /* Base 0x22000000, Burst inhibit, valid */ |
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111 | { .R = 0xff000010 } |
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112 | }, |
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113 | |
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114 | /* CS3: External FPGA */ |
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115 | { |
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116 | { .R = 0x23000003 }, /* Base 0x23000000, Burst inhibit, valid. */ |
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117 | { .R = 0xff000020 } |
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118 | } |
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119 | #elif defined(MPC55XX_BOARD_MPC5566EVB) |
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120 | /* CS0: External SRAM (2 wait states, 512kB, 4 word burst) */ |
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121 | { |
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122 | { |
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123 | .B.BA = 0, |
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124 | .B.PS = 1, |
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125 | .B.BL = 1, |
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126 | .B.WEBS = 0, |
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127 | .B.TBDIP = 0, |
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128 | .B.BI = 1, /* TODO: Enable burst */ |
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129 | .B.V = 1 |
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130 | }, |
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131 | |
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132 | { |
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133 | .B.AM = 0x1fff0, |
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134 | .B.SCY = 0, |
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135 | .B.BSCY = 0 |
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136 | } |
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137 | }, |
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138 | { { .R = 0 }, { .R = 0 } }, /* CS1: Unused. */ |
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139 | { { .R = 0 }, { .R = 0 } }, /* CS2: Unused. */ |
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140 | { /* CS3: ethernet? */ |
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141 | { |
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142 | .B.BA = 0x7fff, |
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143 | .B.PS = 1, |
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144 | .B.BL = 0, |
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145 | .B.WEBS = 0, |
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146 | .B.TBDIP = 0, |
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147 | .B.BI = 1, |
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148 | .B.V = 1 |
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149 | }, |
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150 | |
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151 | { |
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152 | .B.AM = 0x1ffff, |
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153 | .B.SCY = 1, |
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154 | .B.BSCY = 0 |
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155 | } |
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156 | } |
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157 | #endif |
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158 | }; |
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159 | |
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160 | const size_t mpc55xx_start_config_ebi_cs_count [] = { |
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161 | RTEMS_ARRAY_SIZE(mpc55xx_start_config_ebi_cs) |
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162 | }; |
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163 | |
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164 | #endif /* MPC55XX_HAS_EBI */ |
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