source: rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-config-clock.c @ 105ccdd5

4.115
Last change on this file since 105ccdd5 was a762dc2, checked in by Sebastian Huber <sebastian.huber@…>, on 01/23/12 at 10:19:22

Support for MPC5643L.

Rework of the start sequence to reduce the amount assembler code and to
support configuration tables which may be provided by the application.

  • Property mode set to 100644
File size: 2.7 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup mpc55xx
5 *
6 * @brief Clock and FMPLL configuration.
7 */
8
9/*
10 * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.com/license/LICENSE.
21 */
22
23#include <bsp/mpc55xx-config.h>
24
25BSP_START_TEXT_SECTION const mpc55xx_clock_config
26  mpc55xx_start_config_clock [1] = { {
27  #ifdef MPC55XX_HAS_FMPLL
28    .syncr_tmp = {
29      .B = {
30        .PREDIV = MPC55XX_FMPLL_PREDIV - 1,
31        .MFD = MPC55XX_FMPLL_MFD,
32        .RFD = 2,
33        .LOCEN = 1
34      }
35    },
36    .syncr_final = {
37      .B = {
38        .PREDIV = MPC55XX_FMPLL_PREDIV - 1,
39        .MFD = MPC55XX_FMPLL_MFD,
40        .RFD = 0,
41        .LOCEN = 1,
42        .LOLIRQ = 1,
43        .LOCIRQ = 1
44      }
45    }
46  #endif
47  #ifdef MPC55XX_HAS_FMPLL_ENHANCED
48    #define EPREDIV_VAL (MPC55XX_FMPLL_PREDIV-1)
49    #define EMFD_VAL    (MPC55XX_FMPLL_MFD-16)
50    #define VCO_CLK_REF (MPC55XX_FMPLL_REF_CLOCK/(EPREDIV_VAL+1))
51    #define VCO_CLK_OUT (VCO_CLK_REF*(EMFD_VAL+16))
52    #define ERFD_VAL    ((VCO_CLK_OUT/MPC55XX_FMPLL_CLK_OUT)-1)
53
54    .esyncr2_tmp = {
55      .B = {
56        .LOCEN = 0,
57        .LOLRE = 0,
58        .LOCRE = 0,
59        .LOLIRQ = 0,
60        .LOCIRQ = 0,
61        .ERATE = 0,
62        .EDEPTH = 0,
63        .ERFD = ERFD_VAL + 2 /* reduce output clock during init */
64      }
65    },
66    .esyncr2_final = {
67      .B = {
68        .LOCEN = 0,
69        .LOLRE = 0,
70        .LOCRE = 0,
71        .LOLIRQ = 0,
72        .LOCIRQ = 0,
73        .ERATE = 0,
74        #if MPC55XX_CHIP_TYPE / 10  == 567
75          .CLKCFG_DIS = 1,
76        #endif
77        .EDEPTH = 0,
78        .ERFD = ERFD_VAL /* nominal output clock after init */
79      }
80    },
81    .esyncr1_final = {
82      .B = {
83        .CLKCFG = 7,
84        .EPREDIV = EPREDIV_VAL,
85        .EMFD = EMFD_VAL
86      }
87    }
88  #endif
89  #ifdef MPC55XX_HAS_MODE_CONTROL
90    .fmpll = {
91      {
92        .cr = {
93          .B = { .IDF = 3, .ODF = 1, .NDIV = 48, .I_LOCK = 1, .PLL_ON = 1 }
94        }
95      },
96      {
97        .cr = {
98          .B = { .IDF = 3, .ODF = 2, .NDIV = 32, .I_LOCK = 1, .PLL_ON = 1 }
99        }
100      }
101    },
102    .ocds_sc = {
103      .B = { .SELDIV = 2, .SELCTL = 2 }
104    },
105    .auxclk = {
106      [1] = {
107        .AC_SC = { .B = { .SELCTL = 4 } },
108        .AC_DC0_3 = { .B = { .DE0 = 1, .DIV0 = 11 } }
109      },
110      [2] = {
111        .AC_SC = { .B = { .SELCTL = 4 } },
112        .AC_DC0_3 = { .B = { .DE0 = 1, .DIV0 = 11 } }
113      },
114      [3] = {
115        .AC_SC = { .B = { .SELCTL = 1 } }
116      },
117      [4] = {
118        .AC_SC = { .B = { .SELCTL = 1 } }
119      }
120    }
121  #endif
122} };
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