[a762dc2] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup mpc55xx |
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| 5 | * |
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| 6 | * @brief Clock and FMPLL configuration. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. |
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| 11 | * |
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| 12 | * embedded brains GmbH |
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| 13 | * Obere Lagerstr. 30 |
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| 14 | * 82178 Puchheim |
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| 15 | * Germany |
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| 16 | * <rtems@embedded-brains.de> |
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| 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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| 20 | * http://www.rtems.com/license/LICENSE. |
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| 21 | */ |
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| 22 | |
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| 23 | #include <bsp/mpc55xx-config.h> |
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| 24 | |
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| 25 | BSP_START_TEXT_SECTION const mpc55xx_clock_config |
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| 26 | mpc55xx_start_config_clock [1] = { { |
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| 27 | #ifdef MPC55XX_HAS_FMPLL |
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| 28 | .syncr_tmp = { |
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| 29 | .B = { |
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| 30 | .PREDIV = MPC55XX_FMPLL_PREDIV - 1, |
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| 31 | .MFD = MPC55XX_FMPLL_MFD, |
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| 32 | .RFD = 2, |
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| 33 | .LOCEN = 1 |
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| 34 | } |
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| 35 | }, |
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| 36 | .syncr_final = { |
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| 37 | .B = { |
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| 38 | .PREDIV = MPC55XX_FMPLL_PREDIV - 1, |
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| 39 | .MFD = MPC55XX_FMPLL_MFD, |
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| 40 | .RFD = 0, |
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| 41 | .LOCEN = 1, |
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| 42 | .LOLIRQ = 1, |
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| 43 | .LOCIRQ = 1 |
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| 44 | } |
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| 45 | } |
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| 46 | #endif |
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| 47 | #ifdef MPC55XX_HAS_FMPLL_ENHANCED |
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| 48 | #define EPREDIV_VAL (MPC55XX_FMPLL_PREDIV-1) |
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| 49 | #define EMFD_VAL (MPC55XX_FMPLL_MFD-16) |
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| 50 | #define VCO_CLK_REF (MPC55XX_FMPLL_REF_CLOCK/(EPREDIV_VAL+1)) |
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| 51 | #define VCO_CLK_OUT (VCO_CLK_REF*(EMFD_VAL+16)) |
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| 52 | #define ERFD_VAL ((VCO_CLK_OUT/MPC55XX_FMPLL_CLK_OUT)-1) |
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| 53 | |
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| 54 | .esyncr2_tmp = { |
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| 55 | .B = { |
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| 56 | .LOCEN = 0, |
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| 57 | .LOLRE = 0, |
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| 58 | .LOCRE = 0, |
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| 59 | .LOLIRQ = 0, |
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| 60 | .LOCIRQ = 0, |
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| 61 | .ERATE = 0, |
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| 62 | .EDEPTH = 0, |
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| 63 | .ERFD = ERFD_VAL + 2 /* reduce output clock during init */ |
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| 64 | } |
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| 65 | }, |
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| 66 | .esyncr2_final = { |
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| 67 | .B = { |
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| 68 | .LOCEN = 0, |
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| 69 | .LOLRE = 0, |
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| 70 | .LOCRE = 0, |
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| 71 | .LOLIRQ = 0, |
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| 72 | .LOCIRQ = 0, |
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| 73 | .ERATE = 0, |
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| 74 | #if MPC55XX_CHIP_TYPE / 10 == 567 |
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| 75 | .CLKCFG_DIS = 1, |
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| 76 | #endif |
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| 77 | .EDEPTH = 0, |
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| 78 | .ERFD = ERFD_VAL /* nominal output clock after init */ |
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| 79 | } |
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| 80 | }, |
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| 81 | .esyncr1_final = { |
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| 82 | .B = { |
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| 83 | .CLKCFG = 7, |
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| 84 | .EPREDIV = EPREDIV_VAL, |
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| 85 | .EMFD = EMFD_VAL |
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| 86 | } |
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| 87 | } |
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| 88 | #endif |
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| 89 | #ifdef MPC55XX_HAS_MODE_CONTROL |
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| 90 | .fmpll = { |
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| 91 | { |
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| 92 | .cr = { |
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| 93 | .B = { .IDF = 3, .ODF = 1, .NDIV = 48, .I_LOCK = 1, .PLL_ON = 1 } |
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| 94 | } |
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| 95 | }, |
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| 96 | { |
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| 97 | .cr = { |
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| 98 | .B = { .IDF = 3, .ODF = 2, .NDIV = 32, .I_LOCK = 1, .PLL_ON = 1 } |
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| 99 | } |
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| 100 | } |
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| 101 | }, |
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| 102 | .ocds_sc = { |
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| 103 | .B = { .SELDIV = 2, .SELCTL = 2 } |
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| 104 | }, |
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| 105 | .auxclk = { |
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| 106 | [1] = { |
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| 107 | .AC_SC = { .B = { .SELCTL = 4 } }, |
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| 108 | .AC_DC0_3 = { .B = { .DE0 = 1, .DIV0 = 11 } } |
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| 109 | }, |
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| 110 | [2] = { |
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| 111 | .AC_SC = { .B = { .SELCTL = 4 } }, |
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| 112 | .AC_DC0_3 = { .B = { .DE0 = 1, .DIV0 = 11 } } |
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| 113 | }, |
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| 114 | [3] = { |
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| 115 | .AC_SC = { .B = { .SELCTL = 1 } } |
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| 116 | }, |
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| 117 | [4] = { |
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| 118 | .AC_SC = { .B = { .SELCTL = 1 } } |
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| 119 | } |
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| 120 | } |
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| 121 | #endif |
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| 122 | } }; |
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