1 | /** |
---|
2 | * @file |
---|
3 | * |
---|
4 | * @ingroup mpc55xx |
---|
5 | * |
---|
6 | * @brief Clock and FMPLL initialization code. |
---|
7 | */ |
---|
8 | |
---|
9 | /* |
---|
10 | * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. |
---|
11 | * |
---|
12 | * embedded brains GmbH |
---|
13 | * Obere Lagerstr. 30 |
---|
14 | * 82178 Puchheim |
---|
15 | * Germany |
---|
16 | * <rtems@embedded-brains.de> |
---|
17 | * |
---|
18 | * The license and distribution terms for this file may be |
---|
19 | * found in the file LICENSE in this distribution or at |
---|
20 | * http://www.rtems.com/license/LICENSE. |
---|
21 | */ |
---|
22 | |
---|
23 | #include <bsp.h> |
---|
24 | #include <bsp/start.h> |
---|
25 | #include <bsp/bootcard.h> |
---|
26 | #include <bsp/mpc55xx-config.h> |
---|
27 | |
---|
28 | #if defined(MPC55XX_HAS_FMPLL) || defined(MPC55XX_HAS_FMPLL_ENHANCED) |
---|
29 | static BSP_START_TEXT_SECTION void fmpll_wait_for_lock(void) |
---|
30 | { |
---|
31 | int i = 0; |
---|
32 | bool lock = false; |
---|
33 | |
---|
34 | while (!lock && i < 6000) { |
---|
35 | lock = FMPLL.SYNSR.B.LOCK != 0; |
---|
36 | ++i; |
---|
37 | } |
---|
38 | |
---|
39 | if (!lock) { |
---|
40 | bsp_reset(); |
---|
41 | } |
---|
42 | } |
---|
43 | #endif |
---|
44 | |
---|
45 | BSP_START_TEXT_SECTION void mpc55xx_start_clock(void) |
---|
46 | { |
---|
47 | const mpc55xx_clock_config *cfg = mpc55xx_start_config_clock; |
---|
48 | |
---|
49 | #ifdef MPC55XX_HAS_FMPLL |
---|
50 | volatile struct FMPLL_tag *fmpll = &FMPLL; |
---|
51 | |
---|
52 | fmpll->SYNCR.R = cfg->syncr_tmp.R; |
---|
53 | fmpll->SYNCR.R; |
---|
54 | fmpll_wait_for_lock(); |
---|
55 | |
---|
56 | fmpll->SYNCR.R = cfg->syncr_final.R; |
---|
57 | fmpll->SYNCR.R; |
---|
58 | fmpll_wait_for_lock(); |
---|
59 | #endif |
---|
60 | |
---|
61 | #ifdef MPC55XX_HAS_FMPLL_ENHANCED |
---|
62 | volatile struct FMPLL_tag *fmpll = &FMPLL; |
---|
63 | |
---|
64 | fmpll->ESYNCR2.R = cfg->esyncr2_tmp.R; |
---|
65 | fmpll->ESYNCR2.R; |
---|
66 | fmpll->ESYNCR1.R = cfg->esyncr1_final.R; |
---|
67 | fmpll->ESYNCR1.R; |
---|
68 | fmpll_wait_for_lock(); |
---|
69 | |
---|
70 | fmpll->ESYNCR2.R = cfg->esyncr2_final.R; |
---|
71 | fmpll->ESYNCR2.R; |
---|
72 | fmpll_wait_for_lock(); |
---|
73 | |
---|
74 | #if MPC55XX_CHIP_TYPE / 10 == 551 |
---|
75 | /* System clock supplied by PLL */ |
---|
76 | SIU.SYSCLK.B.SYSCLKSEL = 2; |
---|
77 | #endif |
---|
78 | #endif |
---|
79 | |
---|
80 | #ifdef MPC55XX_HAS_MODE_CONTROL |
---|
81 | volatile CGM_tag *cgm = &CGM; |
---|
82 | size_t fmpll_count = sizeof(cfg->fmpll) / sizeof(cfg->fmpll [0]); |
---|
83 | size_t auxclk_count = sizeof(cfg->auxclk) / sizeof(cfg->auxclk [0]); |
---|
84 | size_t i = 0; |
---|
85 | |
---|
86 | for (i = 0; i < auxclk_count; ++i) { |
---|
87 | cgm->AUXCLK [i].AC_SC.R = cfg->auxclk [i].AC_SC.R; |
---|
88 | cgm->AUXCLK [i].AC_DC0_3.R = cfg->auxclk [i].AC_DC0_3.R; |
---|
89 | } |
---|
90 | |
---|
91 | for (i = 0; i < fmpll_count; ++i) { |
---|
92 | cgm->FMPLL [i].CR.R = cfg->fmpll [i].cr.R; |
---|
93 | cgm->FMPLL [i].MR.R = cfg->fmpll [i].mr.R; |
---|
94 | } |
---|
95 | |
---|
96 | cgm->OC_EN.R = cfg->oc_en.R; |
---|
97 | cgm->OCDS_SC.R = cfg->ocds_sc.R; |
---|
98 | #endif |
---|
99 | } |
---|