source: rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-cache.S @ dafacfa7

4.115
Last change on this file since dafacfa7 was 32ec0f6b, checked in by Sebastian Huber <sebastian.huber@…>, on 07/17/12 at 14:56:58

bsp/mpc55xx: Add MPC55XX_NEEDS_LOW_LEVEL_INIT
  • Property mode set to 100644
File size: 2.2 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup mpc55xx_asm
5 *
6 * @brief Cache initialization.
7 */
8
9/*
10 * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.com/license/LICENSE.
21 */
22
23#include <libcpu/powerpc-utility.h>
24
25#include <mpc55xx/regs.h>
26
27        .globl  mpc55xx_start_cache
28
29        .section        ".bsp_start_text", "ax"
30
31mpc55xx_start_cache:
32
33#ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT
34
35        /* Load zero, CINV, and CABT) */
36        li      r0, 0
37        li      r3, 0x2
38        li      r4, 0x4
39
40#if defined(BSP_INSTRUCTION_CACHE_ENABLED) \
41  && defined(MPC55XX_HAS_INSTRUCTION_CACHE)
42
43start_instruction_cache_invalidation:
44
45        /* Clear instruction cache invalidation abort */
46        mtspr   FSL_EIS_L1CSR1, r0
47
48        /* Start instruction cache invalidation */
49        mtspr   FSL_EIS_L1CSR1, r3
50
51get_instruction_cache_invalidation_status:
52
53        /* Get instruction cache invalidation status */
54        mfspr   r5, FSL_EIS_L1CSR1
55
56        /* Check CABT */
57        and.    r6, r5, r4
58        bne     start_instruction_cache_invalidation
59
60        /* Check CINV */
61        and.    r6, r5, r3
62        bne     get_instruction_cache_invalidation_status
63
64        /* Save instruction cache settings */
65        LWI     r6, 0x00010001
66        isync
67        msync
68        mtspr   FSL_EIS_L1CSR1, r6
69
70#endif
71
72#if (defined(BSP_DATA_CACHE_ENABLED) && defined(MPC55XX_HAS_DATA_CACHE)) \
73  || ((defined(BSP_DATA_CACHE_ENABLED) \
74    || defined(BSP_INSTRUCTION_CACHE_ENABLED)) \
75      && defined(MPC55XX_HAS_UNIFIED_CACHE))
76
77start_data_cache_invalidation:
78
79        /* Clear data cache invalidation abort */
80        mtspr   FSL_EIS_L1CSR0, r0
81
82        /* Start data cache invalidation */
83        mtspr   FSL_EIS_L1CSR0, r3
84
85get_data_cache_invalidation_status:
86
87        /* Get data cache invalidation status */
88        mfspr   r5, FSL_EIS_L1CSR0
89
90        /* Check CABT */
91        and.    r6, r5, r4
92        bne     start_data_cache_invalidation
93
94        /* Check CINV */
95        and.    r6, r5, r3
96        bne     get_data_cache_invalidation_status
97
98        /* Save data cache settings */
99#if MPC55XX_CHIP_TYPE / 10 != 567
100        /* FIXME: CORG??? 0x00180011 */
101        LWI     r6, 0x00100001
102#else
103        LWI     r6, 0x00190001
104#endif
105        isync
106        msync
107        mtspr   FSL_EIS_L1CSR0, r6
108
109#endif
110
111#endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */
112
113        /* Return */
114        blr
Note: See TracBrowser for help on using the repository browser.