1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc55xx_asm |
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5 | * |
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6 | * @brief Cache initialization. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.com/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <libcpu/powerpc-utility.h> |
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24 | |
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25 | #include <mpc55xx/regs.h> |
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26 | |
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27 | .globl mpc55xx_start_cache |
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28 | |
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29 | .section ".bsp_start_text", "ax" |
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30 | |
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31 | mpc55xx_start_cache: |
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32 | |
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33 | #ifdef MPC55XX_NEEDS_LOW_LEVEL_INIT |
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34 | |
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35 | /* Load zero, CINV, and CABT) */ |
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36 | li r0, 0 |
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37 | li r3, 0x2 |
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38 | li r4, 0x4 |
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39 | |
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40 | #if defined(BSP_INSTRUCTION_CACHE_ENABLED) \ |
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41 | && defined(MPC55XX_HAS_INSTRUCTION_CACHE) |
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42 | |
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43 | start_instruction_cache_invalidation: |
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44 | |
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45 | /* Clear instruction cache invalidation abort */ |
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46 | mtspr FSL_EIS_L1CSR1, r0 |
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47 | |
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48 | /* Start instruction cache invalidation */ |
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49 | mtspr FSL_EIS_L1CSR1, r3 |
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50 | |
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51 | get_instruction_cache_invalidation_status: |
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52 | |
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53 | /* Get instruction cache invalidation status */ |
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54 | mfspr r5, FSL_EIS_L1CSR1 |
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55 | |
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56 | /* Check CABT */ |
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57 | and. r6, r5, r4 |
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58 | bne start_instruction_cache_invalidation |
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59 | |
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60 | /* Check CINV */ |
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61 | and. r6, r5, r3 |
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62 | bne get_instruction_cache_invalidation_status |
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63 | |
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64 | /* Save instruction cache settings */ |
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65 | LWI r6, 0x00010001 |
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66 | isync |
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67 | msync |
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68 | mtspr FSL_EIS_L1CSR1, r6 |
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69 | |
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70 | #endif |
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71 | |
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72 | #if (defined(BSP_DATA_CACHE_ENABLED) && defined(MPC55XX_HAS_DATA_CACHE)) \ |
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73 | || ((defined(BSP_DATA_CACHE_ENABLED) \ |
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74 | || defined(BSP_INSTRUCTION_CACHE_ENABLED)) \ |
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75 | && defined(MPC55XX_HAS_UNIFIED_CACHE)) |
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76 | |
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77 | start_data_cache_invalidation: |
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78 | |
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79 | /* Clear data cache invalidation abort */ |
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80 | mtspr FSL_EIS_L1CSR0, r0 |
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81 | |
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82 | /* Start data cache invalidation */ |
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83 | mtspr FSL_EIS_L1CSR0, r3 |
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84 | |
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85 | get_data_cache_invalidation_status: |
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86 | |
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87 | /* Get data cache invalidation status */ |
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88 | mfspr r5, FSL_EIS_L1CSR0 |
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89 | |
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90 | /* Check CABT */ |
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91 | and. r6, r5, r4 |
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92 | bne start_data_cache_invalidation |
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93 | |
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94 | /* Check CINV */ |
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95 | and. r6, r5, r3 |
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96 | bne get_data_cache_invalidation_status |
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97 | |
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98 | /* Save data cache settings */ |
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99 | #if MPC55XX_CHIP_TYPE / 10 != 567 |
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100 | /* FIXME: CORG??? 0x00180011 */ |
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101 | LWI r6, 0x00100001 |
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102 | #else |
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103 | LWI r6, 0x00190001 |
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104 | #endif |
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105 | isync |
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106 | msync |
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107 | mtspr FSL_EIS_L1CSR0, r6 |
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108 | |
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109 | #endif |
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110 | |
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111 | #endif /* MPC55XX_NEEDS_LOW_LEVEL_INIT */ |
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112 | |
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113 | /* Return */ |
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114 | blr |
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