source: rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/start-cache.S @ 105ccdd5

4.115
Last change on this file since 105ccdd5 was a880c90, checked in by Sebastian Huber <sebastian.huber@…>, on 05/18/12 at 13:41:56

powerpc/mpc55xxevb: Fix cache define usage
  • Property mode set to 100644
File size: 2.1 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup mpc55xx_asm
5 *
6 * @brief Cache initialization.
7 */
8
9/*
10 * Copyright (c) 2008-2012 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.com/license/LICENSE.
21 */
22
23#include <libcpu/powerpc-utility.h>
24
25#include <mpc55xx/regs.h>
26
27        .globl  mpc55xx_start_cache
28
29        .section        ".bsp_start_text", "ax"
30
31mpc55xx_start_cache:
32
33        /* Load zero, CINV, and CABT) */
34        li      r0, 0
35        li      r3, 0x2
36        li      r4, 0x4
37
38#if defined(BSP_INSTRUCTION_CACHE_ENABLED) \
39  && defined(MPC55XX_HAS_INSTRUCTION_CACHE)
40
41start_instruction_cache_invalidation:
42
43        /* Clear instruction cache invalidation abort */
44        mtspr   FSL_EIS_L1CSR1, r0
45
46        /* Start instruction cache invalidation */
47        mtspr   FSL_EIS_L1CSR1, r3
48
49get_instruction_cache_invalidation_status:
50
51        /* Get instruction cache invalidation status */
52        mfspr   r5, FSL_EIS_L1CSR1
53
54        /* Check CABT */
55        and.    r6, r5, r4
56        bne     start_instruction_cache_invalidation
57
58        /* Check CINV */
59        and.    r6, r5, r3
60        bne     get_instruction_cache_invalidation_status
61
62        /* Save instruction cache settings */
63        LWI     r6, 0x00010001
64        isync
65        msync
66        mtspr   FSL_EIS_L1CSR1, r6
67
68#endif
69
70#if (defined(BSP_DATA_CACHE_ENABLED) && defined(MPC55XX_HAS_DATA_CACHE)) \
71  || ((defined(BSP_DATA_CACHE_ENABLED) \
72    || defined(BSP_INSTRUCTION_CACHE_ENABLED)) \
73      && defined(MPC55XX_HAS_UNIFIED_CACHE))
74
75start_data_cache_invalidation:
76
77        /* Clear data cache invalidation abort */
78        mtspr   FSL_EIS_L1CSR0, r0
79
80        /* Start data cache invalidation */
81        mtspr   FSL_EIS_L1CSR0, r3
82
83get_data_cache_invalidation_status:
84
85        /* Get data cache invalidation status */
86        mfspr   r5, FSL_EIS_L1CSR0
87
88        /* Check CABT */
89        and.    r6, r5, r4
90        bne     start_data_cache_invalidation
91
92        /* Check CINV */
93        and.    r6, r5, r3
94        bne     get_data_cache_invalidation_status
95
96        /* Save data cache settings */
97#if MPC55XX_CHIP_TYPE / 10 != 567
98        /* FIXME: CORG??? 0x00180011 */
99        LWI     r6, 0x00100001
100#else
101        LWI     r6, 0x00190001
102#endif
103        isync
104        msync
105        mtspr   FSL_EIS_L1CSR0, r6
106
107#endif
108
109        /* Return */
110        blr
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