1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc55xx |
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5 | * |
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6 | * @brief MPC55XX MMU configuration. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.com/license/LICENSE. |
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21 | * |
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22 | * $Id$ |
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23 | */ |
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24 | |
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25 | #include <bsp/mpc55xx-config.h> |
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26 | #include <bsp/start.h> |
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27 | #include <bsp.h> |
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28 | |
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29 | const BSP_START_TEXT_SECTION struct MMU_tag |
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30 | mpc55xx_mmu_config [] = { |
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31 | #if defined(MPC55XX_BOARD_GWLCFM) |
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32 | /* External Ethernet Controller 64k */ |
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33 | MPC55XX_MMU_TAG_INITIALIZER(5, 0x3fff8000, 6, 0, 1, 1, 1) |
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34 | #elif defined(MPC55XX_BOARD_PHYCORE_MPC5554) |
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35 | /* XXX I'm not using TLB1 entry 2 the same way as |
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36 | * in the BAM. |
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37 | */ |
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38 | /* Set up MMU TLB1 entry 2 for external ram. */ |
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39 | /* Effective Base address = 0x2100_0000 XXX NOT LIKE BAM */ |
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40 | /* Real Base address = 0x2100_0000 XXX NOT LIKE BAM */ |
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41 | /* Page Size 6 = 4MB XXX Not like BAM */ |
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42 | /* Not Guarded, Cache Enable, All Access (0, 3F) */ |
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43 | { |
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44 | { .R = 0x10020000}, /* MAS0 */ |
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45 | { .R = 0xC0000600}, /* MAS1 */ |
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46 | { .R = 0x21000000}, /* MAS2 */ |
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47 | { .R = 0x2100003F} /* MAS3 */ |
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48 | }, |
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49 | |
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50 | /* Set up MMU TLB1 entry 5 for second half of SRAM (debug RAM) */ |
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51 | /* Effective Base address = 0x2140_0000 */ |
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52 | /* Real Base address = 0x2140_0000 */ |
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53 | /* Page Size 6 = 4MB */ |
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54 | /* Not Guarded, Cache Enable, All Access (0, 3F) */ |
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55 | { |
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56 | { .R = 0x10050000 }, /* MAS0 */ |
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57 | { .R = 0xC0000600 }, /* MAS1 */ |
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58 | { .R = 0x21400000 }, /* MAS2 */ |
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59 | { .R = 0x2140003F } /* MAS3 */ |
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60 | }, |
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61 | /* Set up MMU TLB1 entry 6 for External LAN91C111 */ |
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62 | /* Effective Base address = 0x2200_0000 */ |
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63 | /* Real Base address = 0x2200_0000 */ |
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64 | /* Page Size 7 = 16MB */ |
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65 | /* Write-through, Guarded, Cache Inhibit, All Access (E, 3F) */ |
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66 | { |
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67 | { .R = 0x10060000}, /* MAS0 */ |
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68 | { .R = 0xC0000700}, /* MAS1 */ |
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69 | { .R = 0x2200000E}, /* MAS2 */ |
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70 | { .R = 0x2200003F} /* MAS3 */ |
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71 | }, |
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72 | |
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73 | /* Set up MMU TLB1 entry 7 for External FPGA */ |
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74 | /* Effective Base address = 0x2300_0000 */ |
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75 | /* Real Base address = 0x2300_0000 */ |
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76 | /* Page Size 7 = 16MB */ |
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77 | /* Write-through, Guarded, Cache Inhibit, All Access (E, 3F) */ |
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78 | { |
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79 | { .R = 0x10070000}, /* MAS0 */ |
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80 | { .R = 0xC0000700}, /* MAS1 */ |
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81 | { .R = 0x2300000E}, /* MAS2 */ |
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82 | { .R = 0x2300003F}, /* MAS3 */ |
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83 | }, |
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84 | |
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85 | /* Should also set up maps for the debug RAM and the |
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86 | * external flash. |
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87 | */ |
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88 | #elif defined(MPC55XX_BOARD_MPC5566EVB) |
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89 | /* Internal flash 3M */ |
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90 | MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, 6, 1, 0, 1, 0), |
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91 | MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, 6, 1, 0, 1, 0), |
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92 | MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, 6, 1, 0, 1, 0), |
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93 | MPC55XX_MMU_TAG_INITIALIZER(7, 0x00030000, 6, 1, 0, 1, 0), |
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94 | MPC55XX_MMU_TAG_INITIALIZER(8, 0x00040000, 8, 1, 0, 1, 0), |
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95 | MPC55XX_MMU_TAG_INITIALIZER(9, 0x00080000, 8, 1, 0, 1, 0), |
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96 | MPC55XX_MMU_TAG_INITIALIZER(10, 0x000c0000, 8, 1, 0, 1, 0), |
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97 | MPC55XX_MMU_TAG_INITIALIZER(11, 0x00100000, 10, 1, 0, 1, 0), |
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98 | MPC55XX_MMU_TAG_INITIALIZER(12, 0x00200000, 10, 1, 0, 1, 0), |
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99 | /* External SRAM 512k */ |
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100 | MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, 8, 0, 1, 1, 0), |
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101 | MPC55XX_MMU_TAG_INITIALIZER(13, 0x20040000, 8, 0, 1, 1, 0), |
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102 | /* Internal SRAM 128k */ |
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103 | MPC55XX_MMU_TAG_INITIALIZER(3, 0x40010000, 6, 0, 1, 1, 0), |
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104 | MPC55XX_MMU_TAG_INITIALIZER(14, 0x40000000, 6, 0, 1, 1, 0), |
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105 | /* External Ethernet Controller 64k */ |
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106 | MPC55XX_MMU_TAG_INITIALIZER(15, 0x3fff8000, 6, 0, 1, 1, 1) |
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107 | #elif defined(MPC55XX_BOARD_MPC5674FEVB) |
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108 | /* Internal flash 4M */ |
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109 | MPC55XX_MMU_TAG_INITIALIZER(1, 0x00000000, 6, 1, 0, 1, 0), |
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110 | MPC55XX_MMU_TAG_INITIALIZER(5, 0x00010000, 6, 1, 0, 1, 0), |
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111 | MPC55XX_MMU_TAG_INITIALIZER(6, 0x00020000, 7, 1, 0, 1, 0), |
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112 | MPC55XX_MMU_TAG_INITIALIZER(7, 0x00040000, 8, 1, 0, 1, 0), |
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113 | MPC55XX_MMU_TAG_INITIALIZER(8, 0x00080000, 9, 1, 0, 1, 0), |
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114 | MPC55XX_MMU_TAG_INITIALIZER(9, 0x00100000, 10, 1, 0, 1, 0), |
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115 | MPC55XX_MMU_TAG_INITIALIZER(10, 0x00200000, 11, 1, 0, 1, 0), |
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116 | /* External SRAM 512k */ |
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117 | MPC55XX_MMU_TAG_INITIALIZER(2, 0x20000000, 9, 0, 1, 1, 0), |
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118 | /* Internal SRAM 256k */ |
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119 | MPC55XX_MMU_TAG_INITIALIZER(3, 0x40000000, 8, 0, 1, 1, 0) |
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120 | #endif |
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121 | }; |
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122 | |
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123 | const BSP_START_TEXT_SECTION size_t mpc55xx_mmu_config_count [] = { |
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124 | sizeof(mpc55xx_mmu_config) / sizeof(mpc55xx_mmu_config [0]) |
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125 | }; |
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