source: rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/ebi-cs-config.c @ 9e7758b

4.115
Last change on this file since 9e7758b was 9e7758b, checked in by Sebastian Huber <sebastian.huber@…>, on 08/31/11 at 16:03:10

2011-08-31 Sebastian Huber <sebastian.huber@…>

  • startup/bspgetworkarea.c, startup/linkcmds.base: Removed files.
  • include/mpc55xx-config.h, make/custom/mpc5674fevb.cfg, startup/early-init.c, startup/ebi-cal-cs-config.c, startup/ebi-cs-config.c, startup/exc-vector-base.S, startup/fmpll-syncr-vals.c, startup/linkcmds.mpc5674fevb, startup/mmu-config.c, startup/siu-pcr-config.c: New files.
  • Makefile.am, preinstall.am: Reflect changes above.
  • startup/linkcmds.gwlcfm, startup/linkcmds.mpc5566evb, startup/linkcmds.phycore_mpc5554: Use linker command base file.
  • configure.ac: Support MPC5674F. Changed eSCI options.
  • clock/clock-config.c: Support MPC5674F.
  • i2c/i2c_init.c, network/smsc9218i.c, startup/sd-card-init.c: Update due to API changes.
  • include/bsp.h: Define BSP_INTERRUPT_STACK_AT_WORK_AREA_BEGIN.
  • network/if_smc.c: Use HAS_SMC91111.
  • startup/start.S, startup/bspstart.c: Moved low-level initialization into new files. Overall cleanup.
  • Property mode set to 100644
File size: 3.7 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup mpc55xx
5 *
6 * @brief MPC55XX EBI chip-select configuration.
7 */
8
9/*
10 * Copyright (c) 2008-2011 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.com/license/LICENSE.
21 *
22 * $Id$
23 */
24
25#include <bsp/mpc55xx-config.h>
26#include <bsp/start.h>
27#include <bsp.h>
28
29const BSP_START_TEXT_SECTION struct EBI_CS_tag
30mpc55xx_ebi_cs_config [] = {
31#if defined(MPC55XX_BOARD_GWLCFM)
32        /* CS0: External SRAM (16 bit, 1 wait states, 512kB, no burst) */
33        {
34        {
35            .B.BA = 0x20000000>>15,
36            .B.PS = 1,
37            .B.AD_MUX = 1,
38            .B.WEBS = 1,
39            .B.TBDIP = 0,
40            .B.BI = 1,
41            .B.V = 1
42        },
43        {
44            .B.AM = 0x1fff0,
45            .B.SCY = 1,
46            .B.BSCY = 0
47        }
48    },
49        /* CS1: External USB controller (16 bit, 3 wait states, 32kB, no burst) */
50        {
51        {
52            .B.BA = 0x22000000>>15,
53            .B.PS = 1,
54            .B.AD_MUX = 1,
55            .B.WEBS = 0,
56            .B.TBDIP = 0,
57            .B.BI = 1,
58            .B.V = 1
59        },
60        {
61            .B.AM = 0x1ffff,
62            .B.SCY = 3,
63            .B.BSCY = 0
64        }
65    },
66        /* CS2: Ethernet (16 bit, 2 wait states, 32kB, no burst) */
67        {
68        {
69            .B.BA = 0x22800000>>15,
70            .B.PS = 1,
71            .B.AD_MUX = 1,
72            .B.WEBS = 1,
73            .B.TBDIP = 0,
74            .B.BI = 1,
75            .B.V = 1
76        },
77        {
78            .B.AM = 0x1ffff,
79            .B.SCY = 1,
80            .B.BSCY = 0
81        }
82    },
83    {                           /* CS3: MOST Companion. */
84        {
85            .B.BA = 0x23000000>>15,
86            .B.PS = 1,
87            .B.AD_MUX = 1,
88            .B.WEBS = 0,
89            .B.TBDIP = 0,
90            .B.BI = 1,
91            .B.V = 1
92        },
93
94        {
95            .B.AM = 0x1fff0,
96            .B.SCY = 1,
97            .B.BSCY = 0
98        }
99    }
100#elif defined(MPC55XX_BOARD_PHYCORE_MPC5554)
101    /* CS0: External flash. */
102    {
103        { .R = 0x20000003 },   /* Base 0x2000000, Burst Inhibit, Valid */
104        { .R = 0xff000050 }
105    },
106    /* CS1: External synchronous burst mode SRAM. */
107    {
108        { .R = 0x21000051 },   /* Base 0x2100000, 4-word Burst Enabled, Valid */
109        { .R = 0xff000000 }    /* No wait states. */
110    },
111    /* CS2: External LAN91C111 */
112    {
113        { .R = 0x22000003 },   /* Base 0x22000000, Burst inhibit, valid */
114        { .R = 0xff000010 }
115    },
116
117    /* CS3: External FPGA */
118    {
119        { .R = 0x23000003 },   /* Base 0x23000000, Burst inhibit, valid. */
120        { .R = 0xff000020 }
121    }
122#elif defined(MPC55XX_BOARD_MPC5566EVB)
123        /* CS0: External SRAM (2 wait states, 512kB, 4 word burst) */
124    {
125        {
126            .B.BA = 0,
127            .B.PS = 1,
128            .B.BL = 1,
129            .B.WEBS = 0,
130            .B.TBDIP = 0,
131            .B.BI = 1, /* TODO: Enable burst */
132            .B.V = 1
133        },
134
135        {
136            .B.AM = 0x1fff0,
137            .B.SCY = 0,
138            .B.BSCY = 0
139        }
140    },
141    { { .R = 0 }, { .R = 0 } },   /* CS1: Unused. */
142    { { .R = 0 }, { .R = 0 } },   /* CS2: Unused. */
143    {   /* CS3: ethernet? */
144        {
145            .B.BA = 0x7fff,
146            .B.PS = 1,
147            .B.BL = 0,
148            .B.WEBS = 0,
149            .B.TBDIP = 0,
150            .B.BI = 1,
151            .B.V = 1
152        },
153
154        {
155            .B.AM = 0x1ffff,
156            .B.SCY = 1,
157            .B.BSCY = 0
158        }
159    }
160#endif
161};
162
163const BSP_START_TEXT_SECTION size_t mpc55xx_ebi_cs_config_count [] = {
164  sizeof(mpc55xx_ebi_cs_config) / sizeof(mpc55xx_ebi_cs_config [0])
165};
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