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source: rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/startup/bspstart.c @ 95fe2fd

4.115

Last change on this file since 95fe2fd was a4475277, checked in by Sebastian Huber <sebastian.huber@…>, on 06/07/11 at 09:14:06

2011-06-07 Sebastian Huber <sebastian.huber@…>

clock/clock-config.c: Fixes to pass psnsext01.
startup/bspstart.c: Workaround for GCC 4.6 bug.
include/smsc9218i.h, network/smsc9218i.c, Makefile.am: Changes throughout.

Property mode set to 100644

File size: 18.7 KB

Line
1	/**
2	* @file
3	*
4	* @ingroup mpc55xx
5	*
6	* @brief BSP startup code.
7	*/
8
9	/*
10	* Copyright (c) 2008
11	* Embedded Brains GmbH
12	* Obere Lagerstr. 30
13	* D-82178 Puchheim
14	* Germany
15	* rtems@embedded-brains.de
16	*
17	* The license and distribution terms for this file may be found in the file
18	* LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
19	*/
20
21	#include <mpc55xx/mpc55xx.h>
22	#include <mpc55xx/regs.h>
23	#include <mpc55xx/edma.h>
24	#include <mpc55xx/emios.h>
25	#include <mpc55xx/siu.h>
26
27	#include <rtems.h>
28
29	#include <libcpu/powerpc-utility.h>
30	#include <bsp/vectors.h>
31
32	#include <bsp.h>
33	#include <bsp/bootcard.h>
34	#include <bsp/irq.h>
35	#include <bsp/irq-generic.h>
36
37	#define RTEMS_STATUS_CHECKS_USE_PRINTK
38
39	#include <rtems/status-checks.h>
40
41	#define DEBUG_DONE() RTEMS_DEBUG_PRINT( "Done\n")
42
43	#define MPC55XX_INTERRUPT_STACK_SIZE 0x1000
44
45	/* Symbols defined in linker command file */
46	LINKER_SYMBOL(bsp_ram_start);
47	LINKER_SYMBOL(bsp_ram_end);
48	LINKER_SYMBOL(bsp_external_ram_start);
49	LINKER_SYMBOL(bsp_external_ram_size);
50	LINKER_SYMBOL(bsp_section_bss_end);
51
52	unsigned int bsp_clock_speed = 0;
53
54	uint32_t bsp_clicks_per_usec = 0;
55
56	void BSP_panic( char *s)
57	{
58	rtems_interrupt_level level;
59
60	rtems_interrupt_disable( level);
61
62	printk( "%s PANIC %s\n", _RTEMS_version, s);
63
64	while (1) {
65	/* Do nothing */
66	}
67	}
68
69	void _BSP_Fatal_error( unsigned n)
70	{
71	rtems_interrupt_level level;
72
73	rtems_interrupt_disable( level);
74
75	printk( "%s PANIC ERROR %u\n", _RTEMS_version, n);
76
77	while (1) {
78	/* Do nothing */
79	}
80	}
81
82	void bsp_predriver_hook()
83	{
84	rtems_status_code sc = RTEMS_SUCCESSFUL;
85
86	RTEMS_DEBUG_PRINT( "Initialize eDMA ...\n");
87	sc = mpc55xx_edma_init();
88	if (sc != RTEMS_SUCCESSFUL) {
89	BSP_panic( "Cannot initialize eDMA");
90	} else {
91	DEBUG_DONE();
92	}
93	}
94
95	#if ((MPC55XX_CHIP_TYPE>=5510) && (MPC55XX_CHIP_TYPE<=5517))
96	/*
97	* define init values for FMPLL ESYNCRx
98	* (used in start.S/fmpll.S)
99	*/
100	#define EPREDIV_VAL (MPC55XX_FMPLL_PREDIV-1)
101	#define EMFD_VAL (MPC55XX_FMPLL_MFD-16)
102	#define VCO_CLK_REF (MPC55XX_FMPLL_REF_CLOCK/(EPREDIV_VAL+1))
103	#define VCO_CLK_OUT (VCO_CLK_REF*(EMFD_VAL+16))
104	#define ERFD_VAL ((VCO_CLK_OUT/MPC55XX_FMPLL_CLK_OUT)-1)
105
106	const struct fmpll_syncr_vals_t {
107	union ESYNCR2_tag esyncr2_temp;
108	union ESYNCR2_tag esyncr2_final;
109	union ESYNCR1_tag esyncr1_final;
110	} fmpll_syncr_vals =
111	{
112	{ /* esyncr2_temp */
113	.B.LOCEN=0,
114	.B.LOLRE=0,
115	.B.LOCRE=0,
116	.B.LOLIRQ=0,
117	.B.LOCIRQ=0,
118	.B.ERATE=0,
119	.B.DEPTH=0,
120	.B.ERFD=ERFD_VAL+2 /* reduce output clock during init */
121	},
122	{ /* esyncr2_final */
123	.B.LOCEN=0,
124	.B.LOLRE=0,
125	.B.LOCRE=0,
126	.B.LOLIRQ=0,
127	.B.LOCIRQ=0,
128	.B.ERATE=0,
129	.B.DEPTH=0,
130	.B.ERFD=ERFD_VAL /* nominal output clock after init */
131	},
132	{ /* esyncr1_final */
133	.B.CLKCFG=7,
134	.B.EPREDIV=EPREDIV_VAL,
135	.B.EMFD=EMFD_VAL
136	}
137	};
138
139	#else /* ((MPC55XX_CHIP_TYPE>=5510) && (MPC55XX_CHIP_TYPE<=5517)) */
140
141	const struct fmpll_syncr_vals_t {
142	union SYNCR_tag syncr_temp;
143	union SYNCR_tag syncr_final;
144	} fmpll_syncr_vals =
145	{
146	{ /* syncr_temp */
147	.B.PREDIV=MPC55XX_FMPLL_PREDIV-1,
148	.B.MFD=MPC55XX_FMPLL_MFD,
149	.B.RFD=2,
150	.B.LOCEN=1
151	},
152	{ /* syncr_final */
153	.B.PREDIV=MPC55XX_FMPLL_PREDIV-1,
154	.B.MFD=MPC55XX_FMPLL_MFD,
155	.B.RFD=0,
156	.B.LOCEN=1
157	}
158	};
159
160	#endif /* ((MPC55XX_CHIP_TYPE>=5510) && (MPC55XX_CHIP_TYPE<=5517)) */
161
162	#if defined(BOARD_GWLCFM)
163	static const mpc55xx_siu_pcr_entry_t siu_pcr_list[] = {
164	{ 0,16,{.B.PA = 1, .B.WPE = 0}}, /* PA[ 0..15] analog input */
165	{ 16, 4,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[ 0.. 4] LED/CAN_STBN out */
166	{ 20, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PB[ 5.. 6] CAN_ERR/USBFLGC in*/
167	{ 22, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[ 7 ] FR_A_EN out */
168	{ 23, 4,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PB[ 8..10] IRQ/FR_A_ERR/USB_RDYin */
169	{ 27, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[11..11] FR_STBN out */
170
171	{ 32, 2,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 0.. 1] FR_A_TX/TXEN out */
172	{ 34, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 2.. 2] FR_A_RX in */
173	{ 35, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 3.. 4] INIT_ERR/ISB_IRQ in */
174	{ 37, 2,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 5.. 6] PWRO1/2_ON out */
175	{ 39, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 7.. 7] FR_B_RX in */
176	{ 40, 2,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 8.. 9] FR_B_TX/TXEN out */
177	{ 42, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[10 ] FR_B_EN out */
178	{ 43, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[11 ] FOR_STATUS in */
179	{ 44, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[12 ] FR_B_ERRN in */
180	{ 45, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[13 ] HS_CAN_STBN out */
181	{ 46, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[14 ] HS_CAN_ERR in */
182	{ 47, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[15 ] HS_CAN_EN out */
183
184	{ 48, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 0 ] HS_CAN_TX out */
185	{ 49, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 1 ] HS_CAN_RX in */
186	{ 50, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 2.. 3] PWRO1/2_OC in */
187	{ 52, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 4 ] LS_CAN_TX out */
188	{ 53, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 5 ] LS_CAN_RX in */
189	{ 54, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 6 ] HS_CAN_TX out */
190	{ 55, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 7 ] HS_CAN_RX in */
191	{ 56, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
192	/* PD[ 8 ] I2C_SCL in/out */
193	{ 57, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}},
194	/* PD[ 9 ] I2C_SDA in/out */
195
196	{ 58, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PD[10] LS_CAN_EN out*/
197	{ 59, 3,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}},
198	/* PD[11..13] PWO1_OC, MOCO_INT in */
199
200	{ 62, 4,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PD[14..15] USB_FLGA/B in */
201
202	{ 64, 5,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PE[ 0.. 4] LED_EXT1-5. out*/
203	{ 70, 1,{.B.PA = 1,.B.SRC = 3,.B.WPE = 0}}, /* PE[ 6.. 6] CLKOUT out*/
204
205	{ 80, 1,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PF[ 0.. 0] RD_WR out*/
206	{ 81, 1,{.B.PA = 0,.B.SRC = 0,.B.WPE = 0}}, /* PF[ 1.. 1] (nc) in */
207	{ 82, 8,{.B.PA = 2,.B.SRC = 1,.B.WPE = 0}}, /* PF[ 2..11] ADDR[8..15] out*/
208	{ 90, 2,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PF[ 2..11] CS[0..1] out*/
209	{ 92, 1,{.B.PA = 3,.B.SRC = 3,.B.WPE = 0}}, /* PF[ 12] ALE out*/
210	{ 93, 3,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PF[13..15] OE/WE out*/
211
212	{ 96,16,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PG[ 0..15] AD16..31 in/out*/
213
214	{113, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 1.. 1] RES_MOSTComp out*/
215	{114, 1,{.B.PA = 3,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 2.. 2] CS3_MOSTComp out*/
216	{115, 1,{.B.PA = 3,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 3.. 3] CS2_ETH out*/
217	{116, 2,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 4.. 5] FR/HC_TERM out*/
218	{118, 1,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 6.. 6] LIN_Tx out*/
219	{119, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PH[ 7.. 7] LIN_Rx in */
220	{120, 4,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 8..11] LIN_SLP,RST out*/
221
222	{0,0}
223	};
224	#elif defined(BOARD_PHYCORE_MPC5554)
225
226	static const mpc55xx_siu_pcr_entry_t siu_pcr_list[] = {
227	{ 0, 4,{.B.PA = 1, .B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS [0:3] */
228	{ 4,24,{.B.PA = 1, .B.DSC = 1 }}, /* ADDR [8 : 31] */
229	{ 28,32,{.B.PA = 1, .B.DSC = 1 }}, /* DATA [0 : 31] */
230	{ 60, 4,{.B.PA = 1, .B.DSC = 1, }}, /* TSIZ[0:1], RD_!WR, BDIP */
231	{ 64, 6,{.B.PA = 1, .B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* RD_!WR, BDIP, !WE, !OE, !TS */
232	{ 89, 4,{.B.PA = 1 }}, /* ESCI_A and ESCI_B */
233	{229, 4,{ .B.OBE= 1,.B.DSC = 1 }}, /* CLKOUT */
234
235	{0,0}
236	};
237
238	#else /* MPC55xxEVB */
239
240	static const mpc55xx_siu_pcr_entry_t siu_pcr_list[] = {
241	{ 0, 1,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS [0] */
242	{ 3, 1,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS [3] */
243	{ 4,24,{.B.PA = 1,.B.DSC = 1 }}, /* ADDR [8 : 31] */
244	{ 28,16,{.B.PA = 1,.B.DSC = 1 }}, /* DATA [0 : 15] */
245	{ 62, 8,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* RD_!WR, BDIP,
246	!WE, !OE, !TS */
247	{ 89, 2,{.B.PA = 1 }}, /* ESCI_B */
248
249	{0,0}
250	};
251	#endif /* BOARD_GWLCFM */
252
253	/*
254	* Arrays for setting up the chip selects.
255	* You can define up to four, and those with the valid bit
256	* set will be loaded into the matching chip select.
257	*/
258	static const struct EBI_CS_tag cs_setup[] = {
259	#if defined(BOARD_GWLCFM)
260	/* CS0: External SRAM (16 bit, 1 wait states, 512kB, no burst) */
261	{
262	{
263	.B.BA = 0x20000000>>15,
264	.B.PS = 1,
265	.B.AD_MUX = 1,
266	.B.WEBS = 1,
267	.B.TBDIP = 0,
268	.B.BI = 1,
269	.B.V = 1
270	},
271	{
272	.B.AM = 0x1fff0,
273	.B.SCY = 1,
274	.B.BSCY = 0
275	}
276	},
277	/* CS1: External USB controller (16 bit, 3 wait states, 32kB, no burst) */
278	{
279	{
280	.B.BA = 0x22000000>>15,
281	.B.PS = 1,
282	.B.AD_MUX = 1,
283	.B.WEBS = 0,
284	.B.TBDIP = 0,
285	.B.BI = 1,
286	.B.V = 1
287	},
288	{
289	.B.AM = 0x1ffff,
290	.B.SCY = 3,
291	.B.BSCY = 0
292	}
293	},
294	/* CS2: Ethernet (16 bit, 2 wait states, 32kB, no burst) */
295	{
296	{
297	.B.BA = 0x22800000>>15,
298	.B.PS = 1,
299	.B.AD_MUX = 1,
300	.B.WEBS = 1,
301	.B.TBDIP = 0,
302	.B.BI = 1,
303	.B.V = 1
304	},
305	{
306	.B.AM = 0x1ffff,
307	.B.SCY = 1,
308	.B.BSCY = 0
309	}
310	},
311	{ /* CS3: MOST Companion. */
312	{
313	.B.BA = 0x23000000>>15,
314	.B.PS = 1,
315	.B.AD_MUX = 1,
316	.B.WEBS = 0,
317	.B.TBDIP = 0,
318	.B.BI = 1,
319	.B.V = 1
320	},
321
322	{
323	.B.AM = 0x1fff0,
324	.B.SCY = 1,
325	.B.BSCY = 0
326	}
327	}
328	#elif defined(BOARD_PHYCORE_MPC5554)
329	/* CS0: External flash. */
330	{
331	{ .R = 0x20000003 }, /* Base 0x2000000, Burst Inhibit, Valid */
332	{ .R = 0xff000050 }
333	},
334	/* CS1: External synchronous burst mode SRAM. */
335	{
336	{ .R = 0x21000051 }, /* Base 0x2100000, 4-word Burst Enabled, Valid */
337	{ .R = 0xff000000 } /* No wait states. */
338	},
339	/* CS2: External LAN91C111 */
340	{
341	{ .R = 0x22000003 }, /* Base 0x22000000, Burst inhibit, valid */
342	{ .R = 0xff000010 }
343	},
344
345	/* CS3: External FPGA */
346	{
347	{ .R = 0x23000003 }, /* Base 0x23000000, Burst inhibit, valid. */
348	{ .R = 0xff000020 }
349	}
350	#else /* default, MPC55xxEVB */
351	/* CS0: External SRAM (2 wait states, 512kB, 4 word burst) */
352	{
353	{
354	.B.BA = 0,
355	.B.PS = 1,
356	.B.BL = 1,
357	.B.WEBS = 0,
358	.B.TBDIP = 0,
359	.B.BI = 1, /* TODO: Enable burst */
360	.B.V = 1
361	},
362
363	{
364	.B.AM = 0x1fff0,
365	.B.SCY = 0,
366	.B.BSCY = 0
367	}
368	},
369	{ { .R = 0 }, { .R = 0 } }, /* CS1: Unused. */
370	{ { .R = 0 }, { .R = 0 } }, /* CS2: Unused. */
371	{ /* CS3: ethernet? */
372	{
373	.B.BA = 0x7fff,
374	.B.PS = 1,
375	.B.BL = 0,
376	.B.WEBS = 0,
377	.B.TBDIP = 0,
378	.B.BI = 1,
379	.B.V = 1
380	},
381
382	{
383	.B.AM = 0x1ffff,
384	.B.SCY = 1,
385	.B.BSCY = 0
386	}
387	}
388	#endif /* Chip select setup */
389	};
390
391	/*
392	* Arrays for setting up the MAS registers.
393	* You can set as many as you want,we determine the size using sizeof.
394	*/
395	static const struct MMU_tag mmu_setup[] = {
396	#if defined(BOARD_GWLCFM)
397	{
398	/* External Ethernet Controller (3 wait states, 64kB) */
399
400	{
401	.B.TLBSEL = 1, /* MAS0 */
402	.B.ESEL = 5
403	},
404	{
405	.B.VALID = 1, /* MAS1 */
406	.B.IPROT = 1,
407	.B.TSIZ = 1
408	},
409	{
410	.B.EPN = 0x3fff8, /* MAS2 */
411	.B.I = 1,
412	.B.G = 1
413	},
414	{
415	.B.RPN = 0x3fff8, /* MAS3 */
416	.B.UW = 1,
417	.B.SW = 1,
418	.B.UR = 1,
419	.B.SR = 1
420	}
421	}
422
423	#elif defined(BOARD_PHYCORE_MPC5554)
424
425	/* XXX I'm not using TLB1 entry 2 the same way as
426	* in the BAM.
427	*/
428	/* Set up MMU TLB1 entry 2 for external ram. */
429	/* Effective Base address = 0x2100_0000 XXX NOT LIKE BAM */
430	/* Real Base address = 0x2100_0000 XXX NOT LIKE BAM */
431	/* Page Size 6 = 4MB XXX Not like BAM */
432	/* Not Guarded, Cache Enable, All Access (0, 3F) */
433	{
434	{ .R = 0x10020000}, /* MAS0 */
435	{ .R = 0xC0000600}, /* MAS1 */
436	{ .R = 0x21000000}, /* MAS2 */
437	{ .R = 0x2100003F} /* MAS3 */
438	},
439
440	/* Set up MMU TLB1 entry 5 for second half of SRAM (debug RAM) */
441	/* Effective Base address = 0x2140_0000 */
442	/* Real Base address = 0x2140_0000 */
443	/* Page Size 6 = 4MB */
444	/* Not Guarded, Cache Enable, All Access (0, 3F) */
445	{
446	{ .R = 0x10050000 }, /* MAS0 */
447	{ .R = 0xC0000600 }, /* MAS1 */
448	{ .R = 0x21400000 }, /* MAS2 */
449	{ .R = 0x2140003F } /* MAS3 */
450	},
451	/* Set up MMU TLB1 entry 6 for External LAN91C111 */
452	/* Effective Base address = 0x2200_0000 */
453	/* Real Base address = 0x2200_0000 */
454	/* Page Size 7 = 16MB */
455	/* Write-through, Guarded, Cache Inhibit, All Access (E, 3F) */
456	{
457	{ .R = 0x10060000}, /* MAS0 */
458	{ .R = 0xC0000700}, /* MAS1 */
459	{ .R = 0x2200000E}, /* MAS2 */
460	{ .R = 0x2200003F} /* MAS3 */
461	},
462
463	/* Set up MMU TLB1 entry 7 for External FPGA */
464	/* Effective Base address = 0x2300_0000 */
465	/* Real Base address = 0x2300_0000 */
466	/* Page Size 7 = 16MB */
467	/* Write-through, Guarded, Cache Inhibit, All Access (E, 3F) */
468	{
469	{ .R = 0x10070000}, /* MAS0 */
470	{ .R = 0xC0000700}, /* MAS1 */
471	{ .R = 0x2300000E}, /* MAS2 */
472	{ .R = 0x2300003F}, /* MAS3 */
473	},
474
475	/* Should also set up maps for the debug RAM and the
476	* external flash.
477	*/
478	#else /* default, MPC55xxEVB */
479	{
480	/* External Ethernet Controller (3 wait states, 64kB) */
481	.MAS0 = { .R = 0x10050000 },
482	.MAS1 = { .R = 0xc0000100 },
483	.MAS2 = { .R = 0x3fff800a },
484	.MAS3 = { .R = 0x3fff800f }
485	}
486	#endif /* MMU setup */
487	};
488
489	#ifdef MPC55XX_BOOTFLAGS
490	/* mpc55xx_bootflag_0 is defined in start.S using PUBLIC_VAR(). I go through this
491	* indirection to avoid a linker issue - if I try to reference
492	* mpc55xx_bootflag_0 as an "extern uint32_t" I get a linker error.
493	* Maybe if I declare it as an "extern const uint32_t"? Anyway, this works.
494	*/
495	extern void *mpc55xx_bootflag_0(void);
496	uint32_t p_mpc55xx_bootflag_0 = (uint32_t )mpc55xx_bootflag_0;
497	#endif
498
499	static void mpc55xx_ebi_init(void)
500	{
501	int i;
502
503	#if defined(BOARD_GWLCFM)
504	SIU.GPDO[122].B.PDO=1; /* make sure USB reset is kept high */
505	SIU.GPDO[121].B.PDO=1; /* make sure Ethernet reset is kept high */
506	SIU.GPDO[113].B.PDO=1; /* make sure MOST Companion reset is kept high */
507	#endif /* defined(BOARD_GWLCFM) */
508	/*
509	* init I/O pins to proper state
510	*/
511	mpc55xx_siu_pcr_init(&SIU,
512	siu_pcr_list);
513
514	/* Set up chip selects. */
515	for (i = 0; i < sizeof(cs_setup) / sizeof(cs_setup[0]); i++) {
516	if (cs_setup[i].BR.B.V) {
517	EBI.CS [i] = cs_setup[i];
518	}
519	}
520
521	#ifdef MPC55XX_BOOTFLAGS
522	/* If the low bit of bootflag 0 is clear don't change the MMU.
523	*/
524	if (((*p_mpc55xx_bootflag_0) & 1))
525	#endif
526	{
527	/* Set up MMU. */
528	for (i = 0; i < sizeof(mmu_setup) / sizeof(mmu_setup[0]); i++) {
529	PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS0, mmu_setup[i].MAS0.R);
530	PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS1, mmu_setup[i].MAS1.R);
531	PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS2, mmu_setup[i].MAS2.R);
532	PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS3, mmu_setup[i].MAS3.R);
533	__asm__ volatile ("tlbwe");
534	}
535	}
536
537	#if defined(BOARD_GWLCFM)
538	/*
539	* init EBI for Muxed AD bus
540	*/
541	EBI.MCR.B.DBM = 1;
542	EBI.MCR.B.ADMUX = 1; /* use multiplexed bus */
543	EBI.MCR.B.D16_32 = 1; /* use lower AD bus */
544
545	SIU.ECCR.B.EBDF = 3; /* use CLK/4 as bus clock */
546
547	#endif /* defined(BOARD_GWLCFM) */
548	}
549
550	/**
551	* @brief Start BSP.
552	*/
553	LINKER_SYMBOL(bsp_section_bss_start);
554	LINKER_SYMBOL(bsp_section_bss_end);
555	LINKER_SYMBOL(bsp_section_sbss_start);
556	LINKER_SYMBOL(bsp_section_sbss_end);
557	LINKER_SYMBOL(bsp_section_vector_start);
558
559	void bsp_start(void)
560	{
561	rtems_status_code sc = RTEMS_SUCCESSFUL;
562	ppc_cpu_id_t myCpu;
563	ppc_cpu_revision_t myCpuRevision;
564
565	uintptr_t interrupt_stack_start = (uintptr_t)bsp_ram_end - 2 * MPC55XX_INTERRUPT_STACK_SIZE;
566	uint32_t interrupt_stack_size = MPC55XX_INTERRUPT_STACK_SIZE;
567
568
569	/* Initialize External Bus Interface */
570	mpc55xx_ebi_init();
571
572	/*
573	* make sure BSS/SBSS is cleared
574	*/
575	memset(bsp_section_bss_start,0,
576	bsp_section_bss_end-bsp_section_bss_start);
577	memset(bsp_section_sbss_start,0,
578	bsp_section_sbss_end-bsp_section_sbss_start);
579
580	ppc_exc_vector_base = (uint32_t) bsp_section_vector_start;
581
582	RTEMS_DEBUG_PRINT( "BSP start ...\n");
583
584	RTEMS_DEBUG_PRINT( "System clock : %i\n", mpc55xx_get_system_clock());
585	RTEMS_DEBUG_PRINT( "Memory start : 0x%08x\n", bsp_ram_start);
586	RTEMS_DEBUG_PRINT( "Memory end : 0x%08x\n", bsp_ram_end);
587	RTEMS_DEBUG_PRINT( "Memory size : 0x%08x\n", bsp_ram_end - bsp_ram_start);
588	RTEMS_DEBUG_PRINT( "Interrupt stack start : 0x%08x\n", interrupt_stack_start);
589	RTEMS_DEBUG_PRINT( "Interrupt stack end : 0x%08x\n", interrupt_stack_start + interrupt_stack_size);
590	RTEMS_DEBUG_PRINT( "Interrupt stack size : 0x%08x\n", interrupt_stack_size);
591
592	/*
593	* Get CPU identification dynamically. Note that the get_ppc_cpu_type()
594	* function store the result in global variables so that it can be used
595	* latter...
596	*/
597	myCpu = get_ppc_cpu_type();
598	myCpuRevision = get_ppc_cpu_revision();
599
600	/*
601	* determine clock speed
602	*/
603	bsp_clock_speed = mpc55xx_get_system_clock();
604
605	/* Time reference value */
606	bsp_clicks_per_usec = bsp_clock_speed / 1000000;
607
608	/* Initialize exceptions */
609	RTEMS_DEBUG_PRINT( "Initialize exceptions ...\n");
610	sc = ppc_exc_initialize(
611	PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
612	interrupt_stack_start,
613	interrupt_stack_size
614	);
615	if (sc != RTEMS_SUCCESSFUL) {
616	BSP_panic( "Cannot initialize exceptions");
617	} else {
618	DEBUG_DONE();
619	}
620
621	/* Initialize interrupts */
622	RTEMS_DEBUG_PRINT( "Initialize interrupts ...\n");
623	sc = bsp_interrupt_initialize();
624	if (sc != RTEMS_SUCCESSFUL) {
625	BSP_panic( "Cannot initialize interrupts");
626	} else {
627	DEBUG_DONE();
628	}
629
630	/* Initialize eMIOS */
631	mpc55xx_emios_initialize( MPC55XX_EMIOS_PRESCALER);
632	}

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