[574fb67] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup mpc55xx |
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| 5 | * |
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| 6 | * @brief BSP startup code. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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[9e7758b] | 10 | * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. |
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[574fb67] | 11 | * |
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[9e7758b] | 12 | * embedded brains GmbH |
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| 13 | * Obere Lagerstr. 30 |
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| 14 | * 82178 Puchheim |
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| 15 | * Germany |
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| 16 | * <rtems@embedded-brains.de> |
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| 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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| 20 | * http://www.rtems.com/license/LICENSE. |
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[574fb67] | 21 | */ |
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| 22 | |
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| 23 | #include <mpc55xx/mpc55xx.h> |
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| 24 | #include <mpc55xx/regs.h> |
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| 25 | #include <mpc55xx/edma.h> |
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[2f5435a4] | 26 | #include <mpc55xx/emios.h> |
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[9e7758b] | 27 | |
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| 28 | #include <string.h> |
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[574fb67] | 29 | |
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| 30 | #include <rtems.h> |
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[9e7758b] | 31 | #include <rtems/config.h> |
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[574fb67] | 32 | |
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| 33 | #include <libcpu/powerpc-utility.h> |
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[2d2de4eb] | 34 | #include <bsp/vectors.h> |
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[574fb67] | 35 | |
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| 36 | #include <bsp.h> |
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[d4886a06] | 37 | #include <bsp/bootcard.h> |
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[574fb67] | 38 | #include <bsp/irq.h> |
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| 39 | #include <bsp/irq-generic.h> |
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[9e7758b] | 40 | #include <bsp/linker-symbols.h> |
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| 41 | #include <bsp/start.h> |
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| 42 | #include <bsp/mpc55xx-config.h> |
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[574fb67] | 43 | |
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[a762dc2] | 44 | extern Heap_Control *RTEMS_Malloc_Heap; |
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| 45 | |
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[574fb67] | 46 | /* Symbols defined in linker command file */ |
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[9e7758b] | 47 | LINKER_SYMBOL(mpc55xx_exc_vector_base); |
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[574fb67] | 48 | |
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| 49 | unsigned int bsp_clock_speed = 0; |
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| 50 | |
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| 51 | uint32_t bsp_clicks_per_usec = 0; |
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| 52 | |
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| 53 | void BSP_panic( char *s) |
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| 54 | { |
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| 55 | rtems_interrupt_level level; |
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| 56 | |
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| 57 | rtems_interrupt_disable( level); |
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| 58 | |
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| 59 | printk( "%s PANIC %s\n", _RTEMS_version, s); |
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| 60 | |
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| 61 | while (1) { |
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| 62 | /* Do nothing */ |
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| 63 | } |
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| 64 | } |
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| 65 | |
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| 66 | void _BSP_Fatal_error( unsigned n) |
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| 67 | { |
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| 68 | rtems_interrupt_level level; |
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| 69 | |
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| 70 | rtems_interrupt_disable( level); |
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| 71 | |
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| 72 | printk( "%s PANIC ERROR %u\n", _RTEMS_version, n); |
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| 73 | |
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| 74 | while (1) { |
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| 75 | /* Do nothing */ |
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| 76 | } |
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| 77 | } |
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| 78 | |
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[9e7758b] | 79 | static void null_pointer_protection(void) |
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[574fb67] | 80 | { |
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[b9b3f3b7] | 81 | #ifdef MPC55XX_NULL_POINTER_PROTECTION |
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[9e7758b] | 82 | struct MMU_tag mmu = { .MAS0 = { .B = { .TLBSEL = 1, .ESEL = 1 } } }; |
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| 83 | |
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| 84 | PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS0, mmu.MAS0.R); |
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| 85 | __asm__ volatile ("tlbre"); |
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| 86 | mmu.MAS1.R = PPC_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS1); |
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| 87 | mmu.MAS1.B.VALID = 0; |
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| 88 | PPC_SET_SPECIAL_PURPOSE_REGISTER(FSL_EIS_MAS1, mmu.MAS1.R); |
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| 89 | __asm__ volatile ("tlbwe"); |
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[dbb3211a] | 90 | #endif |
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[574fb67] | 91 | } |
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| 92 | |
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| 93 | void bsp_start(void) |
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| 94 | { |
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[2d2de4eb] | 95 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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[574fb67] | 96 | ppc_cpu_id_t myCpu; |
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| 97 | ppc_cpu_revision_t myCpuRevision; |
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| 98 | |
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[9e7758b] | 99 | null_pointer_protection(); |
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[08013e8] | 100 | |
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| 101 | /* |
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| 102 | * make sure BSS/SBSS is cleared |
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| 103 | */ |
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[9e7758b] | 104 | memset(&bsp_section_bss_begin [0], 0, (size_t) bsp_section_bss_size); |
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[ac7af4a] | 105 | |
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[574fb67] | 106 | /* |
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| 107 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() |
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| 108 | * function store the result in global variables so that it can be used |
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| 109 | * latter... |
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| 110 | */ |
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| 111 | myCpu = get_ppc_cpu_type(); |
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| 112 | myCpuRevision = get_ppc_cpu_revision(); |
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[ac7af4a] | 113 | |
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[08013e8] | 114 | /* |
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| 115 | * determine clock speed |
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| 116 | */ |
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[dafacfa7] | 117 | bsp_clock_speed = mpc55xx_get_system_clock() / MPC55XX_SYSTEM_CLOCK_DIVIDER; |
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[ac7af4a] | 118 | |
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[dbb3211a] | 119 | /* Time reference value */ |
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| 120 | bsp_clicks_per_usec = bsp_clock_speed / 1000000; |
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| 121 | |
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[574fb67] | 122 | /* Initialize exceptions */ |
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[9e7758b] | 123 | ppc_exc_vector_base = (uint32_t) mpc55xx_exc_vector_base; |
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[2d2de4eb] | 124 | sc = ppc_exc_initialize( |
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| 125 | PPC_INTERRUPT_DISABLE_MASK_DEFAULT, |
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[9e7758b] | 126 | (uintptr_t) bsp_section_work_begin, |
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| 127 | Configuration.interrupt_stack_size |
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[2d2de4eb] | 128 | ); |
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| 129 | if (sc != RTEMS_SUCCESSFUL) { |
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| 130 | BSP_panic( "Cannot initialize exceptions"); |
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| 131 | } |
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[601d500] | 132 | ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler); |
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[574fb67] | 133 | |
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| 134 | /* Initialize interrupts */ |
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[2d2de4eb] | 135 | sc = bsp_interrupt_initialize(); |
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| 136 | if (sc != RTEMS_SUCCESSFUL) { |
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[574fb67] | 137 | BSP_panic( "Cannot initialize interrupts"); |
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| 138 | } |
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[ac7af4a] | 139 | |
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[9e7758b] | 140 | mpc55xx_edma_init(); |
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[a762dc2] | 141 | #ifdef MPC55XX_EMIOS_PRESCALER |
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| 142 | mpc55xx_emios_initialize(MPC55XX_EMIOS_PRESCALER); |
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| 143 | #endif |
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| 144 | } |
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| 145 | |
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| 146 | void bsp_pretasking_hook(void) |
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| 147 | { |
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| 148 | #if MPC55XX_CHIP_TYPE / 10 == 564 |
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| 149 | _Heap_Extend( |
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| 150 | RTEMS_Malloc_Heap, |
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| 151 | bsp_section_rwextra_end, |
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| 152 | (uintptr_t) bsp_ram_end |
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| 153 | - (uintptr_t) bsp_section_rwextra_end, |
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| 154 | NULL |
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| 155 | ); |
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| 156 | #endif |
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[574fb67] | 157 | } |
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