[574fb67] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup mpc55xx |
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| 5 | * |
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| 6 | * @brief BSP startup code. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Copyright (c) 2008 |
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| 11 | * Embedded Brains GmbH |
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| 12 | * Obere Lagerstr. 30 |
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| 13 | * D-82178 Puchheim |
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| 14 | * Germany |
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| 15 | * rtems@embedded-brains.de |
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| 16 | * |
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| 17 | * The license and distribution terms for this file may be found in the file |
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| 18 | * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. |
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| 19 | */ |
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| 20 | |
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| 21 | #include <mpc55xx/mpc55xx.h> |
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| 22 | #include <mpc55xx/regs.h> |
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| 23 | #include <mpc55xx/edma.h> |
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| 24 | |
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| 25 | #include <rtems.h> |
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| 26 | |
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| 27 | #include <libcpu/powerpc-utility.h> |
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| 28 | |
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| 29 | #include <bsp.h> |
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[d4886a06] | 30 | #include <bsp/bootcard.h> |
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[574fb67] | 31 | #include <bsp/irq.h> |
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| 32 | #include <bsp/irq-generic.h> |
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| 33 | #include <bsp/ppc_exc_bspsupp.h> |
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| 34 | |
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| 35 | #define RTEMS_STATUS_CHECKS_USE_PRINTK |
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| 36 | |
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| 37 | #include <rtems/status-checks.h> |
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| 38 | |
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[7495494] | 39 | #define DEBUG_DONE() RTEMS_DEBUG_PRINT( "Done\n") |
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[574fb67] | 40 | |
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| 41 | #define MPC55XX_INTERRUPT_STACK_SIZE 0x1000 |
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| 42 | |
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| 43 | /* Symbols defined in linker command file */ |
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[e76068d] | 44 | LINKER_SYMBOL(bsp_ram_start); |
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| 45 | LINKER_SYMBOL(bsp_ram_end); |
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| 46 | LINKER_SYMBOL(bsp_external_ram_start); |
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| 47 | LINKER_SYMBOL(bsp_external_ram_size); |
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| 48 | LINKER_SYMBOL(bsp_section_bss_end); |
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[574fb67] | 49 | |
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| 50 | unsigned int bsp_clock_speed = 0; |
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| 51 | |
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| 52 | uint32_t bsp_clicks_per_usec = 0; |
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| 53 | |
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| 54 | void BSP_panic( char *s) |
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| 55 | { |
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| 56 | rtems_interrupt_level level; |
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| 57 | |
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| 58 | rtems_interrupt_disable( level); |
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| 59 | |
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| 60 | printk( "%s PANIC %s\n", _RTEMS_version, s); |
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| 61 | |
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| 62 | while (1) { |
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| 63 | /* Do nothing */ |
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| 64 | } |
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| 65 | } |
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| 66 | |
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| 67 | void _BSP_Fatal_error( unsigned n) |
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| 68 | { |
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| 69 | rtems_interrupt_level level; |
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| 70 | |
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| 71 | rtems_interrupt_disable( level); |
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| 72 | |
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| 73 | printk( "%s PANIC ERROR %u\n", _RTEMS_version, n); |
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| 74 | |
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| 75 | while (1) { |
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| 76 | /* Do nothing */ |
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| 77 | } |
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| 78 | } |
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| 79 | |
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| 80 | void bsp_predriver_hook() |
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| 81 | { |
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| 82 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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| 83 | |
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[7495494] | 84 | RTEMS_DEBUG_PRINT( "Initialize eDMA ...\n"); |
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[574fb67] | 85 | sc = mpc55xx_edma_init(); |
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| 86 | if (sc != RTEMS_SUCCESSFUL) { |
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| 87 | BSP_panic( "Cannot initialize eDMA"); |
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| 88 | } else { |
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| 89 | DEBUG_DONE(); |
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| 90 | } |
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| 91 | } |
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| 92 | |
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| 93 | static void mpc55xx_ebi_init() |
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| 94 | { |
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| 95 | struct EBI_CS_tag cs = { BR : MPC55XX_ZERO_FLAGS, OR : MPC55XX_ZERO_FLAGS }; |
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| 96 | union SIU_PCR_tag pcr = MPC55XX_ZERO_FLAGS; |
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| 97 | int i = 0; |
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| 98 | |
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| 99 | /* External SRAM (0 wait states, 512kB, 4 word burst) */ |
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| 100 | cs.BR.B.BA = 0; |
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| 101 | cs.BR.B.PS = 1; |
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| 102 | cs.BR.B.BL = 1; |
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| 103 | cs.BR.B.WEBS = 0; |
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| 104 | cs.BR.B.TBDIP = 0; |
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| 105 | cs.BR.B.BI = 1; /* TODO: Enable burst */ |
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| 106 | cs.BR.B.V = 1; |
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| 107 | |
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| 108 | cs.OR.B.AM = 0x1fff0; |
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| 109 | cs.OR.B.SCY = 0; |
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| 110 | cs.OR.B.BSCY = 0; |
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| 111 | |
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| 112 | EBI.CS [0] = cs; |
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| 113 | |
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| 114 | /* !CS [0] */ |
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| 115 | SIU.PCR [0].R = 0x443; |
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| 116 | |
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| 117 | /* ADDR [8 : 31] */ |
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| 118 | for (i = 4; i < 4 + 24; ++i) { |
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| 119 | SIU.PCR [i].R = 0x440; |
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| 120 | } |
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| 121 | |
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| 122 | /* DATA [0 : 15] */ |
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| 123 | for (i = 28; i < 28 + 16; ++i) { |
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| 124 | SIU.PCR [i].R = 0x440; |
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| 125 | } |
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| 126 | |
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| 127 | /* RD_!WR */ |
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| 128 | SIU.PCR [62].R = 0x443; |
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| 129 | |
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| 130 | /* !BDIP */ |
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| 131 | SIU.PCR [63].R = 0x443; |
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| 132 | |
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| 133 | /* !WE [0 : 3] */ |
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| 134 | for (i = 64; i < 64 + 4; ++i) { |
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| 135 | SIU.PCR [i].R = 0x443; |
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| 136 | } |
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| 137 | |
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| 138 | /* !OE */ |
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| 139 | SIU.PCR [68].R = 0x443; |
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| 140 | |
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| 141 | /* !TS */ |
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| 142 | SIU.PCR [69].R = 0x443; |
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| 143 | } |
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| 144 | |
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| 145 | /** |
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| 146 | * @brief Start BSP. |
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| 147 | */ |
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| 148 | void bsp_start(void) |
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| 149 | { |
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| 150 | ppc_cpu_id_t myCpu; |
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| 151 | ppc_cpu_revision_t myCpuRevision; |
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| 152 | |
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[d4886a06] | 153 | uint32_t interrupt_stack_start = bsp_ram_end - 2 * MPC55XX_INTERRUPT_STACK_SIZE; |
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[574fb67] | 154 | uint32_t interrupt_stack_size = MPC55XX_INTERRUPT_STACK_SIZE; |
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| 155 | |
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| 156 | /* ESCI pad configuration */ |
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| 157 | SIU.PCR [89].R = 0x400; |
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| 158 | SIU.PCR [90].R = 0x400; |
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| 159 | |
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[7495494] | 160 | RTEMS_DEBUG_PRINT( "BSP start ...\n"); |
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[574fb67] | 161 | |
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[7495494] | 162 | RTEMS_DEBUG_PRINT( "System clock : %i\n", mpc55xx_get_system_clock()); |
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| 163 | RTEMS_DEBUG_PRINT( "Memory start : 0x%08x\n", bsp_ram_start); |
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| 164 | RTEMS_DEBUG_PRINT( "Memory end : 0x%08x\n", bsp_ram_end); |
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| 165 | RTEMS_DEBUG_PRINT( "Memory size : 0x%08x\n", bsp_ram_end - bsp_ram_start); |
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| 166 | RTEMS_DEBUG_PRINT( "Interrupt stack start : 0x%08x\n", interrupt_stack_start); |
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| 167 | RTEMS_DEBUG_PRINT( "Interrupt stack end : 0x%08x\n", interrupt_stack_start + interrupt_stack_size); |
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| 168 | RTEMS_DEBUG_PRINT( "Interrupt stack size : 0x%08x\n", interrupt_stack_size); |
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[574fb67] | 169 | |
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| 170 | /* |
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| 171 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() |
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| 172 | * function store the result in global variables so that it can be used |
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| 173 | * latter... |
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| 174 | */ |
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| 175 | myCpu = get_ppc_cpu_type(); |
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| 176 | myCpuRevision = get_ppc_cpu_revision(); |
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| 177 | |
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| 178 | /* Time reference value */ |
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| 179 | bsp_clicks_per_usec = bsp_clock_speed / 1000000; |
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| 180 | |
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| 181 | /* Initialize External Bus Interface */ |
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| 182 | mpc55xx_ebi_init(); |
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| 183 | |
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| 184 | /* Initialize exceptions */ |
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[7495494] | 185 | RTEMS_DEBUG_PRINT( "Initialize exceptions ...\n"); |
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[e76068d] | 186 | ppc_exc_initialize( |
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| 187 | PPC_INTERRUPT_DISABLE_MASK_DEFAULT, |
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| 188 | interrupt_stack_start, |
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| 189 | interrupt_stack_size |
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| 190 | ); |
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[574fb67] | 191 | DEBUG_DONE(); |
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| 192 | |
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| 193 | /* Initialize interrupts */ |
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[7495494] | 194 | RTEMS_DEBUG_PRINT( "Initialize interrupts ...\n"); |
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[574fb67] | 195 | if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) { |
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| 196 | BSP_panic( "Cannot initialize interrupts"); |
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| 197 | } else { |
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| 198 | DEBUG_DONE(); |
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| 199 | } |
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| 200 | |
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[7495494] | 201 | RTEMS_DEBUG_PRINT( "BSP start done\n"); |
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[574fb67] | 202 | |
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| 203 | return; |
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| 204 | |
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| 205 | /* TODO */ |
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| 206 | /* |
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| 207 | * Enable instruction and data caches. Do not force writethrough mode. |
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| 208 | */ |
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| 209 | #if INSTRUCTION_CACHE_ENABLE |
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| 210 | rtems_cache_enable_instruction(); |
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| 211 | #endif |
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| 212 | #if DATA_CACHE_ENABLE |
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| 213 | rtems_cache_enable_data(); |
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| 214 | #endif |
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| 215 | } |
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| 216 | |
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| 217 | /** |
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| 218 | * @brief Idle thread body. |
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| 219 | */ |
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| 220 | Thread _Thread_Idle_body( uint32_t ignored) |
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| 221 | { |
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| 222 | |
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| 223 | while (1) { |
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| 224 | asm volatile( |
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| 225 | "mfmsr 3;" |
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| 226 | "oris 3,3,4;" |
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| 227 | "sync;" |
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| 228 | "mtmsr 3;" |
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| 229 | "isync;" |
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| 230 | "ori 3,3,0;" |
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| 231 | "ori 3,3,0" |
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| 232 | ); |
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| 233 | } |
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| 234 | return 0; |
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| 235 | } |
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