[574fb67] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup mpc55xx |
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| 5 | * |
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| 6 | * @brief BSP startup code. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Copyright (c) 2008 |
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| 11 | * Embedded Brains GmbH |
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| 12 | * Obere Lagerstr. 30 |
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| 13 | * D-82178 Puchheim |
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| 14 | * Germany |
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| 15 | * rtems@embedded-brains.de |
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| 16 | * |
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| 17 | * The license and distribution terms for this file may be found in the file |
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| 18 | * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE. |
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| 19 | */ |
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| 20 | |
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| 21 | #include <mpc55xx/mpc55xx.h> |
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| 22 | #include <mpc55xx/regs.h> |
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| 23 | #include <mpc55xx/edma.h> |
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[2f5435a4] | 24 | #include <mpc55xx/emios.h> |
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| 25 | #include <mpc55xx/siu.h> |
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[574fb67] | 26 | |
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| 27 | #include <rtems.h> |
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| 28 | |
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| 29 | #include <libcpu/powerpc-utility.h> |
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[2d2de4eb] | 30 | #include <bsp/vectors.h> |
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[574fb67] | 31 | |
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| 32 | #include <bsp.h> |
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[d4886a06] | 33 | #include <bsp/bootcard.h> |
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[574fb67] | 34 | #include <bsp/irq.h> |
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| 35 | #include <bsp/irq-generic.h> |
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| 36 | |
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| 37 | #define RTEMS_STATUS_CHECKS_USE_PRINTK |
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| 38 | |
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| 39 | #include <rtems/status-checks.h> |
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| 40 | |
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[7495494] | 41 | #define DEBUG_DONE() RTEMS_DEBUG_PRINT( "Done\n") |
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[574fb67] | 42 | |
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| 43 | #define MPC55XX_INTERRUPT_STACK_SIZE 0x1000 |
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| 44 | |
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| 45 | /* Symbols defined in linker command file */ |
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[e76068d] | 46 | LINKER_SYMBOL(bsp_ram_start); |
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| 47 | LINKER_SYMBOL(bsp_ram_end); |
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| 48 | LINKER_SYMBOL(bsp_external_ram_start); |
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| 49 | LINKER_SYMBOL(bsp_external_ram_size); |
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| 50 | LINKER_SYMBOL(bsp_section_bss_end); |
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[574fb67] | 51 | |
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| 52 | unsigned int bsp_clock_speed = 0; |
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| 53 | |
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| 54 | uint32_t bsp_clicks_per_usec = 0; |
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| 55 | |
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| 56 | void BSP_panic( char *s) |
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| 57 | { |
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| 58 | rtems_interrupt_level level; |
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| 59 | |
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| 60 | rtems_interrupt_disable( level); |
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| 61 | |
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| 62 | printk( "%s PANIC %s\n", _RTEMS_version, s); |
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| 63 | |
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| 64 | while (1) { |
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| 65 | /* Do nothing */ |
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| 66 | } |
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| 67 | } |
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| 68 | |
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| 69 | void _BSP_Fatal_error( unsigned n) |
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| 70 | { |
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| 71 | rtems_interrupt_level level; |
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| 72 | |
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| 73 | rtems_interrupt_disable( level); |
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| 74 | |
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| 75 | printk( "%s PANIC ERROR %u\n", _RTEMS_version, n); |
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| 76 | |
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| 77 | while (1) { |
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| 78 | /* Do nothing */ |
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| 79 | } |
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| 80 | } |
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| 81 | |
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| 82 | void bsp_predriver_hook() |
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| 83 | { |
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| 84 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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| 85 | |
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[7495494] | 86 | RTEMS_DEBUG_PRINT( "Initialize eDMA ...\n"); |
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[574fb67] | 87 | sc = mpc55xx_edma_init(); |
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| 88 | if (sc != RTEMS_SUCCESSFUL) { |
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| 89 | BSP_panic( "Cannot initialize eDMA"); |
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| 90 | } else { |
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| 91 | DEBUG_DONE(); |
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| 92 | } |
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| 93 | } |
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| 94 | |
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[88919d0] | 95 | #if ((MPC55XX_CHIP_TYPE>=5510) && (MPC55XX_CHIP_TYPE<=5517)) |
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[2f5435a4] | 96 | /* |
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| 97 | * define init values for FMPLL ESYNCRx |
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| 98 | * (used in start.S/fmpll.S) |
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| 99 | */ |
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| 100 | #define EPREDIV_VAL (MPC55XX_FMPLL_PREDIV-1) |
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| 101 | #define EMFD_VAL (MPC55XX_FMPLL_MFD-16) |
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| 102 | #define VCO_CLK_REF (MPC55XX_FMPLL_REF_CLOCK/(EPREDIV_VAL+1)) |
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| 103 | #define VCO_CLK_OUT (VCO_CLK_REF*(EMFD_VAL+16)) |
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| 104 | #define ERFD_VAL ((VCO_CLK_OUT/MPC55XX_FMPLL_CLK_OUT)-1) |
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| 105 | |
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| 106 | const struct fmpll_syncr_vals_t { |
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| 107 | union ESYNCR2_tag esyncr2_temp; |
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| 108 | union ESYNCR2_tag esyncr2_final; |
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| 109 | union ESYNCR1_tag esyncr1_final; |
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| 110 | } fmpll_syncr_vals = |
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| 111 | { |
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| 112 | { /* esyncr2_temp */ |
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| 113 | .B.LOCEN=0, |
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| 114 | .B.LOLRE=0, |
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| 115 | .B.LOCRE=0, |
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| 116 | .B.LOLIRQ=0, |
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| 117 | .B.LOCIRQ=0, |
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| 118 | .B.ERATE=0, |
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| 119 | .B.DEPTH=0, |
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| 120 | .B.ERFD=ERFD_VAL+2 /* reduce output clock during init */ |
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| 121 | }, |
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| 122 | { /* esyncr2_final */ |
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| 123 | .B.LOCEN=0, |
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| 124 | .B.LOLRE=0, |
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| 125 | .B.LOCRE=0, |
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| 126 | .B.LOLIRQ=0, |
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| 127 | .B.LOCIRQ=0, |
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| 128 | .B.ERATE=0, |
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| 129 | .B.DEPTH=0, |
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| 130 | .B.ERFD=ERFD_VAL /* nominal output clock after init */ |
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| 131 | }, |
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| 132 | { /* esyncr1_final */ |
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| 133 | .B.CLKCFG=7, |
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| 134 | .B.EPREDIV=EPREDIV_VAL, |
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| 135 | .B.EMFD=EMFD_VAL |
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| 136 | } |
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| 137 | }; |
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| 138 | |
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[88919d0] | 139 | #else /* ((MPC55XX_CHIP_TYPE>=5510) && (MPC55XX_CHIP_TYPE<=5517)) */ |
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[2f5435a4] | 140 | |
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| 141 | const struct fmpll_syncr_vals_t { |
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| 142 | union SYNCR_tag syncr_temp; |
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| 143 | union SYNCR_tag syncr_final; |
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| 144 | } fmpll_syncr_vals = |
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| 145 | { |
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| 146 | { /* syncr_temp */ |
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| 147 | .B.PREDIV=MPC55XX_FMPLL_PREDIV-1, |
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| 148 | .B.MFD=MPC55XX_FMPLL_MFD, |
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| 149 | .B.RFD=2, |
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| 150 | .B.LOCEN=1 |
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| 151 | }, |
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| 152 | { /* syncr_final */ |
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| 153 | .B.PREDIV=MPC55XX_FMPLL_PREDIV-1, |
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| 154 | .B.MFD=MPC55XX_FMPLL_MFD, |
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| 155 | .B.RFD=0, |
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| 156 | .B.LOCEN=1 |
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| 157 | } |
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| 158 | }; |
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| 159 | |
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[88919d0] | 160 | #endif /* ((MPC55XX_CHIP_TYPE>=5510) && (MPC55XX_CHIP_TYPE<=5517)) */ |
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[2f5435a4] | 161 | |
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[08013e8] | 162 | #if defined(BOARD_GWLCFM) |
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[2f5435a4] | 163 | static const mpc55xx_siu_pcr_entry_t siu_pcr_list[] = { |
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| 164 | { 0,16,{.B.PA = 1, .B.WPE = 0}}, /* PA[ 0..15] analog input */ |
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| 165 | { 16, 4,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[ 0.. 4] LED/CAN_STBN out */ |
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| 166 | { 20, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PB[ 5.. 6] CAN_ERR/USBFLGC in*/ |
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| 167 | { 22, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[ 7 ] FR_A_EN out */ |
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| 168 | { 23, 4,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PB[ 8..10] IRQ/FR_A_ERR/USB_RDYin */ |
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| 169 | { 27, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PB[11..11] FR_STBN out */ |
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| 170 | |
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| 171 | { 32, 2,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 0.. 1] FR_A_TX/TXEN out */ |
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| 172 | { 34, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 2.. 2] FR_A_RX in */ |
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| 173 | { 35, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 3.. 4] INIT_ERR/ISB_IRQ in */ |
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| 174 | { 37, 2,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 5.. 6] PWRO1/2_ON out */ |
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| 175 | { 39, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PC[ 7.. 7] FR_B_RX in */ |
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| 176 | { 40, 2,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PC[ 8.. 9] FR_B_TX/TXEN out */ |
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| 177 | { 42, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[10 ] FR_B_EN out */ |
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| 178 | { 43, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[11 ] FOR_STATUS in */ |
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| 179 | { 44, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[12 ] FR_B_ERRN in */ |
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| 180 | { 45, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[13 ] HS_CAN_STBN out */ |
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| 181 | { 46, 1,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PC[14 ] HS_CAN_ERR in */ |
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| 182 | { 47, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PC[15 ] HS_CAN_EN out */ |
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| 183 | |
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| 184 | { 48, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 0 ] HS_CAN_TX out */ |
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| 185 | { 49, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 1 ] HS_CAN_RX in */ |
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| 186 | { 50, 2,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 2.. 3] PWRO1/2_OC in */ |
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| 187 | { 52, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 4 ] LS_CAN_TX out */ |
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| 188 | { 53, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 5 ] LS_CAN_RX in */ |
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| 189 | { 54, 1,{.B.PA = 1,.B.OBE = 1,.B.WPE = 0}}, /* PD[ 6 ] HS_CAN_TX out */ |
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| 190 | { 55, 1,{.B.PA = 1,.B.IBE = 1,.B.WPE = 0}}, /* PD[ 7 ] HS_CAN_RX in */ |
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| 191 | { 56, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}}, |
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| 192 | /* PD[ 8 ] I2C_SCL in/out */ |
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| 193 | { 57, 1,{.B.PA = 2,.B.IBE = 1,.B.OBE = 1,.B.WPE = 0}}, |
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| 194 | /* PD[ 9 ] I2C_SDA in/out */ |
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[dbb3211a] | 195 | |
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| 196 | { 58, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PD[10] LS_CAN_EN out*/ |
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| 197 | { 59, 3,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, |
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| 198 | /* PD[11..13] PWO1_OC, MOCO_INT in */ |
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| 199 | |
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[2f5435a4] | 200 | { 62, 4,{.B.PA = 0,.B.IBE = 1,.B.WPE = 0}}, /* PD[14..15] USB_FLGA/B in */ |
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| 201 | |
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[dbb3211a] | 202 | { 64, 5,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PE[ 0.. 4] LED_EXT1-5. out*/ |
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[08013e8] | 203 | { 70, 1,{.B.PA = 1,.B.SRC = 3,.B.WPE = 0}}, /* PE[ 6.. 6] CLKOUT out*/ |
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| 204 | |
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| 205 | { 80, 1,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PF[ 0.. 0] RD_WR out*/ |
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| 206 | { 81, 1,{.B.PA = 0,.B.SRC = 0,.B.WPE = 0}}, /* PF[ 1.. 1] (nc) in */ |
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| 207 | { 82, 8,{.B.PA = 2,.B.SRC = 1,.B.WPE = 0}}, /* PF[ 2..11] ADDR[8..15] out*/ |
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| 208 | { 90, 2,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PF[ 2..11] CS[0..1] out*/ |
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| 209 | { 92, 1,{.B.PA = 3,.B.SRC = 3,.B.WPE = 0}}, /* PF[ 12] ALE out*/ |
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| 210 | { 93, 3,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PF[13..15] OE/WE out*/ |
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| 211 | |
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| 212 | { 96,16,{.B.PA = 1,.B.SRC = 1,.B.WPE = 0}}, /* PG[ 0..15] AD16..31 in/out*/ |
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[2f5435a4] | 213 | |
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[dbb3211a] | 214 | {113, 1,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 1.. 1] RES_MOSTComp out*/ |
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| 215 | {114, 1,{.B.PA = 3,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 2.. 2] CS3_MOSTComp out*/ |
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[2f5435a4] | 216 | {115, 1,{.B.PA = 3,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 3.. 3] CS2_ETH out*/ |
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| 217 | {116, 2,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 4.. 5] FR/HC_TERM out*/ |
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| 218 | {118, 1,{.B.PA = 2,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 6.. 6] LIN_Tx out*/ |
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| 219 | {119, 1,{.B.PA = 2,.B.IBE = 1,.B.WPE = 0}}, /* PH[ 7.. 7] LIN_Rx in */ |
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| 220 | {120, 4,{.B.PA = 0,.B.OBE = 1,.B.WPE = 0}}, /* PH[ 8..11] LIN_SLP,RST out*/ |
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| 221 | |
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| 222 | {0,0} |
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| 223 | }; |
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[dbb3211a] | 224 | #elif defined(BOARD_PHYCORE_MPC5554) |
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| 225 | |
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| 226 | static const mpc55xx_siu_pcr_entry_t siu_pcr_list[] = { |
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| 227 | { 0, 4,{.B.PA = 1, .B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS [0:3] */ |
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| 228 | { 4,24,{.B.PA = 1, .B.DSC = 1 }}, /* ADDR [8 : 31] */ |
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| 229 | { 28,32,{.B.PA = 1, .B.DSC = 1 }}, /* DATA [0 : 31] */ |
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| 230 | { 60, 4,{.B.PA = 1, .B.DSC = 1, }}, /* TSIZ[0:1], RD_!WR, BDIP */ |
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| 231 | { 64, 6,{.B.PA = 1, .B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* RD_!WR, BDIP, !WE, !OE, !TS */ |
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| 232 | { 89, 4,{.B.PA = 1 }}, /* ESCI_A and ESCI_B */ |
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| 233 | {229, 4,{ .B.OBE= 1,.B.DSC = 1 }}, /* CLKOUT */ |
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| 234 | |
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| 235 | {0,0} |
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| 236 | }; |
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[2f5435a4] | 237 | |
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| 238 | #else /* MPC55xxEVB */ |
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| 239 | |
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| 240 | static const mpc55xx_siu_pcr_entry_t siu_pcr_list[] = { |
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| 241 | { 0, 1,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS [0] */ |
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| 242 | { 3, 1,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* !CS [3] */ |
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| 243 | { 4,24,{.B.PA = 1,.B.DSC = 1 }}, /* ADDR [8 : 31] */ |
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| 244 | { 28,16,{.B.PA = 1,.B.DSC = 1 }}, /* DATA [0 : 15] */ |
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| 245 | { 62, 8,{.B.PA = 1,.B.DSC = 1,.B.WPE=1,.B.WPS=1}}, /* RD_!WR, BDIP, |
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| 246 | !WE, !OE, !TS */ |
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| 247 | { 89, 2,{.B.PA = 1 }}, /* ESCI_B */ |
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| 248 | |
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| 249 | {0,0} |
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| 250 | }; |
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[08013e8] | 251 | #endif /* BOARD_GWLCFM */ |
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[2f5435a4] | 252 | |
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[dbb3211a] | 253 | /* |
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| 254 | * Arrays for setting up the chip selects. |
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| 255 | * You can define up to four, and those with the valid bit |
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| 256 | * set will be loaded into the matching chip select. |
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| 257 | */ |
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| 258 | static const struct EBI_CS_tag cs_setup[] = { |
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| 259 | #if defined(BOARD_GWLCFM) |
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| 260 | /* CS0: External SRAM (16 bit, 1 wait states, 512kB, no burst) */ |
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| 261 | { |
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| 262 | { |
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| 263 | .B.BA = 0x20000000>>15, |
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| 264 | .B.PS = 1, |
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| 265 | .B.AD_MUX = 1, |
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| 266 | .B.WEBS = 1, |
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| 267 | .B.TBDIP = 0, |
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| 268 | .B.BI = 1, |
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| 269 | .B.V = 1 |
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| 270 | }, |
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| 271 | { |
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| 272 | .B.AM = 0x1fff0, |
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| 273 | .B.SCY = 1, |
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| 274 | .B.BSCY = 0 |
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| 275 | } |
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| 276 | }, |
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| 277 | /* CS1: External USB controller (16 bit, 3 wait states, 32kB, no burst) */ |
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| 278 | { |
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| 279 | { |
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| 280 | .B.BA = 0x22000000>>15, |
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| 281 | .B.PS = 1, |
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| 282 | .B.AD_MUX = 1, |
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| 283 | .B.WEBS = 0, |
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| 284 | .B.TBDIP = 0, |
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| 285 | .B.BI = 1, |
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| 286 | .B.V = 1 |
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| 287 | }, |
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| 288 | { |
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| 289 | .B.AM = 0x1ffff, |
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| 290 | .B.SCY = 3, |
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| 291 | .B.BSCY = 0 |
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| 292 | } |
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| 293 | }, |
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| 294 | /* CS2: Ethernet (16 bit, 2 wait states, 32kB, no burst) */ |
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| 295 | { |
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| 296 | { |
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| 297 | .B.BA = 0x22800000>>15, |
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| 298 | .B.PS = 1, |
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| 299 | .B.AD_MUX = 1, |
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| 300 | .B.WEBS = 1, |
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| 301 | .B.TBDIP = 0, |
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| 302 | .B.BI = 1, |
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| 303 | .B.V = 1 |
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| 304 | }, |
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| 305 | { |
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| 306 | .B.AM = 0x1ffff, |
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| 307 | .B.SCY = 1, |
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| 308 | .B.BSCY = 0 |
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| 309 | } |
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| 310 | }, |
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| 311 | { /* CS3: MOST Companion. */ |
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| 312 | { |
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| 313 | .B.BA = 0x23000000>>15, |
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| 314 | .B.PS = 1, |
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| 315 | .B.AD_MUX = 1, |
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| 316 | .B.WEBS = 0, |
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| 317 | .B.TBDIP = 0, |
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| 318 | .B.BI = 1, |
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| 319 | .B.V = 1 |
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| 320 | }, |
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| 321 | |
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| 322 | { |
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| 323 | .B.AM = 0x1fff0, |
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[683af8a] | 324 | .B.SCY = 1, |
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[dbb3211a] | 325 | .B.BSCY = 0 |
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| 326 | } |
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| 327 | } |
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| 328 | #elif defined(BOARD_PHYCORE_MPC5554) |
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| 329 | /* CS0: External flash. */ |
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| 330 | { |
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| 331 | { .R = 0x20000003 }, /* Base 0x2000000, Burst Inhibit, Valid */ |
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| 332 | { .R = 0xff000050 } |
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| 333 | }, |
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| 334 | /* CS1: External synchronous burst mode SRAM. */ |
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| 335 | { |
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| 336 | { .R = 0x21000051 }, /* Base 0x2100000, 4-word Burst Enabled, Valid */ |
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| 337 | { .R = 0xff000000 } /* No wait states. */ |
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| 338 | }, |
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| 339 | /* CS2: External LAN91C111 */ |
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| 340 | { |
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| 341 | { .R = 0x22000003 }, /* Base 0x22000000, Burst inhibit, valid */ |
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| 342 | { .R = 0xff000010 } |
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| 343 | }, |
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| 344 | |
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| 345 | /* CS3: External FPGA */ |
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| 346 | { |
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| 347 | { .R = 0x23000003 }, /* Base 0x23000000, Burst inhibit, valid. */ |
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| 348 | { .R = 0xff000020 } |
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| 349 | } |
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| 350 | #else /* default, MPC55xxEVB */ |
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| 351 | /* CS0: External SRAM (2 wait states, 512kB, 4 word burst) */ |
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| 352 | { |
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| 353 | { |
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| 354 | .B.BA = 0, |
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| 355 | .B.PS = 1, |
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| 356 | .B.BL = 1, |
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| 357 | .B.WEBS = 0, |
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| 358 | .B.TBDIP = 0, |
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| 359 | .B.BI = 1, /* TODO: Enable burst */ |
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| 360 | .B.V = 1 |
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| 361 | }, |
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| 362 | |
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| 363 | { |
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| 364 | .B.AM = 0x1fff0, |
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| 365 | .B.SCY = 0, |
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| 366 | .B.BSCY = 0 |
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| 367 | } |
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| 368 | }, |
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| 369 | { { .R = 0 }, { .R = 0 } }, /* CS1: Unused. */ |
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| 370 | { { .R = 0 }, { .R = 0 } }, /* CS2: Unused. */ |
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| 371 | { /* CS3: ethernet? */ |
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| 372 | { |
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| 373 | .B.BA = 0x7fff, |
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| 374 | .B.PS = 1, |
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| 375 | .B.BL = 0, |
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| 376 | .B.WEBS = 0, |
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| 377 | .B.TBDIP = 0, |
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| 378 | .B.BI = 1, |
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| 379 | .B.V = 1 |
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| 380 | }, |
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| 381 | |
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| 382 | { |
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| 383 | .B.AM = 0x1ffff, |
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| 384 | .B.SCY = 1, |
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| 385 | .B.BSCY = 0 |
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| 386 | } |
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| 387 | } |
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| 388 | #endif /* Chip select setup */ |
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| 389 | }; |
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| 390 | |
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| 391 | /* |
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| 392 | * Arrays for setting up the MAS registers. |
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| 393 | * You can set as many as you want,we determine the size using sizeof. |
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| 394 | */ |
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| 395 | static const struct MMU_tag mmu_setup[] = { |
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| 396 | #if defined(BOARD_GWLCFM) |
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| 397 | { |
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| 398 | /* External Ethernet Controller (3 wait states, 64kB) */ |
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| 399 | |
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| 400 | { |
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| 401 | .B.TLBSEL = 1, /* MAS0 */ |
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| 402 | .B.ESEL = 5 |
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| 403 | }, |
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| 404 | { |
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| 405 | .B.VALID = 1, /* MAS1 */ |
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| 406 | .B.IPROT = 1, |
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| 407 | .B.TSIZ = 1 |
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| 408 | }, |
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| 409 | { |
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| 410 | .B.EPN = 0x3fff8, /* MAS2 */ |
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| 411 | .B.I = 1, |
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| 412 | .B.G = 1 |
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| 413 | }, |
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| 414 | { |
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| 415 | .B.RPN = 0x3fff8, /* MAS3 */ |
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| 416 | .B.UW = 1, |
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| 417 | .B.SW = 1, |
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| 418 | .B.UR = 1, |
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| 419 | .B.SR = 1 |
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| 420 | } |
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| 421 | } |
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| 422 | |
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| 423 | #elif defined(BOARD_PHYCORE_MPC5554) |
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| 424 | |
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| 425 | /* XXX I'm not using TLB1 entry 2 the same way as |
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| 426 | * in the BAM. |
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| 427 | */ |
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| 428 | /* Set up MMU TLB1 entry 2 for external ram. */ |
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| 429 | /* Effective Base address = 0x2100_0000 XXX NOT LIKE BAM */ |
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| 430 | /* Real Base address = 0x2100_0000 XXX NOT LIKE BAM */ |
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| 431 | /* Page Size 6 = 4MB XXX Not like BAM */ |
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| 432 | /* Not Guarded, Cache Enable, All Access (0, 3F) */ |
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| 433 | { |
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| 434 | { .R = 0x10020000}, /* MAS0 */ |
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| 435 | { .R = 0xC0000600}, /* MAS1 */ |
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| 436 | { .R = 0x21000000}, /* MAS2 */ |
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| 437 | { .R = 0x2100003F} /* MAS3 */ |
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| 438 | }, |
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| 439 | |
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| 440 | /* Set up MMU TLB1 entry 5 for second half of SRAM (debug RAM) */ |
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| 441 | /* Effective Base address = 0x2140_0000 */ |
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| 442 | /* Real Base address = 0x2140_0000 */ |
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| 443 | /* Page Size 6 = 4MB */ |
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| 444 | /* Not Guarded, Cache Enable, All Access (0, 3F) */ |
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| 445 | { |
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| 446 | { .R = 0x10050000 }, /* MAS0 */ |
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| 447 | { .R = 0xC0000600 }, /* MAS1 */ |
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| 448 | { .R = 0x21400000 }, /* MAS2 */ |
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| 449 | { .R = 0x2140003F } /* MAS3 */ |
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| 450 | }, |
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| 451 | /* Set up MMU TLB1 entry 6 for External LAN91C111 */ |
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| 452 | /* Effective Base address = 0x2200_0000 */ |
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| 453 | /* Real Base address = 0x2200_0000 */ |
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| 454 | /* Page Size 7 = 16MB */ |
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| 455 | /* Write-through, Guarded, Cache Inhibit, All Access (E, 3F) */ |
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| 456 | { |
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| 457 | { .R = 0x10060000}, /* MAS0 */ |
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| 458 | { .R = 0xC0000700}, /* MAS1 */ |
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| 459 | { .R = 0x2200000E}, /* MAS2 */ |
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| 460 | { .R = 0x2200003F} /* MAS3 */ |
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| 461 | }, |
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| 462 | |
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| 463 | /* Set up MMU TLB1 entry 7 for External FPGA */ |
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| 464 | /* Effective Base address = 0x2300_0000 */ |
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| 465 | /* Real Base address = 0x2300_0000 */ |
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| 466 | /* Page Size 7 = 16MB */ |
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| 467 | /* Write-through, Guarded, Cache Inhibit, All Access (E, 3F) */ |
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| 468 | { |
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| 469 | { .R = 0x10070000}, /* MAS0 */ |
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| 470 | { .R = 0xC0000700}, /* MAS1 */ |
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| 471 | { .R = 0x2300000E}, /* MAS2 */ |
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| 472 | { .R = 0x2300003F}, /* MAS3 */ |
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| 473 | }, |
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| 474 | |
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| 475 | /* Should also set up maps for the debug RAM and the |
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| 476 | * external flash. |
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| 477 | */ |
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| 478 | #else /* default, MPC55xxEVB */ |
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| 479 | { |
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| 480 | /* External Ethernet Controller (3 wait states, 64kB) */ |
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[a4475277] | 481 | .MAS0 = { .R = 0x10050000 }, |
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| 482 | .MAS1 = { .R = 0xc0000100 }, |
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| 483 | .MAS2 = { .R = 0x3fff800a }, |
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| 484 | .MAS3 = { .R = 0x3fff800f } |
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[dbb3211a] | 485 | } |
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| 486 | #endif /* MMU setup */ |
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| 487 | }; |
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| 488 | |
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| 489 | #ifdef MPC55XX_BOOTFLAGS |
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| 490 | /* mpc55xx_bootflag_0 is defined in start.S using PUBLIC_VAR(). I go through this |
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| 491 | * indirection to avoid a linker issue - if I try to reference |
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| 492 | * mpc55xx_bootflag_0 as an "extern uint32_t" I get a linker error. |
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| 493 | * Maybe if I declare it as an "extern const uint32_t"? Anyway, this works. |
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| 494 | */ |
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| 495 | extern void *mpc55xx_bootflag_0(void); |
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| 496 | uint32_t *p_mpc55xx_bootflag_0 = (uint32_t *)mpc55xx_bootflag_0; |
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| 497 | #endif |
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| 498 | |
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[2f5435a4] | 499 | static void mpc55xx_ebi_init(void) |
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[574fb67] | 500 | { |
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[dbb3211a] | 501 | int i; |
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[2f5435a4] | 502 | |
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[dbb3211a] | 503 | #if defined(BOARD_GWLCFM) |
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| 504 | SIU.GPDO[122].B.PDO=1; /* make sure USB reset is kept high */ |
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| 505 | SIU.GPDO[121].B.PDO=1; /* make sure Ethernet reset is kept high */ |
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| 506 | SIU.GPDO[113].B.PDO=1; /* make sure MOST Companion reset is kept high */ |
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| 507 | #endif /* defined(BOARD_GWLCFM) */ |
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[2f5435a4] | 508 | /* |
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| 509 | * init I/O pins to proper state |
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| 510 | */ |
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| 511 | mpc55xx_siu_pcr_init(&SIU, |
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| 512 | siu_pcr_list); |
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[08013e8] | 513 | |
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[dbb3211a] | 514 | /* Set up chip selects. */ |
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| 515 | for (i = 0; i < sizeof(cs_setup) / sizeof(cs_setup[0]); i++) { |
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| 516 | if (cs_setup[i].BR.B.V) { |
---|
| 517 | EBI.CS [i] = cs_setup[i]; |
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| 518 | } |
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| 519 | } |
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| 520 | |
---|
| 521 | #ifdef MPC55XX_BOOTFLAGS |
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| 522 | /* If the low bit of bootflag 0 is clear don't change the MMU. |
---|
| 523 | */ |
---|
| 524 | if (((*p_mpc55xx_bootflag_0) & 1)) |
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| 525 | #endif |
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| 526 | { |
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| 527 | /* Set up MMU. */ |
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| 528 | for (i = 0; i < sizeof(mmu_setup) / sizeof(mmu_setup[0]); i++) { |
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[4c00f02] | 529 | PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS0, mmu_setup[i].MAS0.R); |
---|
| 530 | PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS1, mmu_setup[i].MAS1.R); |
---|
| 531 | PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS2, mmu_setup[i].MAS2.R); |
---|
| 532 | PPC_SET_SPECIAL_PURPOSE_REGISTER( FSL_EIS_MAS3, mmu_setup[i].MAS3.R); |
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[d14d339] | 533 | __asm__ volatile ("tlbwe"); |
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[dbb3211a] | 534 | } |
---|
| 535 | } |
---|
| 536 | |
---|
[08013e8] | 537 | #if defined(BOARD_GWLCFM) |
---|
| 538 | /* |
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| 539 | * init EBI for Muxed AD bus |
---|
| 540 | */ |
---|
| 541 | EBI.MCR.B.DBM = 1; |
---|
| 542 | EBI.MCR.B.ADMUX = 1; /* use multiplexed bus */ |
---|
| 543 | EBI.MCR.B.D16_32 = 1; /* use lower AD bus */ |
---|
| 544 | |
---|
| 545 | SIU.ECCR.B.EBDF = 3; /* use CLK/4 as bus clock */ |
---|
| 546 | |
---|
| 547 | #endif /* defined(BOARD_GWLCFM) */ |
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[574fb67] | 548 | } |
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| 549 | |
---|
| 550 | /** |
---|
| 551 | * @brief Start BSP. |
---|
| 552 | */ |
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[08013e8] | 553 | LINKER_SYMBOL(bsp_section_bss_start); |
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| 554 | LINKER_SYMBOL(bsp_section_bss_end); |
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| 555 | LINKER_SYMBOL(bsp_section_sbss_start); |
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| 556 | LINKER_SYMBOL(bsp_section_sbss_end); |
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| 557 | LINKER_SYMBOL(bsp_section_vector_start); |
---|
| 558 | |
---|
[574fb67] | 559 | void bsp_start(void) |
---|
| 560 | { |
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[2d2de4eb] | 561 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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[574fb67] | 562 | ppc_cpu_id_t myCpu; |
---|
| 563 | ppc_cpu_revision_t myCpuRevision; |
---|
| 564 | |
---|
[2f5435a4] | 565 | uintptr_t interrupt_stack_start = (uintptr_t)bsp_ram_end - 2 * MPC55XX_INTERRUPT_STACK_SIZE; |
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[574fb67] | 566 | uint32_t interrupt_stack_size = MPC55XX_INTERRUPT_STACK_SIZE; |
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| 567 | |
---|
[08013e8] | 568 | |
---|
| 569 | /* Initialize External Bus Interface */ |
---|
| 570 | mpc55xx_ebi_init(); |
---|
| 571 | |
---|
| 572 | /* |
---|
| 573 | * make sure BSS/SBSS is cleared |
---|
| 574 | */ |
---|
| 575 | memset(bsp_section_bss_start,0, |
---|
| 576 | bsp_section_bss_end-bsp_section_bss_start); |
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| 577 | memset(bsp_section_sbss_start,0, |
---|
| 578 | bsp_section_sbss_end-bsp_section_sbss_start); |
---|
| 579 | |
---|
[612ff40e] | 580 | ppc_exc_vector_base = (uint32_t) bsp_section_vector_start; |
---|
[08013e8] | 581 | |
---|
[7495494] | 582 | RTEMS_DEBUG_PRINT( "BSP start ...\n"); |
---|
[574fb67] | 583 | |
---|
[7495494] | 584 | RTEMS_DEBUG_PRINT( "System clock : %i\n", mpc55xx_get_system_clock()); |
---|
| 585 | RTEMS_DEBUG_PRINT( "Memory start : 0x%08x\n", bsp_ram_start); |
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| 586 | RTEMS_DEBUG_PRINT( "Memory end : 0x%08x\n", bsp_ram_end); |
---|
| 587 | RTEMS_DEBUG_PRINT( "Memory size : 0x%08x\n", bsp_ram_end - bsp_ram_start); |
---|
| 588 | RTEMS_DEBUG_PRINT( "Interrupt stack start : 0x%08x\n", interrupt_stack_start); |
---|
| 589 | RTEMS_DEBUG_PRINT( "Interrupt stack end : 0x%08x\n", interrupt_stack_start + interrupt_stack_size); |
---|
| 590 | RTEMS_DEBUG_PRINT( "Interrupt stack size : 0x%08x\n", interrupt_stack_size); |
---|
[ac7af4a] | 591 | |
---|
[574fb67] | 592 | /* |
---|
| 593 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() |
---|
| 594 | * function store the result in global variables so that it can be used |
---|
| 595 | * latter... |
---|
| 596 | */ |
---|
| 597 | myCpu = get_ppc_cpu_type(); |
---|
| 598 | myCpuRevision = get_ppc_cpu_revision(); |
---|
[ac7af4a] | 599 | |
---|
[08013e8] | 600 | /* |
---|
| 601 | * determine clock speed |
---|
| 602 | */ |
---|
| 603 | bsp_clock_speed = mpc55xx_get_system_clock(); |
---|
[ac7af4a] | 604 | |
---|
[dbb3211a] | 605 | /* Time reference value */ |
---|
| 606 | bsp_clicks_per_usec = bsp_clock_speed / 1000000; |
---|
| 607 | |
---|
[574fb67] | 608 | /* Initialize exceptions */ |
---|
[7495494] | 609 | RTEMS_DEBUG_PRINT( "Initialize exceptions ...\n"); |
---|
[2d2de4eb] | 610 | sc = ppc_exc_initialize( |
---|
| 611 | PPC_INTERRUPT_DISABLE_MASK_DEFAULT, |
---|
| 612 | interrupt_stack_start, |
---|
| 613 | interrupt_stack_size |
---|
| 614 | ); |
---|
| 615 | if (sc != RTEMS_SUCCESSFUL) { |
---|
| 616 | BSP_panic( "Cannot initialize exceptions"); |
---|
| 617 | } else { |
---|
| 618 | DEBUG_DONE(); |
---|
| 619 | } |
---|
[601d500] | 620 | ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler); |
---|
[574fb67] | 621 | |
---|
| 622 | /* Initialize interrupts */ |
---|
[7495494] | 623 | RTEMS_DEBUG_PRINT( "Initialize interrupts ...\n"); |
---|
[2d2de4eb] | 624 | sc = bsp_interrupt_initialize(); |
---|
| 625 | if (sc != RTEMS_SUCCESSFUL) { |
---|
[574fb67] | 626 | BSP_panic( "Cannot initialize interrupts"); |
---|
| 627 | } else { |
---|
| 628 | DEBUG_DONE(); |
---|
| 629 | } |
---|
[ac7af4a] | 630 | |
---|
[d374492] | 631 | /* Initialize eMIOS */ |
---|
[dbb3211a] | 632 | mpc55xx_emios_initialize( MPC55XX_EMIOS_PRESCALER); |
---|
[574fb67] | 633 | } |
---|