source: rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/include/smsc9218i.h @ d374492

4.104.11
Last change on this file since d374492 was d374492, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on Jul 21, 2009 at 8:38:04 AM

Update for MPC55XX changes

  • Property mode set to 100644
File size: 21.3 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup mpc55xx
5 *
6 * @brief SMSC - LAN9218i
7 */
8
9/*
10 * Copyright (c) 2009
11 * embedded brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * rtems@embedded-brains.de
16 *
17 * The license and distribution terms for this file may be
18 * found in the file LICENSE in this distribution or at
19 * http://www.rtems.com/license/LICENSE.
20 */
21
22/**
23 * @name Memory Map
24 * @{                       
25 */
26
27typedef struct {
28  uint32_t rx_fifo_data;
29  uint32_t rx_fifo_data_aliases [7];
30  uint32_t tx_fifo_data;
31  uint32_t tx_fifo_data_aliases [7];
32  uint32_t rx_fifo_status;
33  uint32_t rx_fifo_status_peek;
34  uint32_t tx_fifo_status;
35  uint32_t tx_fifo_status_peek;
36  uint32_t id_rev;
37  uint32_t irq_cfg;
38  uint32_t int_sts;
39  uint32_t int_en;
40  uint32_t reserved_0;
41  uint32_t byte_test;
42  uint32_t fifo_int;
43  uint32_t rx_cfg;
44  uint32_t tx_cfg;
45  uint32_t hw_cfg;
46  uint32_t rx_dp_ctl;
47  uint32_t rx_fifo_inf;
48  uint32_t tx_fifo_inf;
49  uint32_t pmt_ctrl;
50  uint32_t gpio_cfg;
51  uint32_t gpt_cfg;
52  uint32_t gpt_cnt;
53  uint32_t reserved_1;
54  uint32_t word_swap;
55  uint32_t free_run;
56  uint32_t rx_drop;
57  uint32_t mac_csr_cmd;
58  uint32_t mac_csr_data;
59  uint32_t afc_cfg;
60  uint32_t e2p_cmd;
61  uint32_t e2p_data;
62} smsc9218i_registers;
63
64volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *) 0x3fff8000;
65
66/** @} */
67
68#define SMSC9218I_BIT_POS(pos) \
69  ((pos) > 15 ? \
70    ((pos) > 23 ? (pos) - 24 : (pos) - 8) \
71      : ((pos) > 7 ? (pos) + 8 : (pos) + 24))
72
73#define SMSC9218I_FLAG(pos) \
74  (1U << SMSC9218I_BIT_POS(pos))
75
76#define SMSC9218I_FIELD_8(val, pos) \
77  (((val) & 0xff) << SMSC9218I_BIT_POS(pos))
78
79#define SMSC9218I_GET_FIELD_8(reg, pos) \
80  (((reg) >> SMSC9218I_BIT_POS(pos)) & 0xff)
81
82#define SMSC9218I_FIELD_16(val, pos) \
83  (SMSC9218I_FIELD_8((val) >> 8, (pos) + 8) \
84    | SMSC9218I_FIELD_8((val), pos))
85
86#define SMSC9218I_GET_FIELD_16(reg, pos) \
87  ((SMSC9218I_GET_FIELD_8(reg, (pos) + 8) << 8) \
88    | SMSC9218I_GET_FIELD_8(reg, pos))
89
90#define SMSC9218I_SWAP(val) \
91  ((((val) >> 24) & 0xff) \
92    | ((((val) >> 16) & 0xff) << 8) \
93    | ((((val) >> 8) & 0xff) << 16) \
94    | (((val) & 0xff) << 24))
95
96/**
97 * @name Receive Status
98 * @{                       
99 */
100
101#define SMSC9218I_RX_STS_FILTER_FAIL SMSC9218I_FLAG(30)
102#define SMSC9218I_RX_STS_GET_LENGTH(reg) (SMSC9218I_GET_FIELD_16(reg, 16) & 0x3fff)
103#define SMSC9218I_RX_STS_ERROR SMSC9218I_FLAG(15)
104#define SMSC9218I_RX_STS_BROADCAST SMSC9218I_FLAG(13)
105#define SMSC9218I_RX_STS_ERROR_LENGTH SMSC9218I_FLAG(12)
106#define SMSC9218I_RX_STS_ERROR_RUNT_FRAME SMSC9218I_FLAG(11)
107#define SMSC9218I_RX_STS_MULTICAST SMSC9218I_FLAG(10)
108#define SMSC9218I_RX_STS_ERROR_TOO_LONG SMSC9218I_FLAG(7)
109#define SMSC9218I_RX_STS_ERROR_COLLISION SMSC9218I_FLAG(6)
110#define SMSC9218I_RX_STS_TYPE SMSC9218I_FLAG(5)
111#define SMSC9218I_RX_STS_WATCHDOG SMSC9218I_FLAG(4)
112#define SMSC9218I_RX_STS_ERROR_MII SMSC9218I_FLAG(3)
113#define SMSC9218I_RX_STS_DRIBBLING_BIT SMSC9218I_FLAG(2)
114#define SMSC9218I_RX_STS_ERROR_CRC SMSC9218I_FLAG(1)
115
116/** @} */
117
118/**
119 * @name Transmit Status
120 * @{                       
121 */
122
123#define SMSC9218I_TX_STS_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16)
124#define SMSC9218I_TX_STS_ERROR SMSC9218I_FLAG(15)
125#define SMSC9218I_TX_STS_ERROR_LOSS_OF_CARRIER SMSC9218I_FLAG(11)
126#define SMSC9218I_TX_STS_ERROR_NO_CARRIER SMSC9218I_FLAG(10)
127#define SMSC9218I_TX_STS_ERROR_LATE_COLLISION SMSC9218I_FLAG(9)
128#define SMSC9218I_TX_STS_ERROR_EXCESSIVE_COLLISIONS SMSC9218I_FLAG(8)
129#define SMSC9218I_TX_STS_ERROR_EXCESSIVE_DEFERRAL SMSC9218I_FLAG(2)
130#define SMSC9218I_TX_STS_ERROR_DEFERRED SMSC9218I_FLAG(0)
131
132/** @} */
133
134/**
135 * @name Transmit Command A
136 * @{                       
137 */
138
139#define SMSC9218I_TX_A_IOC SMSC9218I_FLAG(31)
140#define SMSC9218I_TX_A_END_ALIGN_4 0
141#define SMSC9218I_TX_A_END_ALIGN_16 SMSC9218I_FLAG(24)
142#define SMSC9218I_TX_A_END_ALIGN_32 SMSC9218I_FLAG(25)
143#define SMSC9218I_TX_A_DOFF(val) SMSC9218I_FIELD_8(val, 16)
144#define SMSC9218I_TX_A_FIRST SMSC9218I_FLAG(13)
145#define SMSC9218I_TX_A_LAST SMSC9218I_FLAG(12)
146#define SMSC9218I_TX_A_FRAGMENT_LENGTH(val) SMSC9218I_FIELD_16(val, 0)
147
148/** @} */
149
150/**
151 * @name Transmit Command B
152 * @{                       
153 */
154
155#define SMSC9218I_TX_B_TAG(val) SMSC9218I_FIELD_16(val, 16)
156#define SMSC9218I_TX_B_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16)
157#define SMSC9218I_TX_B_DISABLE_CRC SMSC9218I_FLAG(13)
158#define SMSC9218I_TX_B_DISABLE_PAD SMSC9218I_FLAG(12)
159#define SMSC9218I_TX_B_FRAME_LENGTH(val) SMSC9218I_FIELD_16(val, 0)
160
161/** @} */
162
163/**
164 * @name Chip ID and Revision
165 * @{                       
166 */
167
168#define SMSC9218I_ID_REV_GET_ID(reg) SMSC9218I_GET_FIELD_16(reg, 16)
169#define SMSC9218I_ID_REV_GET_REV(reg) SMSC9218I_GET_FIELD_16(reg, 0)
170#define SMSC9218I_ID_REV_ID_CHIP_118 0x0118U
171#define SMSC9218I_ID_REV_ID_CHIP_218 0x118aU
172
173/** @} */
174
175/**
176 * @name Interrupt Configuration
177 * @{                       
178 */
179
180#define SMSC9218I_IRQ_CFG_INT_DEAS(val) SMSC9218I_FIELD_8(val, 24)
181#define SMSC9218I_IRQ_CFG_GET_INT_DEAS(reg) SMSC9218I_GET_FIELD_8(reg, 24)
182#define SMSC9218I_IRQ_CFG_INT_DEAS_CLR SMSC9218I_FLAG(14)
183#define SMSC9218I_IRQ_CFG_INT_DEAS_STS SMSC9218I_FLAG(13)
184#define SMSC9218I_IRQ_CFG_IRQ_INT SMSC9218I_FLAG(12)
185#define SMSC9218I_IRQ_CFG_IRQ_EN SMSC9218I_FLAG(8)
186#define SMSC9218I_IRQ_CFG_IRQ_POL SMSC9218I_FLAG(4)
187#define SMSC9218I_IRQ_CFG_IRQ_TYPE SMSC9218I_FLAG(0)
188
189/** @} */
190
191/**
192 * @name Interrupt Status
193 * @{                       
194 */
195
196#define SMSC9218I_INT_STS_SW SMSC9218I_FLAG(31)
197#define SMSC9218I_INT_STS_TXSTOP SMSC9218I_FLAG(25)
198#define SMSC9218I_INT_STS_RXSTOP SMSC9218I_FLAG(24)
199#define SMSC9218I_INT_STS_RXDFH SMSC9218I_FLAG(23)
200#define SMSC9218I_INT_STS_TIOC SMSC9218I_FLAG(21)
201#define SMSC9218I_INT_STS_RXD SMSC9218I_FLAG(20)
202#define SMSC9218I_INT_STS_GPT SMSC9218I_FLAG(19)
203#define SMSC9218I_INT_STS_PHY SMSC9218I_FLAG(18)
204#define SMSC9218I_INT_STS_PME SMSC9218I_FLAG(17)
205#define SMSC9218I_INT_STS_TXSO SMSC9218I_FLAG(16)
206#define SMSC9218I_INT_STS_RWT SMSC9218I_FLAG(15)
207#define SMSC9218I_INT_STS_RXE SMSC9218I_FLAG(14)
208#define SMSC9218I_INT_STS_TXE SMSC9218I_FLAG(13)
209#define SMSC9218I_INT_STS_TDFO SMSC9218I_FLAG(10)
210#define SMSC9218I_INT_STS_TDFA SMSC9218I_FLAG(9)
211#define SMSC9218I_INT_STS_TSFF SMSC9218I_FLAG(8)
212#define SMSC9218I_INT_STS_TSFL SMSC9218I_FLAG(7)
213#define SMSC9218I_INT_STS_RSFF SMSC9218I_FLAG(4)
214#define SMSC9218I_INT_STS_RSFL SMSC9218I_FLAG(3)
215#define SMSC9218I_INT_STS_GPIO2 SMSC9218I_FLAG(2)
216#define SMSC9218I_INT_STS_GPIO1 SMSC9218I_FLAG(1)
217#define SMSC9218I_INT_STS_GPIO0 SMSC9218I_FLAG(0)
218
219/** @} */
220
221/**
222 * @name Interrupt Enable
223 * @{                       
224 */
225
226#define SMSC9218I_INT_EN_SW SMSC9218I_FLAG(31)
227#define SMSC9218I_INT_EN_TXSTOP SMSC9218I_FLAG(25)
228#define SMSC9218I_INT_EN_RXSTOP SMSC9218I_FLAG(24)
229#define SMSC9218I_INT_EN_RXDFH SMSC9218I_FLAG(23)
230#define SMSC9218I_INT_EN_TIOC SMSC9218I_FLAG(21)
231#define SMSC9218I_INT_EN_RXD SMSC9218I_FLAG(20)
232#define SMSC9218I_INT_EN_GPT SMSC9218I_FLAG(19)
233#define SMSC9218I_INT_EN_PHY SMSC9218I_FLAG(18)
234#define SMSC9218I_INT_EN_PME SMSC9218I_FLAG(17)
235#define SMSC9218I_INT_EN_TXSO SMSC9218I_FLAG(16)
236#define SMSC9218I_INT_EN_RWT SMSC9218I_FLAG(15)
237#define SMSC9218I_INT_EN_RXE SMSC9218I_FLAG(14)
238#define SMSC9218I_INT_EN_TXE SMSC9218I_FLAG(13)
239#define SMSC9218I_INT_EN_TDFO SMSC9218I_FLAG(10)
240#define SMSC9218I_INT_EN_TDFA SMSC9218I_FLAG(9)
241#define SMSC9218I_INT_EN_TSFF SMSC9218I_FLAG(8)
242#define SMSC9218I_INT_EN_TSFL SMSC9218I_FLAG(7)
243#define SMSC9218I_INT_EN_RSFF SMSC9218I_FLAG(4)
244#define SMSC9218I_INT_EN_RSFL SMSC9218I_FLAG(3)
245#define SMSC9218I_INT_EN_GPIO2 SMSC9218I_FLAG(2)
246#define SMSC9218I_INT_EN_GPIO1 SMSC9218I_FLAG(1)
247#define SMSC9218I_INT_EN_GPIO0 SMSC9218I_FLAG(0)
248
249/** @} */
250
251/**
252 * @name Byte Order Testing
253 * @{                       
254 */
255
256#define SMSC9218I_BYTE_TEST SMSC9218I_SWAP(0x87654321U)
257
258/** @} */
259
260/**
261 * @name FIFO Level Interrupts
262 * @{                       
263 */
264
265#define SMSC9218I_FIFO_INT_TDAL(val) SMSC9218I_FIELD_8(val, 24)
266#define SMSC9218I_FIFO_INT_GET_TDAL(reg) SMSC9218I_GET_FIELD_8(reg, 24)
267#define SMSC9218I_FIFO_INT_TSL(val) SMSC9218I_FIELD_8(val, 16)
268#define SMSC9218I_FIFO_INT_GET_TSL(reg) SMSC9218I_GET_FIELD_8(reg, 16)
269#define SMSC9218I_FIFO_INT_RSL(val) SMSC9218I_FIELD_8(val, 0)
270#define SMSC9218I_FIFO_INT_GET_RSL(reg) SMSC9218I_GET_FIELD_8(reg, 0)
271
272/** @} */
273
274/**
275 * @name Receive Configuration
276 * @{                       
277 */
278
279#define SMSC9218I_RX_CFG_END_ALIGN_4 0
280#define SMSC9218I_RX_CFG_END_ALIGN_16 SMSC9218I_FLAG(30)
281#define SMSC9218I_RX_CFG_END_ALIGN_32 SMSC9218I_FLAG(31)
282#define SMSC9218I_RX_CFG_DMA_CNT(val) SMSC9218I_FIELD_8(val, 24)
283#define SMSC9218I_RX_CFG_GET_DMA_CNT(reg) SMSC9218I_GET_FIELD_8(reg, 24)
284#define SMSC9218I_RX_CFG_DUMP SMSC9218I_FLAG(15)
285#define SMSC9218I_RX_CFG_DOFF(val) SMSC9218I_FIELD_8(val, 8)
286#define SMSC9218I_RX_CFG_GET_DOFF(reg) SMSC9218I_GET_FIELD_8(reg, 8)
287
288/** @} */
289
290/**
291 * @name Transmit Configuration
292 * @{                       
293 */
294
295#define SMSC9218I_TX_CFG_SDUMP SMSC9218I_FLAG(15)
296#define SMSC9218I_TX_CFG_DDUMP SMSC9218I_FLAG(14)
297#define SMSC9218I_TX_CFG_SAO SMSC9218I_FLAG(2)
298#define SMSC9218I_TX_CFG_ON SMSC9218I_FLAG(1)
299#define SMSC9218I_TX_CFG_STOP SMSC9218I_FLAG(0)
300
301/** @} */
302
303/**
304 * @name Hardware Configuration
305 * @{                       
306 */
307
308#define SMSC9218I_HW_CFG_AMDIX SMSC9218I_FLAG(24)
309#define SMSC9218I_HW_CFG_MBO SMSC9218I_FLAG(20)
310#define SMSC9218I_HW_CFG_TX_FIF_SZ(val) SMSC9218I_FIELD_8(val, 16)
311#define SMSC9218I_HW_CFG_GET_TX_FIF_SZ(reg) SMSC9218I_GET_FIELD_8(reg, 16)
312#define SMSC9218I_HW_CFG_BITMD_32 SMSC9218I_FLAG(2)
313#define SMSC9218I_HW_CFG_SRST_TO SMSC9218I_FLAG(1)
314#define SMSC9218I_HW_CFG_SRST SMSC9218I_FLAG(0)
315
316/** @} */
317
318/**
319 * @name Receive Datapath Control
320 * @{                       
321 */
322
323#define SMSC9218I_RX_DP_CTRL_FFWD SMSC9218I_FLAG(31)
324
325/** @} */
326
327/**
328 * @name Receive FIFO Information
329 * @{                       
330 */
331
332#define SMSC9218I_RX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16)
333#define SMSC9218I_RX_FIFO_INF_GET_DUSED(reg) SMSC9218I_GET_FIELD_16(reg, 0)
334
335/** @} */
336
337/**
338 * @name Transmit FIFO Information
339 * @{                       
340 */
341
342#define SMSC9218I_TX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16)
343#define SMSC9218I_TX_FIFO_INF_GET_FREE(reg) SMSC9218I_GET_FIELD_16(reg, 0)
344
345/** @} */
346
347/**
348 * @name Power Management Control
349 * @{                       
350 */
351
352#define SMSC9218I_PMT_CTRL_PM_MODE_D0 0
353#define SMSC9218I_PMT_CTRL_PM_MODE_D1 SMSC9218I_FLAG(12)
354#define SMSC9218I_PMT_CTRL_PM_MODE_D2 SMSC9218I_FLAG(13)
355#define SMSC9218I_PMT_CTRL_PHY_RST SMSC9218I_FLAG(10)
356#define SMSC9218I_PMT_CTRL_WOL_EN SMSC9218I_FLAG(9)
357#define SMSC9218I_PMT_CTRL_ED_EN SMSC9218I_FLAG(8)
358#define SMSC9218I_PMT_CTRL_PME_TYPE_PUPU SMSC9218I_FLAG(6)
359#define SMSC9218I_PMT_CTRL_WUPS_NO 0
360#define SMSC9218I_PMT_CTRL_WUPS_ENERGY SMSC9218I_FLAG(4)
361#define SMSC9218I_PMT_CTRL_WUPS_MAGIC SMSC9218I_FLAG(5)
362#define SMSC9218I_PMT_CTRL_PME_IND SMSC9218I_FLAG(3)
363#define SMSC9218I_PMT_CTRL_PME_POL SMSC9218I_FLAG(2)
364#define SMSC9218I_PMT_CTRL_PME_EN SMSC9218I_FLAG(1)
365#define SMSC9218I_PMT_CTRL_READY SMSC9218I_FLAG(0)
366
367/** @} */
368
369/**
370 * @name General Purpose IO Configuration
371 * @{                       
372 */
373
374#define SMSC9218I_GPIO_CFG_LED3 SMSC9218I_FLAG(30)
375#define SMSC9218I_GPIO_CFG_LED2 SMSC9218I_FLAG(29)
376#define SMSC9218I_GPIO_CFG_LED1 SMSC9218I_FLAG(28)
377#define SMSC9218I_GPIO_CFG_GPIO2_INT_POL SMSC9218I_FLAG(26)
378#define SMSC9218I_GPIO_CFG_GPIO1_INT_POL SMSC9218I_FLAG(25)
379#define SMSC9218I_GPIO_CFG_GPIO0_INT_POL SMSC9218I_FLAG(24)
380#define SMSC9218I_GPIO_CFG_GPIOBUF2 SMSC9218I_FLAG(18)
381#define SMSC9218I_GPIO_CFG_GPIOBUF1 SMSC9218I_FLAG(17)
382#define SMSC9218I_GPIO_CFG_GPIOBUF0 SMSC9218I_FLAG(16)
383#define SMSC9218I_GPIO_CFG_GPIODIR2 SMSC9218I_FLAG(10)
384#define SMSC9218I_GPIO_CFG_GPIODIR1 SMSC9218I_FLAG(9)
385#define SMSC9218I_GPIO_CFG_GPIODIR0 SMSC9218I_FLAG(8)
386#define SMSC9218I_GPIO_CFG_GPO4 SMSC9218I_FLAG(4)
387#define SMSC9218I_GPIO_CFG_GPO3 SMSC9218I_FLAG(3)
388#define SMSC9218I_GPIO_CFG_GPIO0 SMSC9218I_FLAG(0)
389#define SMSC9218I_GPIO_CFG_GPIO2 SMSC9218I_FLAG(2)
390#define SMSC9218I_GPIO_CFG_GPIO1 SMSC9218I_FLAG(1)
391
392/** @} */
393
394/**
395 * @name General Purpose Timer Configuration
396 * @{                       
397 */
398
399#define SMSC9218I_GPT_CFG_TIMER_EN SMSC9218I_FLAG(29)
400#define SMSC9218I_GPT_CFG_LOAD(val) SMSC9218I_FIELD_16(val, 0)
401#define SMSC9218I_GPT_CFG_GET_LOAD(reg) SMSC9218I_GET_FIELD_16(reg, 0)
402
403/** @} */
404
405/**
406 * @name General Purpose Timer Count
407 * @{                       
408 */
409
410#define SMSC9218I_GPT_CNT_GET_CNT SMSC9218I_GET_FIELD_16(reg, 0)
411
412/** @} */
413
414/**
415 * @name Word Swap
416 * @{                       
417 */
418
419#define SMSC9218I_ENDIAN_BIG 0xffffffffU
420
421/** @} */
422
423/**
424 * @name Free Run Counter
425 * @{                       
426 */
427
428#define SMSC9218I_FREE_RUN_GET(reg) SMSC9218I_SWAP(reg)
429
430/** @} */
431
432/**
433 * @name Receiver Dropped Frames Counter
434 * @{                       
435 */
436
437#define SMSC9218I_RX_DROP_GET(reg) SMSC9218I_SWAP(reg)
438
439/** @} */
440
441/**
442 * @name MAC Control and Status Synchronizer Command
443 * @{                       
444 */
445
446#define SMSC9218I_MAC_CSR_CMD_BUSY SMSC9218I_FLAG(31)
447#define SMSC9218I_MAC_CSR_CMD_READ SMSC9218I_FLAG(30)
448#define SMSC9218I_MAC_CSR_CMD_ADDR(val) SMSC9218I_FIELD_8(val, 0)
449#define SMSC9218I_MAC_CSR_CMD_GET_ADDR(reg) SMSC9218I_GET_FIELD_8(reg, 0)
450
451/** @} */
452
453/**
454 * @name MAC Control Register
455 * @{                       
456 */
457
458#define SMSC9218I_MAC_CR 0x00000001U
459#define SMSC9218I_MAC_CR_RXALL 0x80000000U
460#define SMSC9218I_MAC_CR_HBDIS 0x10000000U
461#define SMSC9218I_MAC_CR_RCVOWN 0x00800000U
462#define SMSC9218I_MAC_CR_LOOPBK 0x00200000U
463#define SMSC9218I_MAC_CR_FDPX 0x00100000U
464#define SMSC9218I_MAC_CR_MCPAS 0x00080000U
465#define SMSC9218I_MAC_CR_PRMS 0x00040000U
466#define SMSC9218I_MAC_CR_INVFILT 0x00020000U
467#define SMSC9218I_MAC_CR_PASSBAD 0x00010000U
468#define SMSC9218I_MAC_CR_HFILT 0x00008000U
469#define SMSC9218I_MAC_CR_HPFILT 0x00002000U
470#define SMSC9218I_MAC_CR_LCOLL 0x00001000U
471#define SMSC9218I_MAC_CR_BCAST 0x00000800U
472#define SMSC9218I_MAC_CR_DISRTY 0x00000400U
473#define SMSC9218I_MAC_CR_PADSTR 0x00000100U
474#define SMSC9218I_MAC_CR_BOLMT_MASK 0x000000c0U
475#define SMSC9218I_MAC_CR_BOLMT_10 0x00000000U
476#define SMSC9218I_MAC_CR_BOLMT_8 0x00000040U
477#define SMSC9218I_MAC_CR_BOLMT_4 0x00000080U
478#define SMSC9218I_MAC_CR_BOLMT_1 0x000000c0U
479#define SMSC9218I_MAC_CR_DFCHK 0x00000020U
480#define SMSC9218I_MAC_CR_TXEN 0x00000008U
481#define SMSC9218I_MAC_CR_RXEN 0x00000004U
482
483/** @} */
484
485/**
486 * @name MAC Address High
487 * @{                       
488 */
489
490#define SMSC9218I_MAC_ADDRH 0x00000002U
491#define SMSC9218I_MAC_ADDRH_MASK 0x0000ffffU
492
493/** @} */
494
495/**
496 * @name MAC Address Low
497 * @{                       
498 */
499
500#define SMSC9218I_MAC_ADDRL 0x00000003U
501#define SMSC9218I_MAC_ADDRL_MASK 0xffffffffU
502
503/** @} */
504
505/**
506 * @name Multicast Hash Table High
507 * @{                       
508 */
509
510#define SMSC9218I_MAC_HASHH 0x00000004U
511#define SMSC9218I_MAC_HASHH_MASK 0xffffffffU
512
513/** @} */
514
515/**
516 * @name Multicast Hash Table Low
517 * @{                       
518 */
519
520#define SMSC9218I_MAC_HASHL 0x00000005U
521#define SMSC9218I_MAC_HASHL_MASK 0xffffffffU
522
523/** @} */
524
525/**
526 * @name MII Access
527 * @{                       
528 */
529
530#define SMSC9218I_MAC_MII_ACC 0x00000006U
531#define SMSC9218I_MAC_MII_ACC_PHY_DEFAULT (1U << 11)
532#define SMSC9218I_MAC_MII_ACC_WRITE (1U << 1)
533#define SMSC9218I_MAC_MII_ACC_BUSY (1U << 0)
534#define SMSC9218I_MAC_MII_ACC_ADDR(addr) ((addr) << 6)
535
536/** @} */
537
538/**
539 * @name MII Data
540 * @{                       
541 */
542
543#define SMSC9218I_MAC_MII_DATA 0x00000007U
544
545/** @} */
546
547/**
548 * @name Flow Control
549 * @{                       
550 */
551
552#define SMSC9218I_MAC_FLOW 0x00000008U
553#define SMSC9218I_MAC_FLOW_FCPT_MASK 0xffff0000U
554#define SMSC9218I_MAC_FLOW_FCPASS 0x00000004U
555#define SMSC9218I_MAC_FLOW_FCEN 0x00000002U
556#define SMSC9218I_MAC_FLOW_FCBSY 0x00000001U
557
558/** @} */
559
560/**
561 * @name VLAN1 Tag
562 * @{                       
563 */
564
565#define SMSC9218I_MAC_VLAN1 0x00000009U
566
567/** @} */
568
569/**
570 * @name VLAN2 Tag
571 * @{                       
572 */
573
574#define SMSC9218I_MAC_VLAN2 0x0000000aU
575
576/** @} */
577
578/**
579 * @name Wake-up Frame Filter
580 * @{                       
581 */
582
583#define SMSC9218I_MAC_WUFF 0x0000000bU
584
585/** @} */
586
587/**
588 * @name Wake-up Control and Status
589 * @{                       
590 */
591
592#define SMSC9218I_MAC_WUCSR 0x0000000cU
593#define SMSC9218I_MAC_WUCSR_GUE 0x00000200U
594#define SMSC9218I_MAC_WUCSR_WUFR 0x00000040U
595#define SMSC9218I_MAC_WUCSR_MPR 0x00000020U
596#define SMSC9218I_MAC_WUCSR_WUEN 0x00000004U
597#define SMSC9218I_MAC_WUCSR_MPEN 0x00000002U
598
599/** @} */
600
601/**
602 * @name Basic Control
603 * @{                       
604 */
605
606#define SMSC9218I_PHY_BCR 0x00000000U
607#define SMSC9218I_PHY_BCR_RST 0x00008000U
608#define SMSC9218I_PHY_BCR_LOOPBK 0x00004000U
609#define SMSC9218I_PHY_BCR_SS 0x00002000U
610#define SMSC9218I_PHY_BCR_ANE 0x00001000U
611#define SMSC9218I_PHY_BCR_PWRDN 0x00000800U
612#define SMSC9218I_PHY_BCR_RSTAN 0x00000200U
613#define SMSC9218I_PHY_BCR_FDPLX 0x00000100U
614#define SMSC9218I_PHY_BCR_COLLTST 0x00000080U
615
616/** @} */
617
618/**
619 * @name Basic Status
620 * @{                       
621 */
622
623#define SMSC9218I_PHY_BSR 0x00000001U
624#define SMSC9218I_PHY_BSR_100_T4_ABLE 0x00008000U
625#define SMSC9218I_PHY_BSR_100_TX_FDPLX 0x00004000U
626#define SMSC9218I_PHY_BSR_100_TX_HDPLX 0x00002000U
627#define SMSC9218I_PHY_BSR_10_FDPLX 0x00001000U
628#define SMSC9218I_PHY_BSR_10_HDPLX 0x00000800U
629#define SMSC9218I_PHY_BSR_ANC 0x00000020U
630#define SMSC9218I_PHY_BSR_REM_FAULT 0x00000010U
631#define SMSC9218I_PHY_BSR_AN_ABLE 0x00000008U
632#define SMSC9218I_PHY_BSR_LINK_STATUS 0x00000004U
633#define SMSC9218I_PHY_BSR_JAB_DET 0x00000002U
634#define SMSC9218I_PHY_BSR_EXT_CAP 0x00000001U
635
636/** @} */
637
638/**
639 * @name PHY Identifier 1
640 * @{                       
641 */
642
643#define SMSC9218I_PHY_ID1 0x00000002U
644#define SMSC9218I_PHY_ID1_MASK 0x0000ffffU
645#define SMSC9218I_PHY_ID1_LAN9118 0x00000007U
646#define SMSC9218I_PHY_ID1_LAN9218 (PHY_ID1_LAN9118)
647
648/** @} */
649
650/**
651 * @name PHY Identifier 2
652 * @{                       
653 */
654
655#define SMSC9218I_PHY_ID2 0x00000003U
656#define SMSC9218I_PHY_ID2_MASK 0x0000ffffU
657#define SMSC9218I_PHY_ID2_MODEL_MASK 0x000003f0U
658#define SMSC9218I_PHY_ID2_REV_MASK 0x0000000fU
659#define SMSC9218I_PHY_ID2_LAN9118 0x0000c0d1U
660#define SMSC9218I_PHY_ID2_LAN9218 0x0000c0c3U
661
662/** @} */
663
664/**
665 * @name Auto-negotiation Advertisment
666 * @{                       
667 */
668
669#define SMSC9218I_PHY_ANAR 0x00000004U
670#define SMSC9218I_PHY_ANAR_NXTPG_CAP 0x00008000U
671#define SMSC9218I_PHY_ANAR_REM_FAULT 0x00002000U
672#define SMSC9218I_PHY_ANAR_PAUSE_OP_MASK 0x00000c00U
673#define SMSC9218I_PHY_ANAR_PAUSE_OP_NONE 0x00000000U
674#define SMSC9218I_PHY_ANAR_PAUSE_OP_ASLP 0x00000400U
675#define SMSC9218I_PHY_ANAR_PAUSE_OP_SLP 0x00000800U
676#define SMSC9218I_PHY_ANAR_PAUSE_OP_BOTH 0x00000c00U
677#define SMSC9218I_PHY_ANAR_100_T4_ABLE 0x00000200U
678#define SMSC9218I_PHY_ANAR_100_TX_FDPLX 0x00000100U
679#define SMSC9218I_PHY_ANAR_100_TX_ABLE 0x00000080U
680#define SMSC9218I_PHY_ANAR_10_FDPLX 0x00000040U
681#define SMSC9218I_PHY_ANAR_10_ABLE 0x00000020U
682
683/** @} */
684
685/**
686 * @name Auto-negotiation Link Partner Ability
687 * @{                       
688 */
689
690#define SMSC9218I_PHY_ANLPAR 0x00000005U
691#define SMSC9218I_PHY_ANLPAR_NXTPG_CAP 0x00008000U
692#define SMSC9218I_PHY_ANLPAR_ACK 0x00004000U
693#define SMSC9218I_PHY_ANLPAR_REM_FAULT 0x00002000U
694#define SMSC9218I_PHY_ANLPAR_PAUSE_CAP 0x00000400U
695#define SMSC9218I_PHY_ANLPAR_100_T4_ABLE 0x00000200U
696#define SMSC9218I_PHY_ANLPAR_100_TX_FDPLX 0x00000100U
697#define SMSC9218I_PHY_ANLPAR_100_TX_ABLE 0x00000080U
698#define SMSC9218I_PHY_ANLPAR_10_FDPLX 0x00000040U
699#define SMSC9218I_PHY_ANLPAR_10_ABLE 0x00000020U
700
701/** @} */
702
703/**
704 * @name Auto-negotiation Expansion
705 * @{                       
706 */
707
708#define SMSC9218I_PHY_ANEXPR 0x00000006U
709#define SMSC9218I_PHY_ANEXPR_PARDET_FAULT 0x00000010U
710#define SMSC9218I_PHY_ANEXPR_LP_NXTPG_CAP 0x00000008U
711#define SMSC9218I_PHY_ANEXPR_NXTPG_CAP 0x00000004U
712#define SMSC9218I_PHY_ANEXPR_NEWPG_REC 0x00000002U
713#define SMSC9218I_PHY_ANEXPR_LP_AN_ABLE 0x00000001U
714
715/** @} */
716
717/**
718 * @name Mode Control and Status
719 * @{                       
720 */
721
722#define SMSC9218I_PHY_MCSR 0x00000011U
723#define SMSC9218I_PHY_MCSR_EDPWRDOWN 0x00002000U
724#define SMSC9218I_PHY_MCSR_ENERGYON 0x00000002U
725
726/** @} */
727
728/**
729 * @name Special Modes
730 * @{                       
731 */
732
733#define SMSC9218I_PHY_SPMODES 0x00000012U
734
735/** @} */
736
737/**
738 * @name Special Control and Status Indications
739 * @{                       
740 */
741
742#define SMSC9218I_PHY_CSIR 0x0000001bU
743#define SMSC9218I_PHY_CSIR_SQEOFF 0x00000800U
744#define SMSC9218I_PHY_CSIR_FEFIEN 0x00000020U
745#define SMSC9218I_PHY_CSIR_XPOL 0x00000010U
746
747/** @} */
748
749/**
750 * @name Interrupt Source Flag
751 * @{                       
752 */
753
754#define SMSC9218I_PHY_ISR 0x0000001dU
755#define SMSC9218I_PHY_ISR_INT7 0x00000080U
756#define SMSC9218I_PHY_ISR_INT6 0x00000040U
757#define SMSC9218I_PHY_ISR_INT5 0x00000020U
758#define SMSC9218I_PHY_ISR_INT4 0x00000010U
759#define SMSC9218I_PHY_ISR_INT3 0x00000008U
760#define SMSC9218I_PHY_ISR_INT2 0x00000004U
761#define SMSC9218I_PHY_ISR_INT1 0x00000002U
762
763/** @} */
764
765/**
766 * @name Interrupt Mask
767 * @{                       
768 */
769
770#define SMSC9218I_PHY_IMR 0x0000001eU
771#define SMSC9218I_PHY_IMR_INT7 0x00000080U
772#define SMSC9218I_PHY_IMR_INT6 0x00000040U
773#define SMSC9218I_PHY_IMR_INT5 0x00000020U
774#define SMSC9218I_PHY_IMR_INT4 0x00000010U
775#define SMSC9218I_PHY_IMR_INT3 0x00000008U
776#define SMSC9218I_PHY_IMR_INT2 0x00000004U
777#define SMSC9218I_PHY_IMR_INT1 0x00000002U
778
779/** @} */
780
781/**
782 * @name PHY Special Control and Status
783 * @{                       
784 */
785
786#define SMSC9218I_PHY_PHYSCSR 0x0000001fU
787#define SMSC9218I_PHY_PHYSCSR_ANDONE 0x00001000U
788#define SMSC9218I_PHY_PHYSCSR_4B5B_EN 0x00000040U
789#define SMSC9218I_PHY_PHYSCSR_SPEED_MASK 0x0000001cU
790#define SMSC9218I_PHY_PHYSCSR_SPEED_10HD 0x00000004U
791#define SMSC9218I_PHY_PHYSCSR_SPEED_10FD 0x00000014U
792#define SMSC9218I_PHY_PHYSCSR_SPEED_100HD 0x00000008U
793#define SMSC9218I_PHY_PHYSCSR_SPEED_100FD 0x00000018U
794
795/** @} */
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