source: rtems/c/src/lib/libbsp/powerpc/mpc55xxevb/include/smsc9218i.h @ a447527

4.115
Last change on this file since a447527 was a447527, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 7, 2011 at 9:14:06 AM

2011-06-07 Sebastian Huber <sebastian.huber@…>

  • clock/clock-config.c: Fixes to pass psnsext01.
  • startup/bspstart.c: Workaround for GCC 4.6 bug.
  • include/smsc9218i.h, network/smsc9218i.c, Makefile.am: Changes throughout.
  • Property mode set to 100644
File size: 16.1 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup mpc55xx
5 *
6 * @brief SMSC - LAN9218i
7 */
8
9/*
10 * Copyright (c) 2009
11 * embedded brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * rtems@embedded-brains.de
16 *
17 * The license and distribution terms for this file may be
18 * found in the file LICENSE in this distribution or at
19 * http://www.rtems.com/license/LICENSE.
20 */
21
22/**
23 * @name Memory Map
24 * @{
25 */
26
27typedef struct {
28  uint32_t rx_fifo_data;
29  uint32_t rx_fifo_data_aliases [7];
30  uint32_t tx_fifo_data;
31  uint32_t tx_fifo_data_aliases [7];
32  uint32_t rx_fifo_status;
33  uint32_t rx_fifo_status_peek;
34  uint32_t tx_fifo_status;
35  uint32_t tx_fifo_status_peek;
36  uint32_t id_rev;
37  uint32_t irq_cfg;
38  uint32_t int_sts;
39  uint32_t int_en;
40  uint32_t reserved_0;
41  uint32_t byte_test;
42  uint32_t fifo_int;
43  uint32_t rx_cfg;
44  uint32_t tx_cfg;
45  uint32_t hw_cfg;
46  uint32_t rx_dp_ctl;
47  uint32_t rx_fifo_inf;
48  uint32_t tx_fifo_inf;
49  uint32_t pmt_ctrl;
50  uint32_t gpio_cfg;
51  uint32_t gpt_cfg;
52  uint32_t gpt_cnt;
53  uint32_t reserved_1;
54  uint32_t word_swap;
55  uint32_t free_run;
56  uint32_t rx_drop;
57  uint32_t mac_csr_cmd;
58  uint32_t mac_csr_data;
59  uint32_t afc_cfg;
60  uint32_t e2p_cmd;
61  uint32_t e2p_data;
62} smsc9218i_registers;
63
64volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *) 0x3fff8000;
65
66/** @} */
67
68#define SMSC9218I_BIT_POS(pos) \
69  ((pos) > 15 ? \
70    ((pos) > 23 ? (pos) - 24 : (pos) - 8) \
71      : ((pos) > 7 ? (pos) + 8 : (pos) + 24))
72
73#define SMSC9218I_FLAG(pos) \
74  (1U << SMSC9218I_BIT_POS(pos))
75
76#define SMSC9218I_FIELD_8(val, pos) \
77  (((val) & 0xff) << SMSC9218I_BIT_POS(pos))
78
79#define SMSC9218I_GET_FIELD_8(reg, pos) \
80  (((reg) >> SMSC9218I_BIT_POS(pos)) & 0xff)
81
82#define SMSC9218I_FIELD_16(val, pos) \
83  (SMSC9218I_FIELD_8((val) >> 8, (pos) + 8) \
84    | SMSC9218I_FIELD_8((val), pos))
85
86#define SMSC9218I_GET_FIELD_16(reg, pos) \
87  ((SMSC9218I_GET_FIELD_8(reg, (pos) + 8) << 8) \
88    | SMSC9218I_GET_FIELD_8(reg, pos))
89
90#define SMSC9218I_SWAP(val) \
91  ((((val) >> 24) & 0xff) \
92    | ((((val) >> 16) & 0xff) << 8) \
93    | ((((val) >> 8) & 0xff) << 16) \
94    | (((val) & 0xff) << 24))
95
96/**
97 * @name Receive Status
98 * @{
99 */
100
101#define SMSC9218I_RX_STS_FILTER_FAIL SMSC9218I_FLAG(30)
102#define SMSC9218I_RX_STS_GET_LENGTH(reg) (SMSC9218I_GET_FIELD_16(reg, 16) & 0x3fff)
103#define SMSC9218I_RX_STS_ERROR SMSC9218I_FLAG(15)
104#define SMSC9218I_RX_STS_BROADCAST SMSC9218I_FLAG(13)
105#define SMSC9218I_RX_STS_ERROR_LENGTH SMSC9218I_FLAG(12)
106#define SMSC9218I_RX_STS_ERROR_RUNT_FRAME SMSC9218I_FLAG(11)
107#define SMSC9218I_RX_STS_MULTICAST SMSC9218I_FLAG(10)
108#define SMSC9218I_RX_STS_ERROR_TOO_LONG SMSC9218I_FLAG(7)
109#define SMSC9218I_RX_STS_ERROR_COLLISION SMSC9218I_FLAG(6)
110#define SMSC9218I_RX_STS_TYPE SMSC9218I_FLAG(5)
111#define SMSC9218I_RX_STS_WATCHDOG SMSC9218I_FLAG(4)
112#define SMSC9218I_RX_STS_ERROR_MII SMSC9218I_FLAG(3)
113#define SMSC9218I_RX_STS_DRIBBLING_BIT SMSC9218I_FLAG(2)
114#define SMSC9218I_RX_STS_ERROR_CRC SMSC9218I_FLAG(1)
115
116/** @} */
117
118/**
119 * @name Transmit Status
120 * @{
121 */
122
123#define SMSC9218I_TX_STS_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16)
124#define SMSC9218I_TX_STS_ERROR SMSC9218I_FLAG(15)
125#define SMSC9218I_TX_STS_ERROR_LOSS_OF_CARRIER SMSC9218I_FLAG(11)
126#define SMSC9218I_TX_STS_ERROR_NO_CARRIER SMSC9218I_FLAG(10)
127#define SMSC9218I_TX_STS_ERROR_LATE_COLLISION SMSC9218I_FLAG(9)
128#define SMSC9218I_TX_STS_ERROR_EXCESSIVE_COLLISIONS SMSC9218I_FLAG(8)
129#define SMSC9218I_TX_STS_ERROR_EXCESSIVE_DEFERRAL SMSC9218I_FLAG(2)
130#define SMSC9218I_TX_STS_ERROR_DEFERRED SMSC9218I_FLAG(0)
131
132/** @} */
133
134/**
135 * @name Transmit Command A
136 * @{
137 */
138
139#define SMSC9218I_TX_A_IOC SMSC9218I_FLAG(31)
140#define SMSC9218I_TX_A_END_ALIGN_4 0
141#define SMSC9218I_TX_A_END_ALIGN_16 SMSC9218I_FLAG(24)
142#define SMSC9218I_TX_A_END_ALIGN_32 SMSC9218I_FLAG(25)
143#define SMSC9218I_TX_A_DOFF(val) SMSC9218I_FIELD_8(val, 16)
144#define SMSC9218I_TX_A_FIRST SMSC9218I_FLAG(13)
145#define SMSC9218I_TX_A_LAST SMSC9218I_FLAG(12)
146#define SMSC9218I_TX_A_FRAGMENT_LENGTH(val) SMSC9218I_FIELD_16(val, 0)
147
148/** @} */
149
150/**
151 * @name Transmit Command B
152 * @{
153 */
154
155#define SMSC9218I_TX_B_TAG(val) SMSC9218I_FIELD_16(val, 16)
156#define SMSC9218I_TX_B_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16)
157#define SMSC9218I_TX_B_DISABLE_CRC SMSC9218I_FLAG(13)
158#define SMSC9218I_TX_B_DISABLE_PAD SMSC9218I_FLAG(12)
159#define SMSC9218I_TX_B_FRAME_LENGTH(val) SMSC9218I_FIELD_16(val, 0)
160
161/** @} */
162
163/**
164 * @name Chip ID and Revision
165 * @{
166 */
167
168#define SMSC9218I_ID_REV_GET_ID(reg) SMSC9218I_GET_FIELD_16(reg, 16)
169#define SMSC9218I_ID_REV_GET_REV(reg) SMSC9218I_GET_FIELD_16(reg, 0)
170#define SMSC9218I_ID_REV_ID_CHIP_118 0x0118U
171#define SMSC9218I_ID_REV_ID_CHIP_218 0x118aU
172
173/** @} */
174
175/**
176 * @name Interrupt Configuration
177 * @{
178 */
179
180#define SMSC9218I_IRQ_CFG_INT_DEAS(val) SMSC9218I_FIELD_8(val, 24)
181#define SMSC9218I_IRQ_CFG_GET_INT_DEAS(reg) SMSC9218I_GET_FIELD_8(reg, 24)
182#define SMSC9218I_IRQ_CFG_INT_DEAS_CLR SMSC9218I_FLAG(14)
183#define SMSC9218I_IRQ_CFG_INT_DEAS_STS SMSC9218I_FLAG(13)
184#define SMSC9218I_IRQ_CFG_IRQ_INT SMSC9218I_FLAG(12)
185#define SMSC9218I_IRQ_CFG_IRQ_EN SMSC9218I_FLAG(8)
186#define SMSC9218I_IRQ_CFG_IRQ_POL SMSC9218I_FLAG(4)
187#define SMSC9218I_IRQ_CFG_IRQ_TYPE SMSC9218I_FLAG(0)
188
189/** @} */
190
191/**
192 * @name Interrupt Enable and Status
193 * @{
194 */
195
196#define SMSC9218I_INT_SW SMSC9218I_FLAG(31)
197#define SMSC9218I_INT_TXSTOP SMSC9218I_FLAG(25)
198#define SMSC9218I_INT_RXSTOP SMSC9218I_FLAG(24)
199#define SMSC9218I_INT_RXDFH SMSC9218I_FLAG(23)
200#define SMSC9218I_INT_TIOC SMSC9218I_FLAG(21)
201#define SMSC9218I_INT_RXD SMSC9218I_FLAG(20)
202#define SMSC9218I_INT_GPT SMSC9218I_FLAG(19)
203#define SMSC9218I_INT_PHY SMSC9218I_FLAG(18)
204#define SMSC9218I_INT_PME SMSC9218I_FLAG(17)
205#define SMSC9218I_INT_TXSO SMSC9218I_FLAG(16)
206#define SMSC9218I_INT_RWT SMSC9218I_FLAG(15)
207#define SMSC9218I_INT_RXE SMSC9218I_FLAG(14)
208#define SMSC9218I_INT_TXE SMSC9218I_FLAG(13)
209#define SMSC9218I_INT_TDFO SMSC9218I_FLAG(10)
210#define SMSC9218I_INT_TDFA SMSC9218I_FLAG(9)
211#define SMSC9218I_INT_TSFF SMSC9218I_FLAG(8)
212#define SMSC9218I_INT_TSFL SMSC9218I_FLAG(7)
213#define SMSC9218I_INT_RSFF SMSC9218I_FLAG(4)
214#define SMSC9218I_INT_RSFL SMSC9218I_FLAG(3)
215#define SMSC9218I_INT_GPIO2 SMSC9218I_FLAG(2)
216#define SMSC9218I_INT_GPIO1 SMSC9218I_FLAG(1)
217#define SMSC9218I_INT_GPIO0 SMSC9218I_FLAG(0)
218
219/** @} */
220
221/**
222 * @name Byte Order Testing
223 * @{
224 */
225
226#define SMSC9218I_BYTE_TEST SMSC9218I_SWAP(0x87654321U)
227
228/** @} */
229
230/**
231 * @name FIFO Level Interrupts
232 * @{
233 */
234
235#define SMSC9218I_FIFO_INT_TDAL(val) SMSC9218I_FIELD_8(val, 24)
236#define SMSC9218I_FIFO_INT_GET_TDAL(reg) SMSC9218I_GET_FIELD_8(reg, 24)
237#define SMSC9218I_FIFO_INT_TSL(val) SMSC9218I_FIELD_8(val, 16)
238#define SMSC9218I_FIFO_INT_GET_TSL(reg) SMSC9218I_GET_FIELD_8(reg, 16)
239#define SMSC9218I_FIFO_INT_RSL(val) SMSC9218I_FIELD_8(val, 0)
240#define SMSC9218I_FIFO_INT_GET_RSL(reg) SMSC9218I_GET_FIELD_8(reg, 0)
241
242/** @} */
243
244/**
245 * @name Receive Configuration
246 * @{
247 */
248
249#define SMSC9218I_RX_CFG_END_ALIGN_4 0
250#define SMSC9218I_RX_CFG_END_ALIGN_16 SMSC9218I_FLAG(30)
251#define SMSC9218I_RX_CFG_END_ALIGN_32 SMSC9218I_FLAG(31)
252#define SMSC9218I_RX_CFG_DMA_CNT(val) SMSC9218I_FIELD_8(val, 24)
253#define SMSC9218I_RX_CFG_GET_DMA_CNT(reg) SMSC9218I_GET_FIELD_8(reg, 24)
254#define SMSC9218I_RX_CFG_DUMP SMSC9218I_FLAG(15)
255#define SMSC9218I_RX_CFG_DOFF(val) SMSC9218I_FIELD_8(val, 8)
256#define SMSC9218I_RX_CFG_GET_DOFF(reg) SMSC9218I_GET_FIELD_8(reg, 8)
257
258/** @} */
259
260/**
261 * @name Transmit Configuration
262 * @{
263 */
264
265#define SMSC9218I_TX_CFG_SDUMP SMSC9218I_FLAG(15)
266#define SMSC9218I_TX_CFG_DDUMP SMSC9218I_FLAG(14)
267#define SMSC9218I_TX_CFG_SAO SMSC9218I_FLAG(2)
268#define SMSC9218I_TX_CFG_ON SMSC9218I_FLAG(1)
269#define SMSC9218I_TX_CFG_STOP SMSC9218I_FLAG(0)
270
271/** @} */
272
273/**
274 * @name Hardware Configuration
275 * @{
276 */
277
278#define SMSC9218I_HW_CFG_AMDIX SMSC9218I_FLAG(24)
279#define SMSC9218I_HW_CFG_MBO SMSC9218I_FLAG(20)
280#define SMSC9218I_HW_CFG_TX_FIF_SZ(val) SMSC9218I_FIELD_8(val, 16)
281#define SMSC9218I_HW_CFG_GET_TX_FIF_SZ(reg) SMSC9218I_GET_FIELD_8(reg, 16)
282#define SMSC9218I_HW_CFG_BITMD_32 SMSC9218I_FLAG(2)
283#define SMSC9218I_HW_CFG_SRST_TO SMSC9218I_FLAG(1)
284#define SMSC9218I_HW_CFG_SRST SMSC9218I_FLAG(0)
285
286/** @} */
287
288/**
289 * @name Receive Datapath Control
290 * @{
291 */
292
293#define SMSC9218I_RX_DP_CTRL_FFWD SMSC9218I_FLAG(31)
294
295/** @} */
296
297/**
298 * @name Receive FIFO Information
299 * @{
300 */
301
302#define SMSC9218I_RX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16)
303#define SMSC9218I_RX_FIFO_INF_GET_DUSED(reg) SMSC9218I_GET_FIELD_16(reg, 0)
304
305/** @} */
306
307/**
308 * @name Transmit FIFO Information
309 * @{
310 */
311
312#define SMSC9218I_TX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16)
313#define SMSC9218I_TX_FIFO_INF_GET_FREE(reg) SMSC9218I_GET_FIELD_16(reg, 0)
314
315/** @} */
316
317/**
318 * @name Power Management Control
319 * @{
320 */
321
322#define SMSC9218I_PMT_CTRL_PM_MODE_D0 0
323#define SMSC9218I_PMT_CTRL_PM_MODE_D1 SMSC9218I_FLAG(12)
324#define SMSC9218I_PMT_CTRL_PM_MODE_D2 SMSC9218I_FLAG(13)
325#define SMSC9218I_PMT_CTRL_PHY_RST SMSC9218I_FLAG(10)
326#define SMSC9218I_PMT_CTRL_WOL_EN SMSC9218I_FLAG(9)
327#define SMSC9218I_PMT_CTRL_ED_EN SMSC9218I_FLAG(8)
328#define SMSC9218I_PMT_CTRL_PME_TYPE_PUPU SMSC9218I_FLAG(6)
329#define SMSC9218I_PMT_CTRL_WUPS_NO 0
330#define SMSC9218I_PMT_CTRL_WUPS_ENERGY SMSC9218I_FLAG(4)
331#define SMSC9218I_PMT_CTRL_WUPS_MAGIC SMSC9218I_FLAG(5)
332#define SMSC9218I_PMT_CTRL_PME_IND SMSC9218I_FLAG(3)
333#define SMSC9218I_PMT_CTRL_PME_POL SMSC9218I_FLAG(2)
334#define SMSC9218I_PMT_CTRL_PME_EN SMSC9218I_FLAG(1)
335#define SMSC9218I_PMT_CTRL_READY SMSC9218I_FLAG(0)
336
337/** @} */
338
339/**
340 * @name General Purpose IO Configuration
341 * @{
342 */
343
344#define SMSC9218I_GPIO_CFG_LED3 SMSC9218I_FLAG(30)
345#define SMSC9218I_GPIO_CFG_LED2 SMSC9218I_FLAG(29)
346#define SMSC9218I_GPIO_CFG_LED1 SMSC9218I_FLAG(28)
347#define SMSC9218I_GPIO_CFG_GPIO2_INT_POL SMSC9218I_FLAG(26)
348#define SMSC9218I_GPIO_CFG_GPIO1_INT_POL SMSC9218I_FLAG(25)
349#define SMSC9218I_GPIO_CFG_GPIO0_INT_POL SMSC9218I_FLAG(24)
350#define SMSC9218I_GPIO_CFG_GPIOBUF2 SMSC9218I_FLAG(18)
351#define SMSC9218I_GPIO_CFG_GPIOBUF1 SMSC9218I_FLAG(17)
352#define SMSC9218I_GPIO_CFG_GPIOBUF0 SMSC9218I_FLAG(16)
353#define SMSC9218I_GPIO_CFG_GPIODIR2 SMSC9218I_FLAG(10)
354#define SMSC9218I_GPIO_CFG_GPIODIR1 SMSC9218I_FLAG(9)
355#define SMSC9218I_GPIO_CFG_GPIODIR0 SMSC9218I_FLAG(8)
356#define SMSC9218I_GPIO_CFG_GPO4 SMSC9218I_FLAG(4)
357#define SMSC9218I_GPIO_CFG_GPO3 SMSC9218I_FLAG(3)
358#define SMSC9218I_GPIO_CFG_GPIO0 SMSC9218I_FLAG(0)
359#define SMSC9218I_GPIO_CFG_GPIO2 SMSC9218I_FLAG(2)
360#define SMSC9218I_GPIO_CFG_GPIO1 SMSC9218I_FLAG(1)
361
362/** @} */
363
364/**
365 * @name General Purpose Timer Configuration
366 * @{
367 */
368
369#define SMSC9218I_GPT_CFG_TIMER_EN SMSC9218I_FLAG(29)
370#define SMSC9218I_GPT_CFG_LOAD(val) SMSC9218I_FIELD_16(val, 0)
371#define SMSC9218I_GPT_CFG_GET_LOAD(reg) SMSC9218I_GET_FIELD_16(reg, 0)
372
373/** @} */
374
375/**
376 * @name General Purpose Timer Count
377 * @{
378 */
379
380#define SMSC9218I_GPT_CNT_GET_CNT SMSC9218I_GET_FIELD_16(reg, 0)
381
382/** @} */
383
384/**
385 * @name Word Swap
386 * @{
387 */
388
389#define SMSC9218I_ENDIAN_BIG 0xffffffffU
390
391/** @} */
392
393/**
394 * @name Free Run Counter
395 * @{
396 */
397
398#define SMSC9218I_FREE_RUN_GET(reg) SMSC9218I_SWAP(reg)
399
400/** @} */
401
402/**
403 * @name Receiver Dropped Frames Counter
404 * @{
405 */
406
407#define SMSC9218I_RX_DROP_GET(reg) SMSC9218I_SWAP(reg)
408
409/** @} */
410
411/**
412 * @name EEPROM Command Register
413 * @{
414 */
415
416#define SMSC9218I_E2P_CMD_EPC_BUSY SMSC9218I_FLAG(31)
417
418/** @} */
419
420/**
421 * @name MAC Control and Status Synchronizer Command
422 * @{
423 */
424
425#define SMSC9218I_MAC_CSR_CMD_BUSY SMSC9218I_FLAG(31)
426#define SMSC9218I_MAC_CSR_CMD_READ SMSC9218I_FLAG(30)
427#define SMSC9218I_MAC_CSR_CMD_ADDR(val) SMSC9218I_FIELD_8(val, 0)
428#define SMSC9218I_MAC_CSR_CMD_GET_ADDR(reg) SMSC9218I_GET_FIELD_8(reg, 0)
429
430/** @} */
431
432/**
433 * @name MAC Control Register
434 * @{
435 */
436
437#define SMSC9218I_MAC_CR 0x00000001U
438#define SMSC9218I_MAC_CR_RXALL 0x80000000U
439#define SMSC9218I_MAC_CR_HBDIS 0x10000000U
440#define SMSC9218I_MAC_CR_RCVOWN 0x00800000U
441#define SMSC9218I_MAC_CR_LOOPBK 0x00200000U
442#define SMSC9218I_MAC_CR_FDPX 0x00100000U
443#define SMSC9218I_MAC_CR_MCPAS 0x00080000U
444#define SMSC9218I_MAC_CR_PRMS 0x00040000U
445#define SMSC9218I_MAC_CR_INVFILT 0x00020000U
446#define SMSC9218I_MAC_CR_PASSBAD 0x00010000U
447#define SMSC9218I_MAC_CR_HFILT 0x00008000U
448#define SMSC9218I_MAC_CR_HPFILT 0x00002000U
449#define SMSC9218I_MAC_CR_LCOLL 0x00001000U
450#define SMSC9218I_MAC_CR_BCAST 0x00000800U
451#define SMSC9218I_MAC_CR_DISRTY 0x00000400U
452#define SMSC9218I_MAC_CR_PADSTR 0x00000100U
453#define SMSC9218I_MAC_CR_BOLMT_MASK 0x000000c0U
454#define SMSC9218I_MAC_CR_BOLMT_10 0x00000000U
455#define SMSC9218I_MAC_CR_BOLMT_8 0x00000040U
456#define SMSC9218I_MAC_CR_BOLMT_4 0x00000080U
457#define SMSC9218I_MAC_CR_BOLMT_1 0x000000c0U
458#define SMSC9218I_MAC_CR_DFCHK 0x00000020U
459#define SMSC9218I_MAC_CR_TXEN 0x00000008U
460#define SMSC9218I_MAC_CR_RXEN 0x00000004U
461
462/** @} */
463
464/**
465 * @name MAC Address High
466 * @{
467 */
468
469#define SMSC9218I_MAC_ADDRH 0x00000002U
470#define SMSC9218I_MAC_ADDRH_MASK 0x0000ffffU
471
472/** @} */
473
474/**
475 * @name MAC Address Low
476 * @{
477 */
478
479#define SMSC9218I_MAC_ADDRL 0x00000003U
480#define SMSC9218I_MAC_ADDRL_MASK 0xffffffffU
481
482/** @} */
483
484/**
485 * @name Multicast Hash Table High
486 * @{
487 */
488
489#define SMSC9218I_MAC_HASHH 0x00000004U
490#define SMSC9218I_MAC_HASHH_MASK 0xffffffffU
491
492/** @} */
493
494/**
495 * @name Multicast Hash Table Low
496 * @{
497 */
498
499#define SMSC9218I_MAC_HASHL 0x00000005U
500#define SMSC9218I_MAC_HASHL_MASK 0xffffffffU
501
502/** @} */
503
504/**
505 * @name MII Access
506 * @{
507 */
508
509#define SMSC9218I_MAC_MII_ACC 0x00000006U
510#define SMSC9218I_MAC_MII_ACC_PHY_DEFAULT (1U << 11)
511#define SMSC9218I_MAC_MII_ACC_WRITE (1U << 1)
512#define SMSC9218I_MAC_MII_ACC_BUSY (1U << 0)
513#define SMSC9218I_MAC_MII_ACC_ADDR(addr) ((addr) << 6)
514
515/** @} */
516
517/**
518 * @name MII Data
519 * @{
520 */
521
522#define SMSC9218I_MAC_MII_DATA 0x00000007U
523
524/** @} */
525
526/**
527 * @name Flow Control
528 * @{
529 */
530
531#define SMSC9218I_MAC_FLOW 0x00000008U
532#define SMSC9218I_MAC_FLOW_FCPT_MASK 0xffff0000U
533#define SMSC9218I_MAC_FLOW_FCPASS 0x00000004U
534#define SMSC9218I_MAC_FLOW_FCEN 0x00000002U
535#define SMSC9218I_MAC_FLOW_FCBSY 0x00000001U
536
537/** @} */
538
539/**
540 * @name VLAN1 Tag
541 * @{
542 */
543
544#define SMSC9218I_MAC_VLAN1 0x00000009U
545
546/** @} */
547
548/**
549 * @name VLAN2 Tag
550 * @{
551 */
552
553#define SMSC9218I_MAC_VLAN2 0x0000000aU
554
555/** @} */
556
557/**
558 * @name Wake-up Frame Filter
559 * @{
560 */
561
562#define SMSC9218I_MAC_WUFF 0x0000000bU
563
564/** @} */
565
566/**
567 * @name Wake-up Control and Status
568 * @{
569 */
570
571#define SMSC9218I_MAC_WUCSR 0x0000000cU
572#define SMSC9218I_MAC_WUCSR_GUE 0x00000200U
573#define SMSC9218I_MAC_WUCSR_WUFR 0x00000040U
574#define SMSC9218I_MAC_WUCSR_MPR 0x00000020U
575#define SMSC9218I_MAC_WUCSR_WUEN 0x00000004U
576#define SMSC9218I_MAC_WUCSR_MPEN 0x00000002U
577
578/** @} */
579
580/**
581 * @name PHY Identifier 1
582 * @{
583 */
584
585#define SMSC9218I_PHY_ID1_LAN9118 0x7
586
587/** @} */
588
589/**
590 * @name PHY Identifier 2
591 * @{
592 */
593
594#define SMSC9218I_PHY_ID2_LAN9218 0xc0c3
595
596/** @} */
597
598/**
599 * @name Mode Control and Status
600 * @{
601 */
602
603#define SMSC9218I_PHY_MCSR 0x00000011U
604#define SMSC9218I_PHY_MCSR_EDPWRDOWN 0x00002000U
605#define SMSC9218I_PHY_MCSR_ENERGYON 0x00000002U
606
607/** @} */
608
609/**
610 * @name Special Modes
611 * @{
612 */
613
614#define SMSC9218I_PHY_SPMODES 0x00000012U
615
616/** @} */
617
618/**
619 * @name Special Control and Status Indications
620 * @{
621 */
622
623#define SMSC9218I_PHY_CSIR 0x0000001bU
624#define SMSC9218I_PHY_CSIR_SQEOFF 0x00000800U
625#define SMSC9218I_PHY_CSIR_FEFIEN 0x00000020U
626#define SMSC9218I_PHY_CSIR_XPOL 0x00000010U
627
628/** @} */
629
630/**
631 * @name Interrupt Source Flag
632 * @{
633 */
634
635#define SMSC9218I_PHY_ISR 0x0000001dU
636#define SMSC9218I_PHY_ISR_INT7 0x00000080U
637#define SMSC9218I_PHY_ISR_INT6 0x00000040U
638#define SMSC9218I_PHY_ISR_INT5 0x00000020U
639#define SMSC9218I_PHY_ISR_INT4 0x00000010U
640#define SMSC9218I_PHY_ISR_INT3 0x00000008U
641#define SMSC9218I_PHY_ISR_INT2 0x00000004U
642#define SMSC9218I_PHY_ISR_INT1 0x00000002U
643
644/** @} */
645
646/**
647 * @name Interrupt Mask
648 * @{
649 */
650
651#define SMSC9218I_PHY_IMR 0x0000001eU
652#define SMSC9218I_PHY_IMR_INT7 0x00000080U
653#define SMSC9218I_PHY_IMR_INT6 0x00000040U
654#define SMSC9218I_PHY_IMR_INT5 0x00000020U
655#define SMSC9218I_PHY_IMR_INT4 0x00000010U
656#define SMSC9218I_PHY_IMR_INT3 0x00000008U
657#define SMSC9218I_PHY_IMR_INT2 0x00000004U
658#define SMSC9218I_PHY_IMR_INT1 0x00000002U
659
660/** @} */
661
662/**
663 * @name PHY Special Control and Status
664 * @{
665 */
666
667#define SMSC9218I_PHY_PHYSCSR 0x0000001fU
668#define SMSC9218I_PHY_PHYSCSR_ANDONE 0x00001000U
669#define SMSC9218I_PHY_PHYSCSR_4B5B_EN 0x00000040U
670#define SMSC9218I_PHY_PHYSCSR_SPEED_MASK 0x0000001cU
671#define SMSC9218I_PHY_PHYSCSR_SPEED_10HD 0x00000004U
672#define SMSC9218I_PHY_PHYSCSR_SPEED_10FD 0x00000014U
673#define SMSC9218I_PHY_PHYSCSR_SPEED_100HD 0x00000008U
674#define SMSC9218I_PHY_PHYSCSR_SPEED_100FD 0x00000018U
675
676/** @} */
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