1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc55xx |
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5 | * |
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6 | * @brief SMSC - LAN9218i |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009 |
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11 | * embedded brains GmbH |
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12 | * Obere Lagerstr. 30 |
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13 | * D-82178 Puchheim |
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14 | * Germany |
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15 | * rtems@embedded-brains.de |
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16 | * |
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17 | * The license and distribution terms for this file may be |
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18 | * found in the file LICENSE in this distribution or at |
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19 | * http://www.rtems.com/license/LICENSE. |
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20 | */ |
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21 | |
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22 | /** |
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23 | * @name Memory Map |
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24 | * @{ |
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25 | */ |
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26 | |
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27 | typedef struct { |
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28 | uint32_t rx_fifo_data; |
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29 | uint32_t rx_fifo_data_aliases [7]; |
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30 | uint32_t tx_fifo_data; |
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31 | uint32_t tx_fifo_data_aliases [7]; |
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32 | uint32_t rx_fifo_status; |
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33 | uint32_t rx_fifo_status_peek; |
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34 | uint32_t tx_fifo_status; |
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35 | uint32_t tx_fifo_status_peek; |
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36 | uint32_t id_rev; |
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37 | uint32_t irq_cfg; |
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38 | uint32_t int_sts; |
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39 | uint32_t int_en; |
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40 | uint32_t reserved_0; |
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41 | uint32_t byte_test; |
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42 | uint32_t fifo_int; |
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43 | uint32_t rx_cfg; |
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44 | uint32_t tx_cfg; |
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45 | uint32_t hw_cfg; |
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46 | uint32_t rx_dp_ctl; |
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47 | uint32_t rx_fifo_inf; |
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48 | uint32_t tx_fifo_inf; |
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49 | uint32_t pmt_ctrl; |
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50 | uint32_t gpio_cfg; |
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51 | uint32_t gpt_cfg; |
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52 | uint32_t gpt_cnt; |
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53 | uint32_t reserved_1; |
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54 | uint32_t word_swap; |
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55 | uint32_t free_run; |
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56 | uint32_t rx_drop; |
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57 | uint32_t mac_csr_cmd; |
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58 | uint32_t mac_csr_data; |
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59 | uint32_t afc_cfg; |
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60 | uint32_t e2p_cmd; |
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61 | uint32_t e2p_data; |
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62 | } smsc9218i_registers; |
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63 | |
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64 | volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *) 0x3fff8000; |
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65 | |
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66 | /** @} */ |
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67 | |
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68 | #define SMSC9218I_BIT_POS(pos) \ |
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69 | ((pos) > 15 ? \ |
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70 | ((pos) > 23 ? (pos) - 24 : (pos) - 8) \ |
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71 | : ((pos) > 7 ? (pos) + 8 : (pos) + 24)) |
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72 | |
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73 | #define SMSC9218I_FLAG(pos) \ |
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74 | (1U << SMSC9218I_BIT_POS(pos)) |
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75 | |
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76 | #define SMSC9218I_FIELD_8(val, pos) \ |
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77 | (((val) & 0xff) << SMSC9218I_BIT_POS(pos)) |
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78 | |
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79 | #define SMSC9218I_GET_FIELD_8(reg, pos) \ |
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80 | (((reg) >> SMSC9218I_BIT_POS(pos)) & 0xff) |
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81 | |
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82 | #define SMSC9218I_FIELD_16(val, pos) \ |
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83 | (SMSC9218I_FIELD_8((val) >> 8, (pos) + 8) \ |
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84 | | SMSC9218I_FIELD_8((val), pos)) |
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85 | |
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86 | #define SMSC9218I_GET_FIELD_16(reg, pos) \ |
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87 | ((SMSC9218I_GET_FIELD_8(reg, (pos) + 8) << 8) \ |
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88 | | SMSC9218I_GET_FIELD_8(reg, pos)) |
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89 | |
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90 | #define SMSC9218I_SWAP(val) \ |
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91 | ((((val) >> 24) & 0xff) \ |
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92 | | ((((val) >> 16) & 0xff) << 8) \ |
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93 | | ((((val) >> 8) & 0xff) << 16) \ |
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94 | | (((val) & 0xff) << 24)) |
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95 | |
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96 | /** |
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97 | * @name Receive Status |
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98 | * @{ |
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99 | */ |
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100 | |
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101 | #define SMSC9218I_RX_STS_FILTER_FAIL SMSC9218I_FLAG(30) |
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102 | #define SMSC9218I_RX_STS_GET_LENGTH(reg) (SMSC9218I_GET_FIELD_16(reg, 16) & 0x3fff) |
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103 | #define SMSC9218I_RX_STS_ERROR SMSC9218I_FLAG(15) |
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104 | #define SMSC9218I_RX_STS_BROADCAST SMSC9218I_FLAG(13) |
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105 | #define SMSC9218I_RX_STS_ERROR_LENGTH SMSC9218I_FLAG(12) |
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106 | #define SMSC9218I_RX_STS_ERROR_RUNT_FRAME SMSC9218I_FLAG(11) |
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107 | #define SMSC9218I_RX_STS_MULTICAST SMSC9218I_FLAG(10) |
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108 | #define SMSC9218I_RX_STS_ERROR_TOO_LONG SMSC9218I_FLAG(7) |
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109 | #define SMSC9218I_RX_STS_ERROR_COLLISION SMSC9218I_FLAG(6) |
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110 | #define SMSC9218I_RX_STS_TYPE SMSC9218I_FLAG(5) |
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111 | #define SMSC9218I_RX_STS_WATCHDOG SMSC9218I_FLAG(4) |
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112 | #define SMSC9218I_RX_STS_ERROR_MII SMSC9218I_FLAG(3) |
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113 | #define SMSC9218I_RX_STS_DRIBBLING_BIT SMSC9218I_FLAG(2) |
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114 | #define SMSC9218I_RX_STS_ERROR_CRC SMSC9218I_FLAG(1) |
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115 | |
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116 | /** @} */ |
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117 | |
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118 | /** |
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119 | * @name Transmit Status |
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120 | * @{ |
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121 | */ |
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122 | |
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123 | #define SMSC9218I_TX_STS_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16) |
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124 | #define SMSC9218I_TX_STS_ERROR SMSC9218I_FLAG(15) |
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125 | #define SMSC9218I_TX_STS_ERROR_LOSS_OF_CARRIER SMSC9218I_FLAG(11) |
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126 | #define SMSC9218I_TX_STS_ERROR_NO_CARRIER SMSC9218I_FLAG(10) |
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127 | #define SMSC9218I_TX_STS_ERROR_LATE_COLLISION SMSC9218I_FLAG(9) |
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128 | #define SMSC9218I_TX_STS_ERROR_EXCESSIVE_COLLISIONS SMSC9218I_FLAG(8) |
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129 | #define SMSC9218I_TX_STS_ERROR_EXCESSIVE_DEFERRAL SMSC9218I_FLAG(2) |
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130 | #define SMSC9218I_TX_STS_ERROR_DEFERRED SMSC9218I_FLAG(0) |
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131 | |
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132 | /** @} */ |
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133 | |
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134 | /** |
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135 | * @name Transmit Command A |
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136 | * @{ |
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137 | */ |
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138 | |
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139 | #define SMSC9218I_TX_A_IOC SMSC9218I_FLAG(31) |
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140 | #define SMSC9218I_TX_A_END_ALIGN_4 0 |
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141 | #define SMSC9218I_TX_A_END_ALIGN_16 SMSC9218I_FLAG(24) |
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142 | #define SMSC9218I_TX_A_END_ALIGN_32 SMSC9218I_FLAG(25) |
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143 | #define SMSC9218I_TX_A_DOFF(val) SMSC9218I_FIELD_8(val, 16) |
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144 | #define SMSC9218I_TX_A_FIRST SMSC9218I_FLAG(13) |
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145 | #define SMSC9218I_TX_A_LAST SMSC9218I_FLAG(12) |
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146 | #define SMSC9218I_TX_A_FRAGMENT_LENGTH(val) SMSC9218I_FIELD_16(val, 0) |
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147 | |
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148 | /** @} */ |
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149 | |
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150 | /** |
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151 | * @name Transmit Command B |
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152 | * @{ |
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153 | */ |
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154 | |
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155 | #define SMSC9218I_TX_B_TAG(val) SMSC9218I_FIELD_16(val, 16) |
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156 | #define SMSC9218I_TX_B_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16) |
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157 | #define SMSC9218I_TX_B_DISABLE_CRC SMSC9218I_FLAG(13) |
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158 | #define SMSC9218I_TX_B_DISABLE_PAD SMSC9218I_FLAG(12) |
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159 | #define SMSC9218I_TX_B_FRAME_LENGTH(val) SMSC9218I_FIELD_16(val, 0) |
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160 | |
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161 | /** @} */ |
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162 | |
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163 | /** |
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164 | * @name Chip ID and Revision |
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165 | * @{ |
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166 | */ |
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167 | |
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168 | #define SMSC9218I_ID_REV_GET_ID(reg) SMSC9218I_GET_FIELD_16(reg, 16) |
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169 | #define SMSC9218I_ID_REV_GET_REV(reg) SMSC9218I_GET_FIELD_16(reg, 0) |
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170 | #define SMSC9218I_ID_REV_ID_CHIP_118 0x0118U |
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171 | #define SMSC9218I_ID_REV_ID_CHIP_218 0x118aU |
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172 | |
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173 | /** @} */ |
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174 | |
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175 | /** |
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176 | * @name Interrupt Configuration |
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177 | * @{ |
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178 | */ |
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179 | |
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180 | #define SMSC9218I_IRQ_CFG_INT_DEAS(val) SMSC9218I_FIELD_8(val, 24) |
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181 | #define SMSC9218I_IRQ_CFG_GET_INT_DEAS(reg) SMSC9218I_GET_FIELD_8(reg, 24) |
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182 | #define SMSC9218I_IRQ_CFG_INT_DEAS_CLR SMSC9218I_FLAG(14) |
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183 | #define SMSC9218I_IRQ_CFG_INT_DEAS_STS SMSC9218I_FLAG(13) |
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184 | #define SMSC9218I_IRQ_CFG_IRQ_INT SMSC9218I_FLAG(12) |
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185 | #define SMSC9218I_IRQ_CFG_IRQ_EN SMSC9218I_FLAG(8) |
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186 | #define SMSC9218I_IRQ_CFG_IRQ_POL SMSC9218I_FLAG(4) |
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187 | #define SMSC9218I_IRQ_CFG_IRQ_TYPE SMSC9218I_FLAG(0) |
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188 | |
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189 | /** @} */ |
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190 | |
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191 | /** |
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192 | * @name Interrupt Enable and Status |
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193 | * @{ |
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194 | */ |
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195 | |
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196 | #define SMSC9218I_INT_SW SMSC9218I_FLAG(31) |
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197 | #define SMSC9218I_INT_TXSTOP SMSC9218I_FLAG(25) |
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198 | #define SMSC9218I_INT_RXSTOP SMSC9218I_FLAG(24) |
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199 | #define SMSC9218I_INT_RXDFH SMSC9218I_FLAG(23) |
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200 | #define SMSC9218I_INT_TIOC SMSC9218I_FLAG(21) |
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201 | #define SMSC9218I_INT_RXD SMSC9218I_FLAG(20) |
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202 | #define SMSC9218I_INT_GPT SMSC9218I_FLAG(19) |
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203 | #define SMSC9218I_INT_PHY SMSC9218I_FLAG(18) |
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204 | #define SMSC9218I_INT_PME SMSC9218I_FLAG(17) |
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205 | #define SMSC9218I_INT_TXSO SMSC9218I_FLAG(16) |
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206 | #define SMSC9218I_INT_RWT SMSC9218I_FLAG(15) |
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207 | #define SMSC9218I_INT_RXE SMSC9218I_FLAG(14) |
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208 | #define SMSC9218I_INT_TXE SMSC9218I_FLAG(13) |
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209 | #define SMSC9218I_INT_TDFO SMSC9218I_FLAG(10) |
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210 | #define SMSC9218I_INT_TDFA SMSC9218I_FLAG(9) |
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211 | #define SMSC9218I_INT_TSFF SMSC9218I_FLAG(8) |
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212 | #define SMSC9218I_INT_TSFL SMSC9218I_FLAG(7) |
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213 | #define SMSC9218I_INT_RSFF SMSC9218I_FLAG(4) |
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214 | #define SMSC9218I_INT_RSFL SMSC9218I_FLAG(3) |
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215 | #define SMSC9218I_INT_GPIO2 SMSC9218I_FLAG(2) |
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216 | #define SMSC9218I_INT_GPIO1 SMSC9218I_FLAG(1) |
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217 | #define SMSC9218I_INT_GPIO0 SMSC9218I_FLAG(0) |
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218 | |
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219 | /** @} */ |
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220 | |
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221 | /** |
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222 | * @name Byte Order Testing |
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223 | * @{ |
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224 | */ |
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225 | |
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226 | #define SMSC9218I_BYTE_TEST SMSC9218I_SWAP(0x87654321U) |
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227 | |
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228 | /** @} */ |
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229 | |
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230 | /** |
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231 | * @name FIFO Level Interrupts |
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232 | * @{ |
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233 | */ |
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234 | |
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235 | #define SMSC9218I_FIFO_INT_TDAL(val) SMSC9218I_FIELD_8(val, 24) |
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236 | #define SMSC9218I_FIFO_INT_GET_TDAL(reg) SMSC9218I_GET_FIELD_8(reg, 24) |
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237 | #define SMSC9218I_FIFO_INT_TSL(val) SMSC9218I_FIELD_8(val, 16) |
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238 | #define SMSC9218I_FIFO_INT_GET_TSL(reg) SMSC9218I_GET_FIELD_8(reg, 16) |
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239 | #define SMSC9218I_FIFO_INT_RSL(val) SMSC9218I_FIELD_8(val, 0) |
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240 | #define SMSC9218I_FIFO_INT_GET_RSL(reg) SMSC9218I_GET_FIELD_8(reg, 0) |
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241 | |
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242 | /** @} */ |
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243 | |
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244 | /** |
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245 | * @name Receive Configuration |
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246 | * @{ |
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247 | */ |
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248 | |
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249 | #define SMSC9218I_RX_CFG_END_ALIGN_4 0 |
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250 | #define SMSC9218I_RX_CFG_END_ALIGN_16 SMSC9218I_FLAG(30) |
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251 | #define SMSC9218I_RX_CFG_END_ALIGN_32 SMSC9218I_FLAG(31) |
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252 | #define SMSC9218I_RX_CFG_DMA_CNT(val) SMSC9218I_FIELD_8(val, 24) |
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253 | #define SMSC9218I_RX_CFG_GET_DMA_CNT(reg) SMSC9218I_GET_FIELD_8(reg, 24) |
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254 | #define SMSC9218I_RX_CFG_DUMP SMSC9218I_FLAG(15) |
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255 | #define SMSC9218I_RX_CFG_DOFF(val) SMSC9218I_FIELD_8(val, 8) |
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256 | #define SMSC9218I_RX_CFG_GET_DOFF(reg) SMSC9218I_GET_FIELD_8(reg, 8) |
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257 | |
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258 | /** @} */ |
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259 | |
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260 | /** |
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261 | * @name Transmit Configuration |
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262 | * @{ |
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263 | */ |
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264 | |
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265 | #define SMSC9218I_TX_CFG_SDUMP SMSC9218I_FLAG(15) |
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266 | #define SMSC9218I_TX_CFG_DDUMP SMSC9218I_FLAG(14) |
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267 | #define SMSC9218I_TX_CFG_SAO SMSC9218I_FLAG(2) |
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268 | #define SMSC9218I_TX_CFG_ON SMSC9218I_FLAG(1) |
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269 | #define SMSC9218I_TX_CFG_STOP SMSC9218I_FLAG(0) |
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270 | |
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271 | /** @} */ |
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272 | |
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273 | /** |
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274 | * @name Hardware Configuration |
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275 | * @{ |
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276 | */ |
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277 | |
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278 | #define SMSC9218I_HW_CFG_AMDIX SMSC9218I_FLAG(24) |
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279 | #define SMSC9218I_HW_CFG_MBO SMSC9218I_FLAG(20) |
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280 | #define SMSC9218I_HW_CFG_TX_FIF_SZ(val) SMSC9218I_FIELD_8(val, 16) |
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281 | #define SMSC9218I_HW_CFG_GET_TX_FIF_SZ(reg) SMSC9218I_GET_FIELD_8(reg, 16) |
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282 | #define SMSC9218I_HW_CFG_BITMD_32 SMSC9218I_FLAG(2) |
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283 | #define SMSC9218I_HW_CFG_SRST_TO SMSC9218I_FLAG(1) |
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284 | #define SMSC9218I_HW_CFG_SRST SMSC9218I_FLAG(0) |
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285 | |
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286 | /** @} */ |
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287 | |
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288 | /** |
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289 | * @name Receive Datapath Control |
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290 | * @{ |
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291 | */ |
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292 | |
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293 | #define SMSC9218I_RX_DP_CTRL_FFWD SMSC9218I_FLAG(31) |
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294 | |
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295 | /** @} */ |
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296 | |
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297 | /** |
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298 | * @name Receive FIFO Information |
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299 | * @{ |
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300 | */ |
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301 | |
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302 | #define SMSC9218I_RX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16) |
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303 | #define SMSC9218I_RX_FIFO_INF_GET_DUSED(reg) SMSC9218I_GET_FIELD_16(reg, 0) |
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304 | |
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305 | /** @} */ |
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306 | |
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307 | /** |
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308 | * @name Transmit FIFO Information |
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309 | * @{ |
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310 | */ |
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311 | |
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312 | #define SMSC9218I_TX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16) |
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313 | #define SMSC9218I_TX_FIFO_INF_GET_FREE(reg) SMSC9218I_GET_FIELD_16(reg, 0) |
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314 | |
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315 | /** @} */ |
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316 | |
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317 | /** |
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318 | * @name Power Management Control |
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319 | * @{ |
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320 | */ |
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321 | |
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322 | #define SMSC9218I_PMT_CTRL_PM_MODE_D0 0 |
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323 | #define SMSC9218I_PMT_CTRL_PM_MODE_D1 SMSC9218I_FLAG(12) |
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324 | #define SMSC9218I_PMT_CTRL_PM_MODE_D2 SMSC9218I_FLAG(13) |
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325 | #define SMSC9218I_PMT_CTRL_PHY_RST SMSC9218I_FLAG(10) |
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326 | #define SMSC9218I_PMT_CTRL_WOL_EN SMSC9218I_FLAG(9) |
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327 | #define SMSC9218I_PMT_CTRL_ED_EN SMSC9218I_FLAG(8) |
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328 | #define SMSC9218I_PMT_CTRL_PME_TYPE_PUPU SMSC9218I_FLAG(6) |
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329 | #define SMSC9218I_PMT_CTRL_WUPS_NO 0 |
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330 | #define SMSC9218I_PMT_CTRL_WUPS_ENERGY SMSC9218I_FLAG(4) |
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331 | #define SMSC9218I_PMT_CTRL_WUPS_MAGIC SMSC9218I_FLAG(5) |
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332 | #define SMSC9218I_PMT_CTRL_PME_IND SMSC9218I_FLAG(3) |
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333 | #define SMSC9218I_PMT_CTRL_PME_POL SMSC9218I_FLAG(2) |
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334 | #define SMSC9218I_PMT_CTRL_PME_EN SMSC9218I_FLAG(1) |
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335 | #define SMSC9218I_PMT_CTRL_READY SMSC9218I_FLAG(0) |
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336 | |
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337 | /** @} */ |
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338 | |
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339 | /** |
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340 | * @name General Purpose IO Configuration |
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341 | * @{ |
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342 | */ |
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343 | |
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344 | #define SMSC9218I_GPIO_CFG_LED3 SMSC9218I_FLAG(30) |
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345 | #define SMSC9218I_GPIO_CFG_LED2 SMSC9218I_FLAG(29) |
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346 | #define SMSC9218I_GPIO_CFG_LED1 SMSC9218I_FLAG(28) |
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347 | #define SMSC9218I_GPIO_CFG_GPIO2_INT_POL SMSC9218I_FLAG(26) |
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348 | #define SMSC9218I_GPIO_CFG_GPIO1_INT_POL SMSC9218I_FLAG(25) |
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349 | #define SMSC9218I_GPIO_CFG_GPIO0_INT_POL SMSC9218I_FLAG(24) |
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350 | #define SMSC9218I_GPIO_CFG_GPIOBUF2 SMSC9218I_FLAG(18) |
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351 | #define SMSC9218I_GPIO_CFG_GPIOBUF1 SMSC9218I_FLAG(17) |
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352 | #define SMSC9218I_GPIO_CFG_GPIOBUF0 SMSC9218I_FLAG(16) |
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353 | #define SMSC9218I_GPIO_CFG_GPIODIR2 SMSC9218I_FLAG(10) |
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354 | #define SMSC9218I_GPIO_CFG_GPIODIR1 SMSC9218I_FLAG(9) |
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355 | #define SMSC9218I_GPIO_CFG_GPIODIR0 SMSC9218I_FLAG(8) |
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356 | #define SMSC9218I_GPIO_CFG_GPO4 SMSC9218I_FLAG(4) |
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357 | #define SMSC9218I_GPIO_CFG_GPO3 SMSC9218I_FLAG(3) |
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358 | #define SMSC9218I_GPIO_CFG_GPIO0 SMSC9218I_FLAG(0) |
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359 | #define SMSC9218I_GPIO_CFG_GPIO2 SMSC9218I_FLAG(2) |
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360 | #define SMSC9218I_GPIO_CFG_GPIO1 SMSC9218I_FLAG(1) |
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361 | |
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362 | /** @} */ |
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363 | |
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364 | /** |
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365 | * @name General Purpose Timer Configuration |
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366 | * @{ |
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367 | */ |
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368 | |
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369 | #define SMSC9218I_GPT_CFG_TIMER_EN SMSC9218I_FLAG(29) |
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370 | #define SMSC9218I_GPT_CFG_LOAD(val) SMSC9218I_FIELD_16(val, 0) |
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371 | #define SMSC9218I_GPT_CFG_GET_LOAD(reg) SMSC9218I_GET_FIELD_16(reg, 0) |
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372 | |
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373 | /** @} */ |
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374 | |
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375 | /** |
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376 | * @name General Purpose Timer Count |
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377 | * @{ |
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378 | */ |
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379 | |
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380 | #define SMSC9218I_GPT_CNT_GET_CNT SMSC9218I_GET_FIELD_16(reg, 0) |
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381 | |
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382 | /** @} */ |
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383 | |
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384 | /** |
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385 | * @name Word Swap |
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386 | * @{ |
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387 | */ |
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388 | |
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389 | #define SMSC9218I_ENDIAN_BIG 0xffffffffU |
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390 | |
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391 | /** @} */ |
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392 | |
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393 | /** |
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394 | * @name Free Run Counter |
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395 | * @{ |
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396 | */ |
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397 | |
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398 | #define SMSC9218I_FREE_RUN_GET(reg) SMSC9218I_SWAP(reg) |
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399 | |
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400 | /** @} */ |
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401 | |
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402 | /** |
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403 | * @name Receiver Dropped Frames Counter |
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404 | * @{ |
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405 | */ |
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406 | |
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407 | #define SMSC9218I_RX_DROP_GET(reg) SMSC9218I_SWAP(reg) |
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408 | |
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409 | /** @} */ |
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410 | |
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411 | /** |
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412 | * @name EEPROM Command Register |
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413 | * @{ |
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414 | */ |
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415 | |
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416 | #define SMSC9218I_E2P_CMD_EPC_BUSY SMSC9218I_FLAG(31) |
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417 | |
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418 | /** @} */ |
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419 | |
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420 | /** |
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421 | * @name MAC Control and Status Synchronizer Command |
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422 | * @{ |
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423 | */ |
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424 | |
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425 | #define SMSC9218I_MAC_CSR_CMD_BUSY SMSC9218I_FLAG(31) |
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426 | #define SMSC9218I_MAC_CSR_CMD_READ SMSC9218I_FLAG(30) |
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427 | #define SMSC9218I_MAC_CSR_CMD_ADDR(val) SMSC9218I_FIELD_8(val, 0) |
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428 | #define SMSC9218I_MAC_CSR_CMD_GET_ADDR(reg) SMSC9218I_GET_FIELD_8(reg, 0) |
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429 | |
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430 | /** @} */ |
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431 | |
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432 | /** |
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433 | * @name MAC Control Register |
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434 | * @{ |
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435 | */ |
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436 | |
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437 | #define SMSC9218I_MAC_CR 0x00000001U |
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438 | #define SMSC9218I_MAC_CR_RXALL 0x80000000U |
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439 | #define SMSC9218I_MAC_CR_HBDIS 0x10000000U |
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440 | #define SMSC9218I_MAC_CR_RCVOWN 0x00800000U |
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441 | #define SMSC9218I_MAC_CR_LOOPBK 0x00200000U |
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442 | #define SMSC9218I_MAC_CR_FDPX 0x00100000U |
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443 | #define SMSC9218I_MAC_CR_MCPAS 0x00080000U |
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444 | #define SMSC9218I_MAC_CR_PRMS 0x00040000U |
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445 | #define SMSC9218I_MAC_CR_INVFILT 0x00020000U |
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446 | #define SMSC9218I_MAC_CR_PASSBAD 0x00010000U |
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447 | #define SMSC9218I_MAC_CR_HFILT 0x00008000U |
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448 | #define SMSC9218I_MAC_CR_HPFILT 0x00002000U |
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449 | #define SMSC9218I_MAC_CR_LCOLL 0x00001000U |
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450 | #define SMSC9218I_MAC_CR_BCAST 0x00000800U |
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451 | #define SMSC9218I_MAC_CR_DISRTY 0x00000400U |
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452 | #define SMSC9218I_MAC_CR_PADSTR 0x00000100U |
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453 | #define SMSC9218I_MAC_CR_BOLMT_MASK 0x000000c0U |
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454 | #define SMSC9218I_MAC_CR_BOLMT_10 0x00000000U |
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455 | #define SMSC9218I_MAC_CR_BOLMT_8 0x00000040U |
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456 | #define SMSC9218I_MAC_CR_BOLMT_4 0x00000080U |
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457 | #define SMSC9218I_MAC_CR_BOLMT_1 0x000000c0U |
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458 | #define SMSC9218I_MAC_CR_DFCHK 0x00000020U |
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459 | #define SMSC9218I_MAC_CR_TXEN 0x00000008U |
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460 | #define SMSC9218I_MAC_CR_RXEN 0x00000004U |
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461 | |
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462 | /** @} */ |
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463 | |
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464 | /** |
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465 | * @name MAC Address High |
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466 | * @{ |
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467 | */ |
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468 | |
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469 | #define SMSC9218I_MAC_ADDRH 0x00000002U |
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470 | #define SMSC9218I_MAC_ADDRH_MASK 0x0000ffffU |
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471 | |
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472 | /** @} */ |
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473 | |
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474 | /** |
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475 | * @name MAC Address Low |
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476 | * @{ |
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477 | */ |
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478 | |
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479 | #define SMSC9218I_MAC_ADDRL 0x00000003U |
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480 | #define SMSC9218I_MAC_ADDRL_MASK 0xffffffffU |
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481 | |
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482 | /** @} */ |
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483 | |
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484 | /** |
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485 | * @name Multicast Hash Table High |
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486 | * @{ |
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487 | */ |
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488 | |
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489 | #define SMSC9218I_MAC_HASHH 0x00000004U |
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490 | #define SMSC9218I_MAC_HASHH_MASK 0xffffffffU |
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491 | |
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492 | /** @} */ |
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493 | |
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494 | /** |
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495 | * @name Multicast Hash Table Low |
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496 | * @{ |
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497 | */ |
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498 | |
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499 | #define SMSC9218I_MAC_HASHL 0x00000005U |
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500 | #define SMSC9218I_MAC_HASHL_MASK 0xffffffffU |
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501 | |
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502 | /** @} */ |
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503 | |
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504 | /** |
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505 | * @name MII Access |
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506 | * @{ |
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507 | */ |
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508 | |
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509 | #define SMSC9218I_MAC_MII_ACC 0x00000006U |
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510 | #define SMSC9218I_MAC_MII_ACC_PHY_DEFAULT (1U << 11) |
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511 | #define SMSC9218I_MAC_MII_ACC_WRITE (1U << 1) |
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512 | #define SMSC9218I_MAC_MII_ACC_BUSY (1U << 0) |
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513 | #define SMSC9218I_MAC_MII_ACC_ADDR(addr) ((addr) << 6) |
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514 | |
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515 | /** @} */ |
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516 | |
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517 | /** |
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518 | * @name MII Data |
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519 | * @{ |
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520 | */ |
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521 | |
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522 | #define SMSC9218I_MAC_MII_DATA 0x00000007U |
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523 | |
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524 | /** @} */ |
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525 | |
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526 | /** |
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527 | * @name Flow Control |
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528 | * @{ |
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529 | */ |
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530 | |
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531 | #define SMSC9218I_MAC_FLOW 0x00000008U |
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532 | #define SMSC9218I_MAC_FLOW_FCPT_MASK 0xffff0000U |
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533 | #define SMSC9218I_MAC_FLOW_FCPASS 0x00000004U |
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534 | #define SMSC9218I_MAC_FLOW_FCEN 0x00000002U |
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535 | #define SMSC9218I_MAC_FLOW_FCBSY 0x00000001U |
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536 | |
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537 | /** @} */ |
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538 | |
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539 | /** |
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540 | * @name VLAN1 Tag |
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541 | * @{ |
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542 | */ |
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543 | |
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544 | #define SMSC9218I_MAC_VLAN1 0x00000009U |
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545 | |
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546 | /** @} */ |
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547 | |
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548 | /** |
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549 | * @name VLAN2 Tag |
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550 | * @{ |
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551 | */ |
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552 | |
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553 | #define SMSC9218I_MAC_VLAN2 0x0000000aU |
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554 | |
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555 | /** @} */ |
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556 | |
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557 | /** |
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558 | * @name Wake-up Frame Filter |
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559 | * @{ |
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560 | */ |
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561 | |
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562 | #define SMSC9218I_MAC_WUFF 0x0000000bU |
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563 | |
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564 | /** @} */ |
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565 | |
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566 | /** |
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567 | * @name Wake-up Control and Status |
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568 | * @{ |
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569 | */ |
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570 | |
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571 | #define SMSC9218I_MAC_WUCSR 0x0000000cU |
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572 | #define SMSC9218I_MAC_WUCSR_GUE 0x00000200U |
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573 | #define SMSC9218I_MAC_WUCSR_WUFR 0x00000040U |
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574 | #define SMSC9218I_MAC_WUCSR_MPR 0x00000020U |
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575 | #define SMSC9218I_MAC_WUCSR_WUEN 0x00000004U |
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576 | #define SMSC9218I_MAC_WUCSR_MPEN 0x00000002U |
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577 | |
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578 | /** @} */ |
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579 | |
---|
580 | /** |
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581 | * @name PHY Identifier 1 |
---|
582 | * @{ |
---|
583 | */ |
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584 | |
---|
585 | #define SMSC9218I_PHY_ID1_LAN9118 0x7 |
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586 | |
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587 | /** @} */ |
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588 | |
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589 | /** |
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590 | * @name PHY Identifier 2 |
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591 | * @{ |
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592 | */ |
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593 | |
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594 | #define SMSC9218I_PHY_ID2_LAN9218 0xc0c3 |
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595 | |
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596 | /** @} */ |
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597 | |
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598 | /** |
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599 | * @name Mode Control and Status |
---|
600 | * @{ |
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601 | */ |
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602 | |
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603 | #define SMSC9218I_PHY_MCSR 0x00000011U |
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604 | #define SMSC9218I_PHY_MCSR_EDPWRDOWN 0x00002000U |
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605 | #define SMSC9218I_PHY_MCSR_ENERGYON 0x00000002U |
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606 | |
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607 | /** @} */ |
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608 | |
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609 | /** |
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610 | * @name Special Modes |
---|
611 | * @{ |
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612 | */ |
---|
613 | |
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614 | #define SMSC9218I_PHY_SPMODES 0x00000012U |
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615 | |
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616 | /** @} */ |
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617 | |
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618 | /** |
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619 | * @name Special Control and Status Indications |
---|
620 | * @{ |
---|
621 | */ |
---|
622 | |
---|
623 | #define SMSC9218I_PHY_CSIR 0x0000001bU |
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624 | #define SMSC9218I_PHY_CSIR_SQEOFF 0x00000800U |
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625 | #define SMSC9218I_PHY_CSIR_FEFIEN 0x00000020U |
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626 | #define SMSC9218I_PHY_CSIR_XPOL 0x00000010U |
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627 | |
---|
628 | /** @} */ |
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629 | |
---|
630 | /** |
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631 | * @name Interrupt Source Flag |
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632 | * @{ |
---|
633 | */ |
---|
634 | |
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635 | #define SMSC9218I_PHY_ISR 0x0000001dU |
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636 | #define SMSC9218I_PHY_ISR_INT7 0x00000080U |
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637 | #define SMSC9218I_PHY_ISR_INT6 0x00000040U |
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638 | #define SMSC9218I_PHY_ISR_INT5 0x00000020U |
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639 | #define SMSC9218I_PHY_ISR_INT4 0x00000010U |
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640 | #define SMSC9218I_PHY_ISR_INT3 0x00000008U |
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641 | #define SMSC9218I_PHY_ISR_INT2 0x00000004U |
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642 | #define SMSC9218I_PHY_ISR_INT1 0x00000002U |
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643 | |
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644 | /** @} */ |
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645 | |
---|
646 | /** |
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647 | * @name Interrupt Mask |
---|
648 | * @{ |
---|
649 | */ |
---|
650 | |
---|
651 | #define SMSC9218I_PHY_IMR 0x0000001eU |
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652 | #define SMSC9218I_PHY_IMR_INT7 0x00000080U |
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653 | #define SMSC9218I_PHY_IMR_INT6 0x00000040U |
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654 | #define SMSC9218I_PHY_IMR_INT5 0x00000020U |
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655 | #define SMSC9218I_PHY_IMR_INT4 0x00000010U |
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656 | #define SMSC9218I_PHY_IMR_INT3 0x00000008U |
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657 | #define SMSC9218I_PHY_IMR_INT2 0x00000004U |
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658 | #define SMSC9218I_PHY_IMR_INT1 0x00000002U |
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659 | |
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660 | /** @} */ |
---|
661 | |
---|
662 | /** |
---|
663 | * @name PHY Special Control and Status |
---|
664 | * @{ |
---|
665 | */ |
---|
666 | |
---|
667 | #define SMSC9218I_PHY_PHYSCSR 0x0000001fU |
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668 | #define SMSC9218I_PHY_PHYSCSR_ANDONE 0x00001000U |
---|
669 | #define SMSC9218I_PHY_PHYSCSR_4B5B_EN 0x00000040U |
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670 | #define SMSC9218I_PHY_PHYSCSR_SPEED_MASK 0x0000001cU |
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671 | #define SMSC9218I_PHY_PHYSCSR_SPEED_10HD 0x00000004U |
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672 | #define SMSC9218I_PHY_PHYSCSR_SPEED_10FD 0x00000014U |
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673 | #define SMSC9218I_PHY_PHYSCSR_SPEED_100HD 0x00000008U |
---|
674 | #define SMSC9218I_PHY_PHYSCSR_SPEED_100FD 0x00000018U |
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675 | |
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676 | /** @} */ |
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