[d374492] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup mpc55xx |
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| 5 | * |
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| 6 | * @brief SMSC - LAN9218i |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Copyright (c) 2009 |
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| 11 | * embedded brains GmbH |
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| 12 | * Obere Lagerstr. 30 |
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| 13 | * D-82178 Puchheim |
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| 14 | * Germany |
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| 15 | * rtems@embedded-brains.de |
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| 16 | * |
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| 17 | * The license and distribution terms for this file may be |
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| 18 | * found in the file LICENSE in this distribution or at |
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| 19 | * http://www.rtems.com/license/LICENSE. |
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| 20 | */ |
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| 21 | |
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| 22 | /** |
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| 23 | * @name Memory Map |
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[ac7af4a] | 24 | * @{ |
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[d374492] | 25 | */ |
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| 26 | |
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| 27 | typedef struct { |
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| 28 | uint32_t rx_fifo_data; |
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| 29 | uint32_t rx_fifo_data_aliases [7]; |
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| 30 | uint32_t tx_fifo_data; |
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| 31 | uint32_t tx_fifo_data_aliases [7]; |
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| 32 | uint32_t rx_fifo_status; |
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| 33 | uint32_t rx_fifo_status_peek; |
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| 34 | uint32_t tx_fifo_status; |
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| 35 | uint32_t tx_fifo_status_peek; |
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| 36 | uint32_t id_rev; |
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| 37 | uint32_t irq_cfg; |
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| 38 | uint32_t int_sts; |
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| 39 | uint32_t int_en; |
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| 40 | uint32_t reserved_0; |
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| 41 | uint32_t byte_test; |
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| 42 | uint32_t fifo_int; |
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| 43 | uint32_t rx_cfg; |
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| 44 | uint32_t tx_cfg; |
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| 45 | uint32_t hw_cfg; |
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| 46 | uint32_t rx_dp_ctl; |
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| 47 | uint32_t rx_fifo_inf; |
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| 48 | uint32_t tx_fifo_inf; |
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| 49 | uint32_t pmt_ctrl; |
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| 50 | uint32_t gpio_cfg; |
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| 51 | uint32_t gpt_cfg; |
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| 52 | uint32_t gpt_cnt; |
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| 53 | uint32_t reserved_1; |
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| 54 | uint32_t word_swap; |
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| 55 | uint32_t free_run; |
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| 56 | uint32_t rx_drop; |
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| 57 | uint32_t mac_csr_cmd; |
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| 58 | uint32_t mac_csr_data; |
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| 59 | uint32_t afc_cfg; |
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| 60 | uint32_t e2p_cmd; |
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| 61 | uint32_t e2p_data; |
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| 62 | } smsc9218i_registers; |
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| 63 | |
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| 64 | volatile smsc9218i_registers *const smsc9218i = (volatile smsc9218i_registers *) 0x3fff8000; |
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| 65 | |
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| 66 | /** @} */ |
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| 67 | |
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| 68 | #define SMSC9218I_BIT_POS(pos) \ |
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| 69 | ((pos) > 15 ? \ |
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| 70 | ((pos) > 23 ? (pos) - 24 : (pos) - 8) \ |
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| 71 | : ((pos) > 7 ? (pos) + 8 : (pos) + 24)) |
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| 72 | |
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| 73 | #define SMSC9218I_FLAG(pos) \ |
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| 74 | (1U << SMSC9218I_BIT_POS(pos)) |
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| 75 | |
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| 76 | #define SMSC9218I_FIELD_8(val, pos) \ |
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| 77 | (((val) & 0xff) << SMSC9218I_BIT_POS(pos)) |
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| 78 | |
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| 79 | #define SMSC9218I_GET_FIELD_8(reg, pos) \ |
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| 80 | (((reg) >> SMSC9218I_BIT_POS(pos)) & 0xff) |
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| 81 | |
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| 82 | #define SMSC9218I_FIELD_16(val, pos) \ |
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| 83 | (SMSC9218I_FIELD_8((val) >> 8, (pos) + 8) \ |
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| 84 | | SMSC9218I_FIELD_8((val), pos)) |
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| 85 | |
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| 86 | #define SMSC9218I_GET_FIELD_16(reg, pos) \ |
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| 87 | ((SMSC9218I_GET_FIELD_8(reg, (pos) + 8) << 8) \ |
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| 88 | | SMSC9218I_GET_FIELD_8(reg, pos)) |
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| 89 | |
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| 90 | #define SMSC9218I_SWAP(val) \ |
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| 91 | ((((val) >> 24) & 0xff) \ |
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| 92 | | ((((val) >> 16) & 0xff) << 8) \ |
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| 93 | | ((((val) >> 8) & 0xff) << 16) \ |
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| 94 | | (((val) & 0xff) << 24)) |
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| 95 | |
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| 96 | /** |
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| 97 | * @name Receive Status |
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[ac7af4a] | 98 | * @{ |
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[d374492] | 99 | */ |
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| 100 | |
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| 101 | #define SMSC9218I_RX_STS_FILTER_FAIL SMSC9218I_FLAG(30) |
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| 102 | #define SMSC9218I_RX_STS_GET_LENGTH(reg) (SMSC9218I_GET_FIELD_16(reg, 16) & 0x3fff) |
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| 103 | #define SMSC9218I_RX_STS_ERROR SMSC9218I_FLAG(15) |
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| 104 | #define SMSC9218I_RX_STS_BROADCAST SMSC9218I_FLAG(13) |
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| 105 | #define SMSC9218I_RX_STS_ERROR_LENGTH SMSC9218I_FLAG(12) |
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| 106 | #define SMSC9218I_RX_STS_ERROR_RUNT_FRAME SMSC9218I_FLAG(11) |
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| 107 | #define SMSC9218I_RX_STS_MULTICAST SMSC9218I_FLAG(10) |
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| 108 | #define SMSC9218I_RX_STS_ERROR_TOO_LONG SMSC9218I_FLAG(7) |
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| 109 | #define SMSC9218I_RX_STS_ERROR_COLLISION SMSC9218I_FLAG(6) |
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| 110 | #define SMSC9218I_RX_STS_TYPE SMSC9218I_FLAG(5) |
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| 111 | #define SMSC9218I_RX_STS_WATCHDOG SMSC9218I_FLAG(4) |
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| 112 | #define SMSC9218I_RX_STS_ERROR_MII SMSC9218I_FLAG(3) |
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| 113 | #define SMSC9218I_RX_STS_DRIBBLING_BIT SMSC9218I_FLAG(2) |
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| 114 | #define SMSC9218I_RX_STS_ERROR_CRC SMSC9218I_FLAG(1) |
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| 115 | |
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| 116 | /** @} */ |
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| 117 | |
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| 118 | /** |
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| 119 | * @name Transmit Status |
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[ac7af4a] | 120 | * @{ |
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[d374492] | 121 | */ |
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| 122 | |
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| 123 | #define SMSC9218I_TX_STS_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16) |
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| 124 | #define SMSC9218I_TX_STS_ERROR SMSC9218I_FLAG(15) |
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| 125 | #define SMSC9218I_TX_STS_ERROR_LOSS_OF_CARRIER SMSC9218I_FLAG(11) |
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| 126 | #define SMSC9218I_TX_STS_ERROR_NO_CARRIER SMSC9218I_FLAG(10) |
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| 127 | #define SMSC9218I_TX_STS_ERROR_LATE_COLLISION SMSC9218I_FLAG(9) |
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| 128 | #define SMSC9218I_TX_STS_ERROR_EXCESSIVE_COLLISIONS SMSC9218I_FLAG(8) |
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| 129 | #define SMSC9218I_TX_STS_ERROR_EXCESSIVE_DEFERRAL SMSC9218I_FLAG(2) |
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| 130 | #define SMSC9218I_TX_STS_ERROR_DEFERRED SMSC9218I_FLAG(0) |
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| 131 | |
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| 132 | /** @} */ |
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| 133 | |
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| 134 | /** |
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| 135 | * @name Transmit Command A |
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[ac7af4a] | 136 | * @{ |
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[d374492] | 137 | */ |
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| 138 | |
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| 139 | #define SMSC9218I_TX_A_IOC SMSC9218I_FLAG(31) |
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| 140 | #define SMSC9218I_TX_A_END_ALIGN_4 0 |
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| 141 | #define SMSC9218I_TX_A_END_ALIGN_16 SMSC9218I_FLAG(24) |
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| 142 | #define SMSC9218I_TX_A_END_ALIGN_32 SMSC9218I_FLAG(25) |
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| 143 | #define SMSC9218I_TX_A_DOFF(val) SMSC9218I_FIELD_8(val, 16) |
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| 144 | #define SMSC9218I_TX_A_FIRST SMSC9218I_FLAG(13) |
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| 145 | #define SMSC9218I_TX_A_LAST SMSC9218I_FLAG(12) |
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| 146 | #define SMSC9218I_TX_A_FRAGMENT_LENGTH(val) SMSC9218I_FIELD_16(val, 0) |
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| 147 | |
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| 148 | /** @} */ |
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| 149 | |
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| 150 | /** |
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| 151 | * @name Transmit Command B |
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[ac7af4a] | 152 | * @{ |
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[d374492] | 153 | */ |
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| 154 | |
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| 155 | #define SMSC9218I_TX_B_TAG(val) SMSC9218I_FIELD_16(val, 16) |
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| 156 | #define SMSC9218I_TX_B_GET_TAG(reg) SMSC9218I_GET_FIELD_16(reg, 16) |
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| 157 | #define SMSC9218I_TX_B_DISABLE_CRC SMSC9218I_FLAG(13) |
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| 158 | #define SMSC9218I_TX_B_DISABLE_PAD SMSC9218I_FLAG(12) |
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| 159 | #define SMSC9218I_TX_B_FRAME_LENGTH(val) SMSC9218I_FIELD_16(val, 0) |
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| 160 | |
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| 161 | /** @} */ |
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| 162 | |
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| 163 | /** |
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| 164 | * @name Chip ID and Revision |
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[ac7af4a] | 165 | * @{ |
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[d374492] | 166 | */ |
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| 167 | |
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| 168 | #define SMSC9218I_ID_REV_GET_ID(reg) SMSC9218I_GET_FIELD_16(reg, 16) |
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| 169 | #define SMSC9218I_ID_REV_GET_REV(reg) SMSC9218I_GET_FIELD_16(reg, 0) |
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| 170 | #define SMSC9218I_ID_REV_ID_CHIP_118 0x0118U |
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| 171 | #define SMSC9218I_ID_REV_ID_CHIP_218 0x118aU |
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| 172 | |
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| 173 | /** @} */ |
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| 174 | |
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| 175 | /** |
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| 176 | * @name Interrupt Configuration |
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[ac7af4a] | 177 | * @{ |
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[d374492] | 178 | */ |
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| 179 | |
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| 180 | #define SMSC9218I_IRQ_CFG_INT_DEAS(val) SMSC9218I_FIELD_8(val, 24) |
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| 181 | #define SMSC9218I_IRQ_CFG_GET_INT_DEAS(reg) SMSC9218I_GET_FIELD_8(reg, 24) |
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| 182 | #define SMSC9218I_IRQ_CFG_INT_DEAS_CLR SMSC9218I_FLAG(14) |
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| 183 | #define SMSC9218I_IRQ_CFG_INT_DEAS_STS SMSC9218I_FLAG(13) |
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| 184 | #define SMSC9218I_IRQ_CFG_IRQ_INT SMSC9218I_FLAG(12) |
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| 185 | #define SMSC9218I_IRQ_CFG_IRQ_EN SMSC9218I_FLAG(8) |
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| 186 | #define SMSC9218I_IRQ_CFG_IRQ_POL SMSC9218I_FLAG(4) |
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| 187 | #define SMSC9218I_IRQ_CFG_IRQ_TYPE SMSC9218I_FLAG(0) |
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| 188 | |
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| 189 | /** @} */ |
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| 190 | |
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| 191 | /** |
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| 192 | * @name Interrupt Status |
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[ac7af4a] | 193 | * @{ |
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[d374492] | 194 | */ |
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| 195 | |
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| 196 | #define SMSC9218I_INT_STS_SW SMSC9218I_FLAG(31) |
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| 197 | #define SMSC9218I_INT_STS_TXSTOP SMSC9218I_FLAG(25) |
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| 198 | #define SMSC9218I_INT_STS_RXSTOP SMSC9218I_FLAG(24) |
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| 199 | #define SMSC9218I_INT_STS_RXDFH SMSC9218I_FLAG(23) |
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| 200 | #define SMSC9218I_INT_STS_TIOC SMSC9218I_FLAG(21) |
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| 201 | #define SMSC9218I_INT_STS_RXD SMSC9218I_FLAG(20) |
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| 202 | #define SMSC9218I_INT_STS_GPT SMSC9218I_FLAG(19) |
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| 203 | #define SMSC9218I_INT_STS_PHY SMSC9218I_FLAG(18) |
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| 204 | #define SMSC9218I_INT_STS_PME SMSC9218I_FLAG(17) |
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| 205 | #define SMSC9218I_INT_STS_TXSO SMSC9218I_FLAG(16) |
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| 206 | #define SMSC9218I_INT_STS_RWT SMSC9218I_FLAG(15) |
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| 207 | #define SMSC9218I_INT_STS_RXE SMSC9218I_FLAG(14) |
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| 208 | #define SMSC9218I_INT_STS_TXE SMSC9218I_FLAG(13) |
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| 209 | #define SMSC9218I_INT_STS_TDFO SMSC9218I_FLAG(10) |
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| 210 | #define SMSC9218I_INT_STS_TDFA SMSC9218I_FLAG(9) |
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| 211 | #define SMSC9218I_INT_STS_TSFF SMSC9218I_FLAG(8) |
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| 212 | #define SMSC9218I_INT_STS_TSFL SMSC9218I_FLAG(7) |
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| 213 | #define SMSC9218I_INT_STS_RSFF SMSC9218I_FLAG(4) |
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| 214 | #define SMSC9218I_INT_STS_RSFL SMSC9218I_FLAG(3) |
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| 215 | #define SMSC9218I_INT_STS_GPIO2 SMSC9218I_FLAG(2) |
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| 216 | #define SMSC9218I_INT_STS_GPIO1 SMSC9218I_FLAG(1) |
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| 217 | #define SMSC9218I_INT_STS_GPIO0 SMSC9218I_FLAG(0) |
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| 218 | |
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| 219 | /** @} */ |
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| 220 | |
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| 221 | /** |
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| 222 | * @name Interrupt Enable |
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[ac7af4a] | 223 | * @{ |
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[d374492] | 224 | */ |
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| 225 | |
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| 226 | #define SMSC9218I_INT_EN_SW SMSC9218I_FLAG(31) |
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| 227 | #define SMSC9218I_INT_EN_TXSTOP SMSC9218I_FLAG(25) |
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| 228 | #define SMSC9218I_INT_EN_RXSTOP SMSC9218I_FLAG(24) |
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| 229 | #define SMSC9218I_INT_EN_RXDFH SMSC9218I_FLAG(23) |
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| 230 | #define SMSC9218I_INT_EN_TIOC SMSC9218I_FLAG(21) |
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| 231 | #define SMSC9218I_INT_EN_RXD SMSC9218I_FLAG(20) |
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| 232 | #define SMSC9218I_INT_EN_GPT SMSC9218I_FLAG(19) |
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| 233 | #define SMSC9218I_INT_EN_PHY SMSC9218I_FLAG(18) |
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| 234 | #define SMSC9218I_INT_EN_PME SMSC9218I_FLAG(17) |
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| 235 | #define SMSC9218I_INT_EN_TXSO SMSC9218I_FLAG(16) |
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| 236 | #define SMSC9218I_INT_EN_RWT SMSC9218I_FLAG(15) |
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| 237 | #define SMSC9218I_INT_EN_RXE SMSC9218I_FLAG(14) |
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| 238 | #define SMSC9218I_INT_EN_TXE SMSC9218I_FLAG(13) |
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| 239 | #define SMSC9218I_INT_EN_TDFO SMSC9218I_FLAG(10) |
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| 240 | #define SMSC9218I_INT_EN_TDFA SMSC9218I_FLAG(9) |
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| 241 | #define SMSC9218I_INT_EN_TSFF SMSC9218I_FLAG(8) |
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| 242 | #define SMSC9218I_INT_EN_TSFL SMSC9218I_FLAG(7) |
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| 243 | #define SMSC9218I_INT_EN_RSFF SMSC9218I_FLAG(4) |
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| 244 | #define SMSC9218I_INT_EN_RSFL SMSC9218I_FLAG(3) |
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| 245 | #define SMSC9218I_INT_EN_GPIO2 SMSC9218I_FLAG(2) |
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| 246 | #define SMSC9218I_INT_EN_GPIO1 SMSC9218I_FLAG(1) |
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| 247 | #define SMSC9218I_INT_EN_GPIO0 SMSC9218I_FLAG(0) |
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| 248 | |
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| 249 | /** @} */ |
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| 250 | |
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| 251 | /** |
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| 252 | * @name Byte Order Testing |
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[ac7af4a] | 253 | * @{ |
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[d374492] | 254 | */ |
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| 255 | |
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| 256 | #define SMSC9218I_BYTE_TEST SMSC9218I_SWAP(0x87654321U) |
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| 257 | |
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| 258 | /** @} */ |
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| 259 | |
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| 260 | /** |
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| 261 | * @name FIFO Level Interrupts |
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[ac7af4a] | 262 | * @{ |
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[d374492] | 263 | */ |
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| 264 | |
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| 265 | #define SMSC9218I_FIFO_INT_TDAL(val) SMSC9218I_FIELD_8(val, 24) |
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| 266 | #define SMSC9218I_FIFO_INT_GET_TDAL(reg) SMSC9218I_GET_FIELD_8(reg, 24) |
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| 267 | #define SMSC9218I_FIFO_INT_TSL(val) SMSC9218I_FIELD_8(val, 16) |
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| 268 | #define SMSC9218I_FIFO_INT_GET_TSL(reg) SMSC9218I_GET_FIELD_8(reg, 16) |
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| 269 | #define SMSC9218I_FIFO_INT_RSL(val) SMSC9218I_FIELD_8(val, 0) |
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| 270 | #define SMSC9218I_FIFO_INT_GET_RSL(reg) SMSC9218I_GET_FIELD_8(reg, 0) |
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| 271 | |
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| 272 | /** @} */ |
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| 273 | |
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| 274 | /** |
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| 275 | * @name Receive Configuration |
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[ac7af4a] | 276 | * @{ |
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[d374492] | 277 | */ |
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| 278 | |
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| 279 | #define SMSC9218I_RX_CFG_END_ALIGN_4 0 |
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| 280 | #define SMSC9218I_RX_CFG_END_ALIGN_16 SMSC9218I_FLAG(30) |
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| 281 | #define SMSC9218I_RX_CFG_END_ALIGN_32 SMSC9218I_FLAG(31) |
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| 282 | #define SMSC9218I_RX_CFG_DMA_CNT(val) SMSC9218I_FIELD_8(val, 24) |
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| 283 | #define SMSC9218I_RX_CFG_GET_DMA_CNT(reg) SMSC9218I_GET_FIELD_8(reg, 24) |
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| 284 | #define SMSC9218I_RX_CFG_DUMP SMSC9218I_FLAG(15) |
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| 285 | #define SMSC9218I_RX_CFG_DOFF(val) SMSC9218I_FIELD_8(val, 8) |
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| 286 | #define SMSC9218I_RX_CFG_GET_DOFF(reg) SMSC9218I_GET_FIELD_8(reg, 8) |
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| 287 | |
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| 288 | /** @} */ |
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| 289 | |
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| 290 | /** |
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| 291 | * @name Transmit Configuration |
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[ac7af4a] | 292 | * @{ |
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[d374492] | 293 | */ |
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| 294 | |
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| 295 | #define SMSC9218I_TX_CFG_SDUMP SMSC9218I_FLAG(15) |
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| 296 | #define SMSC9218I_TX_CFG_DDUMP SMSC9218I_FLAG(14) |
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| 297 | #define SMSC9218I_TX_CFG_SAO SMSC9218I_FLAG(2) |
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| 298 | #define SMSC9218I_TX_CFG_ON SMSC9218I_FLAG(1) |
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| 299 | #define SMSC9218I_TX_CFG_STOP SMSC9218I_FLAG(0) |
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| 300 | |
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| 301 | /** @} */ |
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| 302 | |
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| 303 | /** |
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| 304 | * @name Hardware Configuration |
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[ac7af4a] | 305 | * @{ |
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[d374492] | 306 | */ |
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| 307 | |
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| 308 | #define SMSC9218I_HW_CFG_AMDIX SMSC9218I_FLAG(24) |
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| 309 | #define SMSC9218I_HW_CFG_MBO SMSC9218I_FLAG(20) |
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| 310 | #define SMSC9218I_HW_CFG_TX_FIF_SZ(val) SMSC9218I_FIELD_8(val, 16) |
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| 311 | #define SMSC9218I_HW_CFG_GET_TX_FIF_SZ(reg) SMSC9218I_GET_FIELD_8(reg, 16) |
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| 312 | #define SMSC9218I_HW_CFG_BITMD_32 SMSC9218I_FLAG(2) |
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| 313 | #define SMSC9218I_HW_CFG_SRST_TO SMSC9218I_FLAG(1) |
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| 314 | #define SMSC9218I_HW_CFG_SRST SMSC9218I_FLAG(0) |
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| 315 | |
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| 316 | /** @} */ |
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| 317 | |
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| 318 | /** |
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| 319 | * @name Receive Datapath Control |
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[ac7af4a] | 320 | * @{ |
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[d374492] | 321 | */ |
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| 322 | |
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| 323 | #define SMSC9218I_RX_DP_CTRL_FFWD SMSC9218I_FLAG(31) |
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| 324 | |
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| 325 | /** @} */ |
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| 326 | |
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| 327 | /** |
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| 328 | * @name Receive FIFO Information |
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[ac7af4a] | 329 | * @{ |
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[d374492] | 330 | */ |
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| 331 | |
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| 332 | #define SMSC9218I_RX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16) |
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| 333 | #define SMSC9218I_RX_FIFO_INF_GET_DUSED(reg) SMSC9218I_GET_FIELD_16(reg, 0) |
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| 334 | |
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| 335 | /** @} */ |
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| 336 | |
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| 337 | /** |
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| 338 | * @name Transmit FIFO Information |
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[ac7af4a] | 339 | * @{ |
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[d374492] | 340 | */ |
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| 341 | |
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| 342 | #define SMSC9218I_TX_FIFO_INF_GET_SUSED(reg) SMSC9218I_GET_FIELD_8(reg, 16) |
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| 343 | #define SMSC9218I_TX_FIFO_INF_GET_FREE(reg) SMSC9218I_GET_FIELD_16(reg, 0) |
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| 344 | |
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| 345 | /** @} */ |
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| 346 | |
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| 347 | /** |
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| 348 | * @name Power Management Control |
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[ac7af4a] | 349 | * @{ |
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[d374492] | 350 | */ |
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| 351 | |
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| 352 | #define SMSC9218I_PMT_CTRL_PM_MODE_D0 0 |
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| 353 | #define SMSC9218I_PMT_CTRL_PM_MODE_D1 SMSC9218I_FLAG(12) |
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| 354 | #define SMSC9218I_PMT_CTRL_PM_MODE_D2 SMSC9218I_FLAG(13) |
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| 355 | #define SMSC9218I_PMT_CTRL_PHY_RST SMSC9218I_FLAG(10) |
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| 356 | #define SMSC9218I_PMT_CTRL_WOL_EN SMSC9218I_FLAG(9) |
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| 357 | #define SMSC9218I_PMT_CTRL_ED_EN SMSC9218I_FLAG(8) |
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| 358 | #define SMSC9218I_PMT_CTRL_PME_TYPE_PUPU SMSC9218I_FLAG(6) |
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| 359 | #define SMSC9218I_PMT_CTRL_WUPS_NO 0 |
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| 360 | #define SMSC9218I_PMT_CTRL_WUPS_ENERGY SMSC9218I_FLAG(4) |
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| 361 | #define SMSC9218I_PMT_CTRL_WUPS_MAGIC SMSC9218I_FLAG(5) |
---|
| 362 | #define SMSC9218I_PMT_CTRL_PME_IND SMSC9218I_FLAG(3) |
---|
| 363 | #define SMSC9218I_PMT_CTRL_PME_POL SMSC9218I_FLAG(2) |
---|
| 364 | #define SMSC9218I_PMT_CTRL_PME_EN SMSC9218I_FLAG(1) |
---|
| 365 | #define SMSC9218I_PMT_CTRL_READY SMSC9218I_FLAG(0) |
---|
| 366 | |
---|
| 367 | /** @} */ |
---|
| 368 | |
---|
| 369 | /** |
---|
| 370 | * @name General Purpose IO Configuration |
---|
[ac7af4a] | 371 | * @{ |
---|
[d374492] | 372 | */ |
---|
| 373 | |
---|
| 374 | #define SMSC9218I_GPIO_CFG_LED3 SMSC9218I_FLAG(30) |
---|
| 375 | #define SMSC9218I_GPIO_CFG_LED2 SMSC9218I_FLAG(29) |
---|
| 376 | #define SMSC9218I_GPIO_CFG_LED1 SMSC9218I_FLAG(28) |
---|
| 377 | #define SMSC9218I_GPIO_CFG_GPIO2_INT_POL SMSC9218I_FLAG(26) |
---|
| 378 | #define SMSC9218I_GPIO_CFG_GPIO1_INT_POL SMSC9218I_FLAG(25) |
---|
| 379 | #define SMSC9218I_GPIO_CFG_GPIO0_INT_POL SMSC9218I_FLAG(24) |
---|
| 380 | #define SMSC9218I_GPIO_CFG_GPIOBUF2 SMSC9218I_FLAG(18) |
---|
| 381 | #define SMSC9218I_GPIO_CFG_GPIOBUF1 SMSC9218I_FLAG(17) |
---|
| 382 | #define SMSC9218I_GPIO_CFG_GPIOBUF0 SMSC9218I_FLAG(16) |
---|
| 383 | #define SMSC9218I_GPIO_CFG_GPIODIR2 SMSC9218I_FLAG(10) |
---|
| 384 | #define SMSC9218I_GPIO_CFG_GPIODIR1 SMSC9218I_FLAG(9) |
---|
| 385 | #define SMSC9218I_GPIO_CFG_GPIODIR0 SMSC9218I_FLAG(8) |
---|
| 386 | #define SMSC9218I_GPIO_CFG_GPO4 SMSC9218I_FLAG(4) |
---|
| 387 | #define SMSC9218I_GPIO_CFG_GPO3 SMSC9218I_FLAG(3) |
---|
| 388 | #define SMSC9218I_GPIO_CFG_GPIO0 SMSC9218I_FLAG(0) |
---|
| 389 | #define SMSC9218I_GPIO_CFG_GPIO2 SMSC9218I_FLAG(2) |
---|
| 390 | #define SMSC9218I_GPIO_CFG_GPIO1 SMSC9218I_FLAG(1) |
---|
| 391 | |
---|
| 392 | /** @} */ |
---|
| 393 | |
---|
| 394 | /** |
---|
| 395 | * @name General Purpose Timer Configuration |
---|
[ac7af4a] | 396 | * @{ |
---|
[d374492] | 397 | */ |
---|
| 398 | |
---|
| 399 | #define SMSC9218I_GPT_CFG_TIMER_EN SMSC9218I_FLAG(29) |
---|
| 400 | #define SMSC9218I_GPT_CFG_LOAD(val) SMSC9218I_FIELD_16(val, 0) |
---|
| 401 | #define SMSC9218I_GPT_CFG_GET_LOAD(reg) SMSC9218I_GET_FIELD_16(reg, 0) |
---|
| 402 | |
---|
| 403 | /** @} */ |
---|
| 404 | |
---|
| 405 | /** |
---|
| 406 | * @name General Purpose Timer Count |
---|
[ac7af4a] | 407 | * @{ |
---|
[d374492] | 408 | */ |
---|
| 409 | |
---|
| 410 | #define SMSC9218I_GPT_CNT_GET_CNT SMSC9218I_GET_FIELD_16(reg, 0) |
---|
| 411 | |
---|
| 412 | /** @} */ |
---|
| 413 | |
---|
| 414 | /** |
---|
| 415 | * @name Word Swap |
---|
[ac7af4a] | 416 | * @{ |
---|
[d374492] | 417 | */ |
---|
| 418 | |
---|
| 419 | #define SMSC9218I_ENDIAN_BIG 0xffffffffU |
---|
| 420 | |
---|
| 421 | /** @} */ |
---|
| 422 | |
---|
| 423 | /** |
---|
| 424 | * @name Free Run Counter |
---|
[ac7af4a] | 425 | * @{ |
---|
[d374492] | 426 | */ |
---|
| 427 | |
---|
| 428 | #define SMSC9218I_FREE_RUN_GET(reg) SMSC9218I_SWAP(reg) |
---|
| 429 | |
---|
| 430 | /** @} */ |
---|
| 431 | |
---|
| 432 | /** |
---|
| 433 | * @name Receiver Dropped Frames Counter |
---|
[ac7af4a] | 434 | * @{ |
---|
[d374492] | 435 | */ |
---|
| 436 | |
---|
| 437 | #define SMSC9218I_RX_DROP_GET(reg) SMSC9218I_SWAP(reg) |
---|
| 438 | |
---|
| 439 | /** @} */ |
---|
| 440 | |
---|
| 441 | /** |
---|
| 442 | * @name MAC Control and Status Synchronizer Command |
---|
[ac7af4a] | 443 | * @{ |
---|
[d374492] | 444 | */ |
---|
| 445 | |
---|
| 446 | #define SMSC9218I_MAC_CSR_CMD_BUSY SMSC9218I_FLAG(31) |
---|
| 447 | #define SMSC9218I_MAC_CSR_CMD_READ SMSC9218I_FLAG(30) |
---|
| 448 | #define SMSC9218I_MAC_CSR_CMD_ADDR(val) SMSC9218I_FIELD_8(val, 0) |
---|
| 449 | #define SMSC9218I_MAC_CSR_CMD_GET_ADDR(reg) SMSC9218I_GET_FIELD_8(reg, 0) |
---|
| 450 | |
---|
| 451 | /** @} */ |
---|
| 452 | |
---|
| 453 | /** |
---|
| 454 | * @name MAC Control Register |
---|
[ac7af4a] | 455 | * @{ |
---|
[d374492] | 456 | */ |
---|
| 457 | |
---|
| 458 | #define SMSC9218I_MAC_CR 0x00000001U |
---|
| 459 | #define SMSC9218I_MAC_CR_RXALL 0x80000000U |
---|
| 460 | #define SMSC9218I_MAC_CR_HBDIS 0x10000000U |
---|
| 461 | #define SMSC9218I_MAC_CR_RCVOWN 0x00800000U |
---|
| 462 | #define SMSC9218I_MAC_CR_LOOPBK 0x00200000U |
---|
| 463 | #define SMSC9218I_MAC_CR_FDPX 0x00100000U |
---|
| 464 | #define SMSC9218I_MAC_CR_MCPAS 0x00080000U |
---|
| 465 | #define SMSC9218I_MAC_CR_PRMS 0x00040000U |
---|
| 466 | #define SMSC9218I_MAC_CR_INVFILT 0x00020000U |
---|
| 467 | #define SMSC9218I_MAC_CR_PASSBAD 0x00010000U |
---|
| 468 | #define SMSC9218I_MAC_CR_HFILT 0x00008000U |
---|
| 469 | #define SMSC9218I_MAC_CR_HPFILT 0x00002000U |
---|
| 470 | #define SMSC9218I_MAC_CR_LCOLL 0x00001000U |
---|
| 471 | #define SMSC9218I_MAC_CR_BCAST 0x00000800U |
---|
| 472 | #define SMSC9218I_MAC_CR_DISRTY 0x00000400U |
---|
| 473 | #define SMSC9218I_MAC_CR_PADSTR 0x00000100U |
---|
| 474 | #define SMSC9218I_MAC_CR_BOLMT_MASK 0x000000c0U |
---|
| 475 | #define SMSC9218I_MAC_CR_BOLMT_10 0x00000000U |
---|
| 476 | #define SMSC9218I_MAC_CR_BOLMT_8 0x00000040U |
---|
| 477 | #define SMSC9218I_MAC_CR_BOLMT_4 0x00000080U |
---|
| 478 | #define SMSC9218I_MAC_CR_BOLMT_1 0x000000c0U |
---|
| 479 | #define SMSC9218I_MAC_CR_DFCHK 0x00000020U |
---|
| 480 | #define SMSC9218I_MAC_CR_TXEN 0x00000008U |
---|
| 481 | #define SMSC9218I_MAC_CR_RXEN 0x00000004U |
---|
| 482 | |
---|
| 483 | /** @} */ |
---|
| 484 | |
---|
| 485 | /** |
---|
| 486 | * @name MAC Address High |
---|
[ac7af4a] | 487 | * @{ |
---|
[d374492] | 488 | */ |
---|
| 489 | |
---|
| 490 | #define SMSC9218I_MAC_ADDRH 0x00000002U |
---|
| 491 | #define SMSC9218I_MAC_ADDRH_MASK 0x0000ffffU |
---|
| 492 | |
---|
| 493 | /** @} */ |
---|
| 494 | |
---|
| 495 | /** |
---|
| 496 | * @name MAC Address Low |
---|
[ac7af4a] | 497 | * @{ |
---|
[d374492] | 498 | */ |
---|
| 499 | |
---|
| 500 | #define SMSC9218I_MAC_ADDRL 0x00000003U |
---|
| 501 | #define SMSC9218I_MAC_ADDRL_MASK 0xffffffffU |
---|
| 502 | |
---|
| 503 | /** @} */ |
---|
| 504 | |
---|
| 505 | /** |
---|
| 506 | * @name Multicast Hash Table High |
---|
[ac7af4a] | 507 | * @{ |
---|
[d374492] | 508 | */ |
---|
| 509 | |
---|
| 510 | #define SMSC9218I_MAC_HASHH 0x00000004U |
---|
| 511 | #define SMSC9218I_MAC_HASHH_MASK 0xffffffffU |
---|
| 512 | |
---|
| 513 | /** @} */ |
---|
| 514 | |
---|
| 515 | /** |
---|
| 516 | * @name Multicast Hash Table Low |
---|
[ac7af4a] | 517 | * @{ |
---|
[d374492] | 518 | */ |
---|
| 519 | |
---|
| 520 | #define SMSC9218I_MAC_HASHL 0x00000005U |
---|
| 521 | #define SMSC9218I_MAC_HASHL_MASK 0xffffffffU |
---|
| 522 | |
---|
| 523 | /** @} */ |
---|
| 524 | |
---|
| 525 | /** |
---|
| 526 | * @name MII Access |
---|
[ac7af4a] | 527 | * @{ |
---|
[d374492] | 528 | */ |
---|
| 529 | |
---|
| 530 | #define SMSC9218I_MAC_MII_ACC 0x00000006U |
---|
| 531 | #define SMSC9218I_MAC_MII_ACC_PHY_DEFAULT (1U << 11) |
---|
| 532 | #define SMSC9218I_MAC_MII_ACC_WRITE (1U << 1) |
---|
| 533 | #define SMSC9218I_MAC_MII_ACC_BUSY (1U << 0) |
---|
| 534 | #define SMSC9218I_MAC_MII_ACC_ADDR(addr) ((addr) << 6) |
---|
| 535 | |
---|
| 536 | /** @} */ |
---|
| 537 | |
---|
| 538 | /** |
---|
| 539 | * @name MII Data |
---|
[ac7af4a] | 540 | * @{ |
---|
[d374492] | 541 | */ |
---|
| 542 | |
---|
| 543 | #define SMSC9218I_MAC_MII_DATA 0x00000007U |
---|
| 544 | |
---|
| 545 | /** @} */ |
---|
| 546 | |
---|
| 547 | /** |
---|
| 548 | * @name Flow Control |
---|
[ac7af4a] | 549 | * @{ |
---|
[d374492] | 550 | */ |
---|
| 551 | |
---|
| 552 | #define SMSC9218I_MAC_FLOW 0x00000008U |
---|
| 553 | #define SMSC9218I_MAC_FLOW_FCPT_MASK 0xffff0000U |
---|
| 554 | #define SMSC9218I_MAC_FLOW_FCPASS 0x00000004U |
---|
| 555 | #define SMSC9218I_MAC_FLOW_FCEN 0x00000002U |
---|
| 556 | #define SMSC9218I_MAC_FLOW_FCBSY 0x00000001U |
---|
| 557 | |
---|
| 558 | /** @} */ |
---|
| 559 | |
---|
| 560 | /** |
---|
| 561 | * @name VLAN1 Tag |
---|
[ac7af4a] | 562 | * @{ |
---|
[d374492] | 563 | */ |
---|
| 564 | |
---|
| 565 | #define SMSC9218I_MAC_VLAN1 0x00000009U |
---|
| 566 | |
---|
| 567 | /** @} */ |
---|
| 568 | |
---|
| 569 | /** |
---|
| 570 | * @name VLAN2 Tag |
---|
[ac7af4a] | 571 | * @{ |
---|
[d374492] | 572 | */ |
---|
| 573 | |
---|
| 574 | #define SMSC9218I_MAC_VLAN2 0x0000000aU |
---|
| 575 | |
---|
| 576 | /** @} */ |
---|
| 577 | |
---|
| 578 | /** |
---|
| 579 | * @name Wake-up Frame Filter |
---|
[ac7af4a] | 580 | * @{ |
---|
[d374492] | 581 | */ |
---|
| 582 | |
---|
| 583 | #define SMSC9218I_MAC_WUFF 0x0000000bU |
---|
| 584 | |
---|
| 585 | /** @} */ |
---|
| 586 | |
---|
| 587 | /** |
---|
| 588 | * @name Wake-up Control and Status |
---|
[ac7af4a] | 589 | * @{ |
---|
[d374492] | 590 | */ |
---|
| 591 | |
---|
| 592 | #define SMSC9218I_MAC_WUCSR 0x0000000cU |
---|
| 593 | #define SMSC9218I_MAC_WUCSR_GUE 0x00000200U |
---|
| 594 | #define SMSC9218I_MAC_WUCSR_WUFR 0x00000040U |
---|
| 595 | #define SMSC9218I_MAC_WUCSR_MPR 0x00000020U |
---|
| 596 | #define SMSC9218I_MAC_WUCSR_WUEN 0x00000004U |
---|
| 597 | #define SMSC9218I_MAC_WUCSR_MPEN 0x00000002U |
---|
| 598 | |
---|
| 599 | /** @} */ |
---|
| 600 | |
---|
| 601 | /** |
---|
| 602 | * @name Basic Control |
---|
[ac7af4a] | 603 | * @{ |
---|
[d374492] | 604 | */ |
---|
| 605 | |
---|
| 606 | #define SMSC9218I_PHY_BCR 0x00000000U |
---|
| 607 | #define SMSC9218I_PHY_BCR_RST 0x00008000U |
---|
| 608 | #define SMSC9218I_PHY_BCR_LOOPBK 0x00004000U |
---|
| 609 | #define SMSC9218I_PHY_BCR_SS 0x00002000U |
---|
| 610 | #define SMSC9218I_PHY_BCR_ANE 0x00001000U |
---|
| 611 | #define SMSC9218I_PHY_BCR_PWRDN 0x00000800U |
---|
| 612 | #define SMSC9218I_PHY_BCR_RSTAN 0x00000200U |
---|
| 613 | #define SMSC9218I_PHY_BCR_FDPLX 0x00000100U |
---|
| 614 | #define SMSC9218I_PHY_BCR_COLLTST 0x00000080U |
---|
| 615 | |
---|
| 616 | /** @} */ |
---|
| 617 | |
---|
| 618 | /** |
---|
| 619 | * @name Basic Status |
---|
[ac7af4a] | 620 | * @{ |
---|
[d374492] | 621 | */ |
---|
| 622 | |
---|
| 623 | #define SMSC9218I_PHY_BSR 0x00000001U |
---|
| 624 | #define SMSC9218I_PHY_BSR_100_T4_ABLE 0x00008000U |
---|
| 625 | #define SMSC9218I_PHY_BSR_100_TX_FDPLX 0x00004000U |
---|
| 626 | #define SMSC9218I_PHY_BSR_100_TX_HDPLX 0x00002000U |
---|
| 627 | #define SMSC9218I_PHY_BSR_10_FDPLX 0x00001000U |
---|
| 628 | #define SMSC9218I_PHY_BSR_10_HDPLX 0x00000800U |
---|
| 629 | #define SMSC9218I_PHY_BSR_ANC 0x00000020U |
---|
| 630 | #define SMSC9218I_PHY_BSR_REM_FAULT 0x00000010U |
---|
| 631 | #define SMSC9218I_PHY_BSR_AN_ABLE 0x00000008U |
---|
| 632 | #define SMSC9218I_PHY_BSR_LINK_STATUS 0x00000004U |
---|
| 633 | #define SMSC9218I_PHY_BSR_JAB_DET 0x00000002U |
---|
| 634 | #define SMSC9218I_PHY_BSR_EXT_CAP 0x00000001U |
---|
| 635 | |
---|
| 636 | /** @} */ |
---|
| 637 | |
---|
| 638 | /** |
---|
| 639 | * @name PHY Identifier 1 |
---|
[ac7af4a] | 640 | * @{ |
---|
[d374492] | 641 | */ |
---|
| 642 | |
---|
| 643 | #define SMSC9218I_PHY_ID1 0x00000002U |
---|
| 644 | #define SMSC9218I_PHY_ID1_MASK 0x0000ffffU |
---|
| 645 | #define SMSC9218I_PHY_ID1_LAN9118 0x00000007U |
---|
| 646 | #define SMSC9218I_PHY_ID1_LAN9218 (PHY_ID1_LAN9118) |
---|
| 647 | |
---|
| 648 | /** @} */ |
---|
| 649 | |
---|
| 650 | /** |
---|
| 651 | * @name PHY Identifier 2 |
---|
[ac7af4a] | 652 | * @{ |
---|
[d374492] | 653 | */ |
---|
| 654 | |
---|
| 655 | #define SMSC9218I_PHY_ID2 0x00000003U |
---|
| 656 | #define SMSC9218I_PHY_ID2_MASK 0x0000ffffU |
---|
| 657 | #define SMSC9218I_PHY_ID2_MODEL_MASK 0x000003f0U |
---|
| 658 | #define SMSC9218I_PHY_ID2_REV_MASK 0x0000000fU |
---|
| 659 | #define SMSC9218I_PHY_ID2_LAN9118 0x0000c0d1U |
---|
| 660 | #define SMSC9218I_PHY_ID2_LAN9218 0x0000c0c3U |
---|
| 661 | |
---|
| 662 | /** @} */ |
---|
| 663 | |
---|
| 664 | /** |
---|
| 665 | * @name Auto-negotiation Advertisment |
---|
[ac7af4a] | 666 | * @{ |
---|
[d374492] | 667 | */ |
---|
| 668 | |
---|
| 669 | #define SMSC9218I_PHY_ANAR 0x00000004U |
---|
| 670 | #define SMSC9218I_PHY_ANAR_NXTPG_CAP 0x00008000U |
---|
| 671 | #define SMSC9218I_PHY_ANAR_REM_FAULT 0x00002000U |
---|
| 672 | #define SMSC9218I_PHY_ANAR_PAUSE_OP_MASK 0x00000c00U |
---|
| 673 | #define SMSC9218I_PHY_ANAR_PAUSE_OP_NONE 0x00000000U |
---|
| 674 | #define SMSC9218I_PHY_ANAR_PAUSE_OP_ASLP 0x00000400U |
---|
| 675 | #define SMSC9218I_PHY_ANAR_PAUSE_OP_SLP 0x00000800U |
---|
| 676 | #define SMSC9218I_PHY_ANAR_PAUSE_OP_BOTH 0x00000c00U |
---|
| 677 | #define SMSC9218I_PHY_ANAR_100_T4_ABLE 0x00000200U |
---|
| 678 | #define SMSC9218I_PHY_ANAR_100_TX_FDPLX 0x00000100U |
---|
| 679 | #define SMSC9218I_PHY_ANAR_100_TX_ABLE 0x00000080U |
---|
| 680 | #define SMSC9218I_PHY_ANAR_10_FDPLX 0x00000040U |
---|
| 681 | #define SMSC9218I_PHY_ANAR_10_ABLE 0x00000020U |
---|
| 682 | |
---|
| 683 | /** @} */ |
---|
| 684 | |
---|
| 685 | /** |
---|
| 686 | * @name Auto-negotiation Link Partner Ability |
---|
[ac7af4a] | 687 | * @{ |
---|
[d374492] | 688 | */ |
---|
| 689 | |
---|
| 690 | #define SMSC9218I_PHY_ANLPAR 0x00000005U |
---|
| 691 | #define SMSC9218I_PHY_ANLPAR_NXTPG_CAP 0x00008000U |
---|
| 692 | #define SMSC9218I_PHY_ANLPAR_ACK 0x00004000U |
---|
| 693 | #define SMSC9218I_PHY_ANLPAR_REM_FAULT 0x00002000U |
---|
| 694 | #define SMSC9218I_PHY_ANLPAR_PAUSE_CAP 0x00000400U |
---|
| 695 | #define SMSC9218I_PHY_ANLPAR_100_T4_ABLE 0x00000200U |
---|
| 696 | #define SMSC9218I_PHY_ANLPAR_100_TX_FDPLX 0x00000100U |
---|
| 697 | #define SMSC9218I_PHY_ANLPAR_100_TX_ABLE 0x00000080U |
---|
| 698 | #define SMSC9218I_PHY_ANLPAR_10_FDPLX 0x00000040U |
---|
| 699 | #define SMSC9218I_PHY_ANLPAR_10_ABLE 0x00000020U |
---|
| 700 | |
---|
| 701 | /** @} */ |
---|
| 702 | |
---|
| 703 | /** |
---|
| 704 | * @name Auto-negotiation Expansion |
---|
[ac7af4a] | 705 | * @{ |
---|
[d374492] | 706 | */ |
---|
| 707 | |
---|
| 708 | #define SMSC9218I_PHY_ANEXPR 0x00000006U |
---|
| 709 | #define SMSC9218I_PHY_ANEXPR_PARDET_FAULT 0x00000010U |
---|
| 710 | #define SMSC9218I_PHY_ANEXPR_LP_NXTPG_CAP 0x00000008U |
---|
| 711 | #define SMSC9218I_PHY_ANEXPR_NXTPG_CAP 0x00000004U |
---|
| 712 | #define SMSC9218I_PHY_ANEXPR_NEWPG_REC 0x00000002U |
---|
| 713 | #define SMSC9218I_PHY_ANEXPR_LP_AN_ABLE 0x00000001U |
---|
| 714 | |
---|
| 715 | /** @} */ |
---|
| 716 | |
---|
| 717 | /** |
---|
| 718 | * @name Mode Control and Status |
---|
[ac7af4a] | 719 | * @{ |
---|
[d374492] | 720 | */ |
---|
| 721 | |
---|
| 722 | #define SMSC9218I_PHY_MCSR 0x00000011U |
---|
| 723 | #define SMSC9218I_PHY_MCSR_EDPWRDOWN 0x00002000U |
---|
| 724 | #define SMSC9218I_PHY_MCSR_ENERGYON 0x00000002U |
---|
| 725 | |
---|
| 726 | /** @} */ |
---|
| 727 | |
---|
| 728 | /** |
---|
| 729 | * @name Special Modes |
---|
[ac7af4a] | 730 | * @{ |
---|
[d374492] | 731 | */ |
---|
| 732 | |
---|
| 733 | #define SMSC9218I_PHY_SPMODES 0x00000012U |
---|
| 734 | |
---|
| 735 | /** @} */ |
---|
| 736 | |
---|
| 737 | /** |
---|
| 738 | * @name Special Control and Status Indications |
---|
[ac7af4a] | 739 | * @{ |
---|
[d374492] | 740 | */ |
---|
| 741 | |
---|
| 742 | #define SMSC9218I_PHY_CSIR 0x0000001bU |
---|
| 743 | #define SMSC9218I_PHY_CSIR_SQEOFF 0x00000800U |
---|
| 744 | #define SMSC9218I_PHY_CSIR_FEFIEN 0x00000020U |
---|
| 745 | #define SMSC9218I_PHY_CSIR_XPOL 0x00000010U |
---|
| 746 | |
---|
| 747 | /** @} */ |
---|
| 748 | |
---|
| 749 | /** |
---|
| 750 | * @name Interrupt Source Flag |
---|
[ac7af4a] | 751 | * @{ |
---|
[d374492] | 752 | */ |
---|
| 753 | |
---|
| 754 | #define SMSC9218I_PHY_ISR 0x0000001dU |
---|
| 755 | #define SMSC9218I_PHY_ISR_INT7 0x00000080U |
---|
| 756 | #define SMSC9218I_PHY_ISR_INT6 0x00000040U |
---|
| 757 | #define SMSC9218I_PHY_ISR_INT5 0x00000020U |
---|
| 758 | #define SMSC9218I_PHY_ISR_INT4 0x00000010U |
---|
| 759 | #define SMSC9218I_PHY_ISR_INT3 0x00000008U |
---|
| 760 | #define SMSC9218I_PHY_ISR_INT2 0x00000004U |
---|
| 761 | #define SMSC9218I_PHY_ISR_INT1 0x00000002U |
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| 762 | |
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| 763 | /** @} */ |
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| 764 | |
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| 765 | /** |
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| 766 | * @name Interrupt Mask |
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[ac7af4a] | 767 | * @{ |
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[d374492] | 768 | */ |
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| 769 | |
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| 770 | #define SMSC9218I_PHY_IMR 0x0000001eU |
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| 771 | #define SMSC9218I_PHY_IMR_INT7 0x00000080U |
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| 772 | #define SMSC9218I_PHY_IMR_INT6 0x00000040U |
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| 773 | #define SMSC9218I_PHY_IMR_INT5 0x00000020U |
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| 774 | #define SMSC9218I_PHY_IMR_INT4 0x00000010U |
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| 775 | #define SMSC9218I_PHY_IMR_INT3 0x00000008U |
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| 776 | #define SMSC9218I_PHY_IMR_INT2 0x00000004U |
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| 777 | #define SMSC9218I_PHY_IMR_INT1 0x00000002U |
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| 778 | |
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| 779 | /** @} */ |
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| 780 | |
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| 781 | /** |
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| 782 | * @name PHY Special Control and Status |
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[ac7af4a] | 783 | * @{ |
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[d374492] | 784 | */ |
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| 785 | |
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| 786 | #define SMSC9218I_PHY_PHYSCSR 0x0000001fU |
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| 787 | #define SMSC9218I_PHY_PHYSCSR_ANDONE 0x00001000U |
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| 788 | #define SMSC9218I_PHY_PHYSCSR_4B5B_EN 0x00000040U |
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| 789 | #define SMSC9218I_PHY_PHYSCSR_SPEED_MASK 0x0000001cU |
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| 790 | #define SMSC9218I_PHY_PHYSCSR_SPEED_10HD 0x00000004U |
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| 791 | #define SMSC9218I_PHY_PHYSCSR_SPEED_10FD 0x00000014U |
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| 792 | #define SMSC9218I_PHY_PHYSCSR_SPEED_100HD 0x00000008U |
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| 793 | #define SMSC9218I_PHY_PHYSCSR_SPEED_100FD 0x00000018U |
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| 794 | |
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| 795 | /** @} */ |
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