1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief Console ESCI implementation. |
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5 | */ |
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6 | |
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7 | /* |
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8 | * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved. |
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9 | * |
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10 | * embedded brains GmbH |
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11 | * Obere Lagerstr. 30 |
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12 | * 82178 Puchheim |
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13 | * Germany |
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14 | * <rtems@embedded-brains.de> |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.com/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #include <bsp/console-esci.h> |
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22 | |
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23 | #include <bsp.h> |
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24 | #include <bsp/irq.h> |
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25 | |
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26 | #ifdef MPC55XX_HAS_ESCI |
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27 | |
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28 | mpc55xx_esci_context mpc55xx_esci_devices [] = { |
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29 | { |
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30 | .regs = &ESCI_A, |
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31 | .irq = MPC55XX_IRQ_ESCI(0) |
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32 | }, { |
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33 | .regs = &ESCI_B, |
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34 | .irq = MPC55XX_IRQ_ESCI(1) |
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35 | } |
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36 | }; |
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37 | |
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38 | static void mpc55xx_esci_poll_write(int minor, char c) |
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39 | { |
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40 | mpc55xx_esci_context *self = console_generic_get_context(minor); |
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41 | const union ESCI_SR_tag clear_tdre = { .B = { .TDRE = 1 } }; |
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42 | volatile struct ESCI_tag *regs = self->regs; |
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43 | rtems_interrupt_level level; |
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44 | bool done = false; |
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45 | bool wait_for_transmit_done = false; |
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46 | |
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47 | rtems_interrupt_disable(level); |
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48 | if (self->transmit_nest_level == 0) { |
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49 | union ESCI_CR1_tag cr1 = { .R = regs->CR1.R }; |
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50 | |
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51 | if (cr1.B.TIE != 0) { |
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52 | cr1.B.TIE = 0; |
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53 | regs->CR1.R = cr1.R; |
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54 | wait_for_transmit_done = !self->transmit_in_progress; |
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55 | self->transmit_nest_level = 1; |
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56 | } |
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57 | } else { |
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58 | ++self->transmit_nest_level; |
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59 | } |
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60 | rtems_interrupt_enable(level); |
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61 | |
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62 | while (!done) { |
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63 | rtems_interrupt_disable(level); |
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64 | bool tx = self->transmit_in_progress; |
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65 | if (!tx || (tx && regs->SR.B.TDRE)) { |
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66 | regs->SR.R = clear_tdre.R; |
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67 | regs->DR.B.D = c; |
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68 | self->transmit_in_progress = true; |
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69 | done = true; |
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70 | } |
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71 | rtems_interrupt_enable(level); |
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72 | } |
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73 | |
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74 | done = false; |
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75 | while (!done) { |
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76 | rtems_interrupt_disable(level); |
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77 | if (wait_for_transmit_done) { |
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78 | if (regs->SR.B.TDRE) { |
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79 | regs->SR.R = clear_tdre.R; |
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80 | self->transmit_in_progress = false; |
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81 | done = true; |
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82 | } |
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83 | } else { |
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84 | done = true; |
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85 | } |
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86 | |
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87 | if (done && self->transmit_nest_level > 0) { |
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88 | --self->transmit_nest_level; |
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89 | |
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90 | if (self->transmit_nest_level == 0) { |
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91 | union ESCI_CR1_tag cr1 = { .R = regs->CR1.R }; |
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92 | |
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93 | cr1.B.TIE = 1; |
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94 | regs->CR1.R = cr1.R; |
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95 | } |
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96 | } |
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97 | rtems_interrupt_enable(level); |
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98 | } |
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99 | } |
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100 | |
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101 | static inline void mpc55xx_esci_interrupts_clear_and_enable( |
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102 | mpc55xx_esci_context *self |
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103 | ) |
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104 | { |
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105 | volatile struct ESCI_tag *regs = self->regs; |
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106 | union ESCI_CR1_tag cr1 = MPC55XX_ZERO_FLAGS; |
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107 | rtems_interrupt_level level; |
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108 | |
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109 | rtems_interrupt_disable(level); |
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110 | cr1.R = regs->CR1.R; |
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111 | cr1.B.RIE = 1; |
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112 | cr1.B.TIE = 1; |
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113 | regs->CR1.R = cr1.R; |
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114 | regs->SR.R = regs->SR.R; |
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115 | rtems_interrupt_enable(level); |
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116 | } |
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117 | |
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118 | static inline void mpc55xx_esci_interrupts_disable(mpc55xx_esci_context *self) |
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119 | { |
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120 | volatile struct ESCI_tag *regs = self->regs; |
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121 | union ESCI_CR1_tag cr1 = MPC55XX_ZERO_FLAGS; |
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122 | rtems_interrupt_level level; |
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123 | |
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124 | rtems_interrupt_disable(level); |
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125 | cr1.R = regs->CR1.R; |
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126 | cr1.B.RIE = 0; |
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127 | cr1.B.TIE = 0; |
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128 | regs->CR1.R = cr1.R; |
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129 | rtems_interrupt_enable(level); |
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130 | } |
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131 | |
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132 | static void mpc55xx_esci_interrupt_handler(void *arg) |
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133 | { |
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134 | mpc55xx_esci_context *self = arg; |
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135 | volatile struct ESCI_tag *regs = self->regs; |
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136 | union ESCI_SR_tag sr = MPC55XX_ZERO_FLAGS; |
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137 | union ESCI_SR_tag active = MPC55XX_ZERO_FLAGS; |
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138 | rtems_interrupt_level level; |
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139 | |
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140 | /* Status */ |
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141 | sr.R = regs->SR.R; |
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142 | |
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143 | /* Receive data register full? */ |
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144 | if (sr.B.RDRF != 0) { |
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145 | active.B.RDRF = 1; |
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146 | } |
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147 | |
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148 | /* Transmit data register empty? */ |
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149 | if (sr.B.TDRE != 0) { |
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150 | active.B.TDRE = 1; |
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151 | } |
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152 | |
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153 | /* Clear flags */ |
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154 | rtems_interrupt_disable(level); |
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155 | regs->SR.R = active.R; |
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156 | self->transmit_in_progress = false; |
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157 | rtems_interrupt_enable(level); |
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158 | |
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159 | /* Enqueue */ |
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160 | if (active.B.RDRF != 0) { |
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161 | char c = regs->DR.B.D; |
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162 | rtems_termios_enqueue_raw_characters(self->tty, &c, 1); |
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163 | } |
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164 | |
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165 | /* Dequeue */ |
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166 | if (active.B.TDRE != 0) { |
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167 | rtems_termios_dequeue_characters(self->tty, 1); |
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168 | } |
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169 | } |
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170 | |
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171 | static int mpc55xx_esci_set_attributes(int minor, const struct termios *t) |
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172 | { |
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173 | mpc55xx_esci_context *self = console_generic_get_context(minor); |
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174 | volatile struct ESCI_tag *regs = self->regs; |
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175 | union ESCI_CR1_tag cr1 = { .R = regs->CR1.R }; |
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176 | union ESCI_CR2_tag cr2 = MPC55XX_ZERO_FLAGS; |
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177 | rtems_termios_baud_t br = rtems_termios_baud_to_number(t->c_cflag); |
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178 | |
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179 | /* Enable module */ |
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180 | cr2.B.MDIS = 0; |
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181 | |
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182 | /* Interrupts */ |
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183 | cr1.B.TCIE = 0; |
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184 | cr1.B.ILIE = 0; |
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185 | cr2.B.IEBERR = 0; |
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186 | cr2.B.ORIE = 0; |
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187 | cr2.B.NFIE = 0; |
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188 | cr2.B.FEIE = 0; |
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189 | cr2.B.PFIE = 0; |
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190 | |
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191 | /* Disable receiver wake-up standby */ |
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192 | cr1.B.RWU = 0; |
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193 | |
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194 | /* Disable DMA channels */ |
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195 | cr2.B.RXDMA = 0; |
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196 | cr2.B.TXDMA = 0; |
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197 | |
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198 | /* Idle line type */ |
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199 | cr1.B.ILT = 0; |
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200 | |
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201 | /* Disable loops */ |
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202 | cr1.B.LOOPS = 0; |
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203 | |
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204 | /* Enable or disable receiver */ |
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205 | cr1.B.RE = (t->c_cflag & CREAD) ? 1 : 0; |
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206 | |
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207 | /* Enable transmitter */ |
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208 | cr1.B.TE = 1; |
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209 | |
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210 | /* Baud rate */ |
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211 | if (br > 0) { |
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212 | br = bsp_clock_speed / (16 * br); |
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213 | br = (br > 8191) ? 8191 : br; |
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214 | } else { |
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215 | br = 0; |
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216 | } |
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217 | cr1.B.SBR = br; |
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218 | |
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219 | /* Number of data bits */ |
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220 | if ((t->c_cflag & CSIZE) != CS8) { |
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221 | return -1; |
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222 | } |
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223 | cr1.B.M = 0; |
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224 | |
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225 | /* Parity */ |
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226 | cr1.B.PE = (t->c_cflag & PARENB) ? 1 : 0; |
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227 | cr1.B.PT = (t->c_cflag & PARODD) ? 1 : 0; |
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228 | |
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229 | /* Stop bits */ |
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230 | if (t->c_cflag & CSTOPB ) { |
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231 | /* Two stop bits */ |
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232 | return -1; |
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233 | } |
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234 | |
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235 | /* Disable LIN */ |
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236 | regs->LCR.R = 0; |
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237 | |
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238 | /* Set control registers */ |
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239 | regs->CR2.R = cr2.R; |
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240 | regs->CR1.R = cr1.R; |
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241 | |
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242 | return 0; |
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243 | } |
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244 | |
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245 | static int mpc55xx_esci_first_open(int major, int minor, void *arg) |
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246 | { |
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247 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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248 | int rv = 0; |
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249 | mpc55xx_esci_context *self = console_generic_get_context(minor); |
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250 | struct rtems_termios_tty *tty = console_generic_get_tty_at_open(arg); |
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251 | |
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252 | self->tty = tty; |
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253 | |
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254 | rv = rtems_termios_set_initial_baud(tty, 115200); |
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255 | if (rv != 0) { |
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256 | rtems_fatal_error_occurred(0xdeadbeef); |
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257 | } |
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258 | |
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259 | rv = mpc55xx_esci_set_attributes(minor, &tty->termios); |
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260 | if (rv != 0) { |
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261 | rtems_fatal_error_occurred(0xdeadbeef); |
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262 | } |
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263 | |
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264 | sc = mpc55xx_interrupt_handler_install( |
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265 | self->irq, |
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266 | "eSCI", |
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267 | RTEMS_INTERRUPT_UNIQUE, |
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268 | MPC55XX_INTC_DEFAULT_PRIORITY, |
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269 | mpc55xx_esci_interrupt_handler, |
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270 | self |
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271 | ); |
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272 | if (sc != RTEMS_SUCCESSFUL) { |
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273 | rtems_fatal_error_occurred(0xdeadbeef); |
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274 | } |
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275 | |
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276 | mpc55xx_esci_interrupts_clear_and_enable(self); |
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277 | self->transmit_in_progress = false; |
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278 | |
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279 | return 0; |
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280 | } |
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281 | |
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282 | static int mpc55xx_esci_last_close(int major, int minor, void* arg) |
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283 | { |
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284 | mpc55xx_esci_context *self = console_generic_get_context(minor); |
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285 | |
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286 | mpc55xx_esci_interrupts_disable(self); |
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287 | self->tty = NULL; |
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288 | |
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289 | return 0; |
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290 | } |
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291 | |
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292 | static int mpc55xx_esci_poll_read(int minor) |
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293 | { |
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294 | mpc55xx_esci_context *self = console_generic_get_context(minor); |
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295 | volatile struct ESCI_tag *regs = self->regs; |
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296 | union ESCI_SR_tag sr = MPC55XX_ZERO_FLAGS; |
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297 | rtems_interrupt_level level; |
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298 | int c = -1; |
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299 | |
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300 | rtems_interrupt_disable(level); |
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301 | if (regs->SR.B.RDRF != 0) { |
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302 | /* Clear flag */ |
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303 | sr.B.RDRF = 1; |
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304 | regs->SR.R = sr.R; |
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305 | |
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306 | /* Read */ |
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307 | c = regs->DR.B.D; |
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308 | } |
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309 | rtems_interrupt_enable(level); |
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310 | |
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311 | return c; |
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312 | } |
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313 | |
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314 | static int mpc55xx_esci_write(int minor, const char *out, size_t n) |
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315 | { |
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316 | mpc55xx_esci_context *self = console_generic_get_context(minor); |
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317 | rtems_interrupt_level level; |
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318 | |
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319 | rtems_interrupt_disable(level); |
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320 | self->regs->DR.B.D = out [0]; |
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321 | self->transmit_in_progress = true; |
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322 | rtems_interrupt_enable(level); |
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323 | |
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324 | return 0; |
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325 | } |
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326 | |
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327 | const console_generic_callbacks mpc55xx_esci_callbacks = { |
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328 | .termios_callbacks = { |
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329 | .firstOpen = mpc55xx_esci_first_open, |
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330 | .lastClose = mpc55xx_esci_last_close, |
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331 | .write = mpc55xx_esci_write, |
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332 | .setAttributes = mpc55xx_esci_set_attributes, |
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333 | .outputUsesInterrupts = TERMIOS_IRQ_DRIVEN |
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334 | }, |
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335 | .poll_read = mpc55xx_esci_poll_read, |
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336 | .poll_write = mpc55xx_esci_poll_write |
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337 | }; |
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338 | |
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339 | #endif /* MPC55XX_HAS_ESCI */ |
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