1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup mpc55xx |
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5 | * |
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6 | * @brief Clock driver configuration. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009-2013 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Dornierstr. 4 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <bsp.h> |
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24 | #include <bsp/fatal.h> |
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25 | #include <bsp/irq.h> |
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26 | |
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27 | #include <mpc55xx/regs.h> |
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28 | |
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29 | #include <rtems/timecounter.h> |
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30 | |
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31 | void Clock_isr(void *arg); |
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32 | |
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33 | static rtems_timecounter_simple mpc55xx_tc; |
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34 | |
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35 | #if defined(MPC55XX_CLOCK_EMIOS_CHANNEL) |
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36 | |
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37 | #include <mpc55xx/emios.h> |
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38 | |
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39 | static uint32_t mpc55xx_tc_get(rtems_timecounter_simple *tc) |
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40 | { |
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41 | return EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL].CCNTR.R; |
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42 | } |
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43 | |
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44 | static bool mpc55xx_tc_is_pending(rtems_timecounter_simple *tc) |
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45 | { |
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46 | return EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL].CSR.B.FLAG != 0; |
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47 | } |
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48 | |
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49 | static uint32_t mpc55xx_tc_get_timecount(struct timecounter *tc) |
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50 | { |
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51 | return rtems_timecounter_simple_upcounter_get( |
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52 | tc, |
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53 | mpc55xx_tc_get, |
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54 | mpc55xx_tc_is_pending |
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55 | ); |
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56 | } |
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57 | |
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58 | static void mpc55xx_tc_at_tick(rtems_timecounter_simple *tc) |
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59 | { |
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60 | union EMIOS_CSR_tag csr = MPC55XX_ZERO_FLAGS; |
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61 | csr.B.FLAG = 1; |
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62 | EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL].CSR.R = csr.R; |
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63 | } |
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64 | |
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65 | static void mpc55xx_tc_tick(void) |
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66 | { |
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67 | rtems_timecounter_simple_upcounter_tick( |
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68 | &mpc55xx_tc, |
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69 | mpc55xx_tc_get, |
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70 | mpc55xx_tc_at_tick |
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71 | ); |
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72 | } |
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73 | |
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74 | static void mpc55xx_clock_handler_install(rtems_isr_entry isr) |
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75 | { |
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76 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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77 | |
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78 | sc = mpc55xx_interrupt_handler_install( |
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79 | MPC55XX_IRQ_EMIOS(MPC55XX_CLOCK_EMIOS_CHANNEL), |
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80 | "clock", |
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81 | RTEMS_INTERRUPT_UNIQUE, |
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82 | MPC55XX_INTC_MIN_PRIORITY, |
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83 | (rtems_interrupt_handler) isr, |
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84 | NULL |
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85 | ); |
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86 | if (sc != RTEMS_SUCCESSFUL) { |
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87 | bsp_fatal(MPC55XX_FATAL_CLOCK_EMIOS_IRQ_INSTALL); |
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88 | } |
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89 | } |
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90 | |
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91 | static void mpc55xx_clock_initialize(void) |
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92 | { |
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93 | volatile struct EMIOS_CH_tag *regs = &EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL]; |
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94 | union EMIOS_CCR_tag ccr = MPC55XX_ZERO_FLAGS; |
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95 | union EMIOS_CSR_tag csr = MPC55XX_ZERO_FLAGS; |
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96 | unsigned prescaler = mpc55xx_emios_global_prescaler(); |
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97 | uint64_t reference_clock = bsp_clock_speed; |
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98 | uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick(); |
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99 | uint64_t interval = (reference_clock * us_per_tick) / 1000000; |
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100 | |
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101 | /* Apply prescaler */ |
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102 | if (prescaler > 0) { |
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103 | interval /= (uint64_t) prescaler; |
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104 | } else { |
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105 | bsp_fatal(MPC55XX_FATAL_CLOCK_EMIOS_PRESCALER); |
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106 | } |
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107 | |
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108 | /* Check interval */ |
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109 | if (interval == 0 || interval > MPC55XX_EMIOS_VALUE_MAX) { |
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110 | bsp_fatal(MPC55XX_FATAL_CLOCK_EMIOS_INTERVAL); |
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111 | } |
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112 | |
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113 | /* Configure eMIOS channel */ |
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114 | |
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115 | /* Set channel in GPIO mode */ |
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116 | ccr.B.MODE = MPC55XX_EMIOS_MODE_GPIO_INPUT; |
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117 | regs->CCR.R = ccr.R; |
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118 | |
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119 | /* Clear status flags */ |
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120 | csr.B.OVR = 1; |
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121 | csr.B.OVFL = 1; |
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122 | csr.B.FLAG = 1; |
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123 | regs->CSR.R = csr.R; |
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124 | |
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125 | /* Set internal counter start value */ |
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126 | regs->CCNTR.R = 1; |
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127 | |
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128 | /* Set timer period */ |
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129 | regs->CADR.R = (uint32_t) interval - 1; |
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130 | |
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131 | /* Set control register */ |
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132 | #if MPC55XX_CHIP_FAMILY == 551 |
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133 | ccr.B.MODE = MPC55XX_EMIOS_MODE_MCB_UP_INT_CLK; |
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134 | #else |
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135 | ccr.B.MODE = MPC55XX_EMIOS_MODE_MC_UP_INT_CLK; |
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136 | #endif |
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137 | ccr.B.UCPREN = 1; |
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138 | ccr.B.FEN = 1; |
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139 | ccr.B.FREN = 1; |
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140 | regs->CCR.R = ccr.R; |
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141 | |
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142 | rtems_timecounter_simple_install( |
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143 | &mpc55xx_tc, |
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144 | reference_clock, |
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145 | interval, |
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146 | mpc55xx_tc_get_timecount |
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147 | ); |
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148 | } |
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149 | |
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150 | static void mpc55xx_clock_cleanup(void) |
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151 | { |
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152 | volatile struct EMIOS_CH_tag *regs = &EMIOS.CH [MPC55XX_CLOCK_EMIOS_CHANNEL]; |
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153 | union EMIOS_CCR_tag ccr = MPC55XX_ZERO_FLAGS; |
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154 | |
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155 | /* Set channel in GPIO mode */ |
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156 | ccr.B.MODE = MPC55XX_EMIOS_MODE_GPIO_INPUT; |
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157 | regs->CCR.R = ccr.R; |
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158 | } |
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159 | |
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160 | #elif defined(MPC55XX_CLOCK_PIT_CHANNEL) |
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161 | |
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162 | static uint32_t mpc55xx_tc_get(rtems_timecounter_simple *tc) |
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163 | { |
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164 | return PIT_RTI.CHANNEL [MPC55XX_CLOCK_PIT_CHANNEL].CVAL.R; |
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165 | } |
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166 | |
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167 | static bool mpc55xx_tc_is_pending(rtems_timecounter_simple *tc) |
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168 | { |
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169 | return PIT_RTI.CHANNEL [MPC55XX_CLOCK_PIT_CHANNEL].TFLG.B.TIF != 0; |
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170 | } |
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171 | |
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172 | static uint32_t mpc55xx_tc_get_timecount(struct timecounter *tc) |
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173 | { |
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174 | return rtems_timecounter_simple_downcounter_get( |
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175 | tc, |
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176 | mpc55xx_tc_get, |
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177 | mpc55xx_tc_is_pending |
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178 | ); |
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179 | } |
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180 | |
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181 | static void mpc55xx_tc_at_tick(rtems_timecounter_simple *tc) |
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182 | { |
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183 | volatile PIT_RTI_CHANNEL_tag *channel = |
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184 | &PIT_RTI.CHANNEL [MPC55XX_CLOCK_PIT_CHANNEL]; |
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185 | PIT_RTI_TFLG_32B_tag tflg = { .B = { .TIF = 1 } }; |
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186 | |
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187 | channel->TFLG.R = tflg.R; |
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188 | } |
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189 | |
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190 | static void mpc55xx_tc_tick(void) |
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191 | { |
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192 | rtems_timecounter_simple_downcounter_tick( |
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193 | &mpc55xx_tc, |
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194 | mpc55xx_tc_get, |
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195 | mpc55xx_tc_at_tick |
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196 | ); |
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197 | } |
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198 | |
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199 | static void mpc55xx_clock_handler_install(rtems_isr_entry isr) |
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200 | { |
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201 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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202 | |
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203 | sc = mpc55xx_interrupt_handler_install( |
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204 | MPC55XX_IRQ_PIT_CHANNEL(MPC55XX_CLOCK_PIT_CHANNEL), |
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205 | "clock", |
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206 | RTEMS_INTERRUPT_UNIQUE, |
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207 | MPC55XX_INTC_MIN_PRIORITY, |
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208 | (rtems_interrupt_handler) isr, |
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209 | NULL |
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210 | ); |
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211 | if (sc != RTEMS_SUCCESSFUL) { |
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212 | bsp_fatal(MPC55XX_FATAL_CLOCK_PIT_IRQ_INSTALL); |
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213 | } |
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214 | } |
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215 | |
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216 | static void mpc55xx_clock_initialize(void) |
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217 | { |
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218 | volatile PIT_RTI_CHANNEL_tag *channel = |
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219 | &PIT_RTI.CHANNEL [MPC55XX_CLOCK_PIT_CHANNEL]; |
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220 | uint64_t reference_clock = bsp_clock_speed; |
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221 | uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick(); |
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222 | uint64_t interval = (reference_clock * us_per_tick) / 1000000; |
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223 | PIT_RTI_PITMCR_32B_tag pitmcr = { .B = { .FRZ = 1 } }; |
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224 | PIT_RTI_TCTRL_32B_tag tctrl = { .B = { .TIE = 1, .TEN = 1 } }; |
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225 | |
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226 | PIT_RTI.PITMCR.R = pitmcr.R; |
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227 | channel->LDVAL.R = interval; |
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228 | channel->TCTRL.R = tctrl.R; |
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229 | |
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230 | rtems_timecounter_simple_install( |
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231 | &mpc55xx_tc, |
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232 | reference_clock, |
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233 | interval, |
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234 | mpc55xx_tc_get_timecount |
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235 | ); |
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236 | } |
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237 | |
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238 | static void mpc55xx_clock_cleanup(void) |
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239 | { |
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240 | volatile PIT_RTI_CHANNEL_tag *channel = |
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241 | &PIT_RTI.CHANNEL [MPC55XX_CLOCK_PIT_CHANNEL]; |
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242 | |
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243 | channel->TCTRL.R = 0; |
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244 | } |
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245 | |
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246 | #endif |
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247 | |
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248 | #define Clock_driver_timecounter_tick() mpc55xx_tc_tick() |
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249 | #define Clock_driver_support_initialize_hardware() \ |
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250 | mpc55xx_clock_initialize() |
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251 | #define Clock_driver_support_install_isr(isr) \ |
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252 | mpc55xx_clock_handler_install(isr) |
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253 | #define Clock_driver_support_shutdown_hardware() \ |
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254 | mpc55xx_clock_cleanup() |
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255 | |
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256 | /* Include shared source clock driver code */ |
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257 | #include "../../../../libbsp/shared/clockdrv_shell.h" |
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