1 | /* |
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2 | * start.S : RTEMS entry point |
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3 | * |
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4 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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5 | * |
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6 | * The license and distribution terms for this file may be |
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7 | * found in found in the file LICENSE in this distribution or at |
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8 | * http://www.OARcorp.com/rtems/license.html. |
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9 | * |
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10 | * $Id$ |
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11 | * |
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12 | */ |
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13 | |
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14 | #include <libcpu/cpu.h> |
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15 | #include <libcpu/io.h> |
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16 | #include <rtems/score/targopts.h> |
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17 | #include <rtems/score/cpu.h> |
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18 | #include "asm.h" |
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19 | |
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20 | #define SYNC \ |
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21 | sync; \ |
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22 | isync |
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23 | |
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24 | #define KERNELBASE 0x0 |
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25 | |
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26 | #define MONITOR_ENTER \ |
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27 | mfmsr r10 ; \ |
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28 | ori r10,r10,MSR_IP ; \ |
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29 | mtmsr r10 ; \ |
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30 | li r10,0x63 ; \ |
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31 | sc |
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32 | |
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33 | .text |
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34 | .globl __rtems_entry_point |
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35 | .type __rtems_entry_point,@function |
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36 | __rtems_entry_point: |
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37 | #ifdef DEBUG_EARLY_START |
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38 | MONITOR_ENTER |
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39 | #endif |
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40 | |
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41 | /* |
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42 | * PREP |
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43 | * This is jumped to on prep systems right after the kernel is relocated |
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44 | * to its proper place in memory by the boot loader. The expected layout |
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45 | * of the regs is: |
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46 | * r3: ptr to residual data |
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47 | * r4: initrd_start or if no initrd then 0 |
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48 | * r5: initrd_end - unused if r4 is 0 |
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49 | * r6: Start of command line string |
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50 | * r7: End of command line string |
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51 | * |
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52 | */ |
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53 | |
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54 | mr r31,r3 /* save parameters */ |
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55 | mr r30,r4 |
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56 | mr r29,r5 |
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57 | mr r28,r6 |
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58 | mr r27,r7 |
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59 | /* |
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60 | * Use the first pair of BAT registers to map the 1st 64MB |
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61 | * of RAM to KERNELBASE. |
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62 | */ |
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63 | lis r11,KERNELBASE@h |
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64 | ori r11,r11,0x7fe /* set up BAT registers for 604 */ |
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65 | li r8,2 /* R/W access */ |
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66 | mtspr DBAT0L,r8 /* N.B. 6xx (not 601) have valid */ |
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67 | mtspr DBAT0U,r11 /* bit in upper BAT register */ |
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68 | mtspr IBAT0L,r8 |
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69 | mtspr IBAT0U,r11 |
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70 | isync |
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71 | |
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72 | /* |
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73 | * we now have the 1st 64M of ram mapped with the bats. |
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74 | */ |
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75 | |
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76 | enter_C_code: |
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77 | bl MMUon |
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78 | /* |
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79 | * stack = &__rtems_end + 4096 |
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80 | */ |
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81 | addis r9,r0, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@ha |
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82 | addi r9,r9, __rtems_end+(4096-CPU_MINIMUM_STACK_FRAME_SIZE)@l |
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83 | mr r1, r9 |
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84 | bl zero_bss |
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85 | /* |
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86 | * restore prep boot params |
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87 | */ |
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88 | mr r3,r31 |
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89 | mr r4,r30 |
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90 | mr r5,r29 |
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91 | mr r6,r28 |
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92 | mr r7,r27 |
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93 | bl save_boot_params |
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94 | bl boot_card |
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95 | bl _return_to_ppcbug |
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96 | |
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97 | .globl MMUon |
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98 | .type MMUon,@function |
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99 | MMUon: |
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100 | mfmsr r0 |
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101 | ori r0,r0, MSR_IP | MSR_RI | MSR_IR | MSR_DR | MSR_EE | MSR_FE0 | MSR_FE1 |
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102 | xori r0, r0, MSR_EE | MSR_IP | MSR_FP |
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103 | mflr r11 |
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104 | mtsrr0 r11 |
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105 | mtsrr1 r0 |
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106 | SYNC |
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107 | rfi |
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108 | |
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109 | .globl MMUoff |
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110 | .type MMUoff,@function |
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111 | MMUoff: |
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112 | mfmsr r0 |
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113 | ori r0,r0,MSR_IR| MSR_DR | MSR_IP |
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114 | mflr r11 |
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115 | xori r0,r0,MSR_IR|MSR_DR |
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116 | mtsrr0 r11 |
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117 | mtsrr1 r0 |
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118 | SYNC |
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119 | rfi |
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120 | |
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121 | .globl _return_to_ppcbug |
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122 | .type _return_to_ppcbug,@function |
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123 | |
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124 | |
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125 | _return_to_ppcbug: |
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126 | mflr r30 |
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127 | bl MMUoff |
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128 | MONITOR_ENTER |
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129 | bl MMUon |
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130 | mtctr r30 |
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131 | bctr |
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