source: rtems/c/src/lib/libbsp/powerpc/motorola_powerpc/residual/residual.h @ ba46ffa6

4.104.114.84.95
Last change on this file since ba46ffa6 was ba46ffa6, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 14, 1999 at 4:51:13 PM

This is a large patch from Eric Valette <valette@…> that was
described in the message following this paragraph. This patch also includes
a mcp750 BSP.

From valette@… Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@…>
To: joel@…
Cc: raguet@…, rtems-snapshots@…, valette@…
Subject: Questions/Suggestion? regarding RTEMS PowerPC code (long)

Dear knowledgeable RTEMS powerpc users,

As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.

In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.

the MCP750 is a COMPACT PCI powerpc board with :

1) a MPC750 233 MHz processor,
2) a raven bus bridge/PCI controller that
implement an OPENPIC compliant interrupt controller,
3) a VIA 82C586 PCI/ISA bridge that offers a PC
compliant IO for keyboard, serial line, IDE, and
the well known PC 8259 cascaded PIC interrupt
architecture model,
4) a DEC 21140 Ethernet controller,
5) the PPCBUG Motorola firmware in flash,
6) A DEC PCI bridge,

This architecture is common to most Motorola 60x/7xx
board except that :

1) on VME board, the DEC PCI bridge is replaced by
a VME chipset,
2) the VIA 82C586 PCI/ISA bridge is replaced by
another bridge that is almost fully compatible
with the via bridge...

So the port should be a rather close basis for many
60x/7xx motorola board...

On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.

Now the questions/suggestions I have :

1) EXCEPTION CODE


As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :

a) Except for the decrementer exception (and
maybe some other on mpc8xx), exceptions are
not recoverable and the handler just need to print
the full context and go to the firmware or debugger...
b) The interrupt switch is only necessary for the
decrementer and external interrupt (at least on
6xx,7xx).
c) The full context for exception is never saved and
thus cannot be used by debugger... I do understand
the most important for interrupts low level code
is to save the minimal context enabling to call C
code for performance reasons. On non recoverable
exception on the other hand, the most important is
to save the maximum information concerning proc status
in order to analyze the reason of the fault. At
least we will need this in order to implement the
port of RGDB on PPC

==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)

See remark about files/directory layout organization in 4)

2) Current Implementation of ISR low level code


I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S

#if (PPC_USE_SPRG)

mfmsr r5
mfspr r6, sprg2

#else

lwz r6,msr_initial(r11)
lis r5,~PPC_MSR_DISABLE_MASK@ha
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
and r6,r6,r5
mfmsr r5

#endif

Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :

a) I want the MSR[IR] and MSR[DR] to be set for
performance reasons and also because I need DBAT
support to have access to PCI memory space as the
interrupt controller is in the PCI space.

Reading the code, I see others have the same kind of request :

/* SCE 980217

*

  • We need address translation ON when we call our ISR routine

mtmsr r5

*/

This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...

Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO
acknowledged.

I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...

So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)

I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.

3) R2/R13 manipulation for EABI implementation


I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).

So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or
handling.

The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.

=> I propose to suppress any specific code for r2 and
r13 in the EABI case.

4) Code layout organization (yes again :-))


I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.

a) exec/score/cpu/* vs lib/libcpu/cpu/*.

I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.

This include at least :

a) registers access routine (e.g GET_MSR_Value),
b) interrupt masking/unmasking routines,
c) cache_mngt_routine,
d) mmu_mngt_routine,
e) Routines to connect the raw_exception, raw_interrupt
handler,

b) lib/libcpu/cpu/powerpc/*

With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x) the directory structure
is fine (except maybe the names that are not homogeneous)

powerpc

ppc421 mpc821 ...

I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.

So, except if the support of automake provides a better solution
I would like to propose something like this :

powerpc

mpc421 mpc821 ... mpc750 shared wrapup

with the following rules :

a) "shared" would act as a source container for sources that may
be shared among processors. Needed files would be compiled inside
the processor specific directory using the vpath Makefile
mechanism. "shared" may also contain compilation code
for routine that are really shared and not worth to inline...
(did not found many things so far as registers access routine
ARE WORTH INLINING)... In the case something is compiled there,
it should create libcpushared.a

b) layout under processor specific directory is free provided
that

1)the result of the compilation process exports :

libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu

2) each processor specific directory creates
a library called libcpuspecific.a

Note that this organization enables to have a file that
is nearly the same than in shared but that must differ
because of processor differences...

c) "wrapup" should create libcpu.a using libcpushared.a
libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu

The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...

Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...

NB: I have done this for mpc750 and other processors could just use
similar Makefiles...

c) The exec/score/cpu/powerpc directory layout.

I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...

Besides that I do not understand why

1) things are compiled in the wrap directory,
2) some includes are moved to rtems/score,

I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor
directory),

5) Interrupt handling API


Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :


| OPEN | <-----|8259|
| PIC | | | 2 ------
|(RAVEN)| | | <-----|8259|
| | | | | | 11
| | | | | | <----
| | | | | |
| | | | | |


------
| VIA PCI/ISA bridge
| x
-------- PCI interrupts

OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :

1) there is no way to specify priorities among
interrupts handler. This is REALLY a bad thing.
For me it is as importnat as having priorities
for threads...
2) for my implementation, each ISR should
contain the code that acknowledge the RAVEN
and 8259 cascade, modify interrupt mask on both
chips, and reenable interrupt at processor level,
..., restore then on interrupt return,.... This code
is actually similar to code located in some
genpvec.c powerpc files,
3) I must update _ISR_Nesting_level because
irq.inl use it...
4) the libchip code connects the ISR via set_vector
but the libchip handler code does not contain any code to
manipulate external interrupt controller hardware
in order to acknoledge the interrupt or re-enable
them (except for the target hardware of course)
So this code is broken unless set_vector adds an
additionnal prologue/epilogue before calling/returning
from in order to acknoledge/mask the raven and the
8259 PICS... => Anyway already EACH BSP MUST REWRITE
PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT
SET_VECTOR.

I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :

1) Once the driver supplied methods is called the
only things the ISR has to do is to worry about the
external hardware that triggered the interrupt.
Everything on openpic/VIA/processor would have been
done by the low levels (same things as set-vector)
2) The caller will need to supply the on/off/isOn
routine that are fundamental to correctly implements
debuggers/performance monitoring is a portable way
3) A globally configurable interrupt priorities
mechanism...

I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).

Additional note : I think the _ISR_Is_in_progress()
inline routine should be :

1) Put in a processor specific section,
2) Should not rely on a global variable,

As :

a) on symmetric MP, there is one interrupt level
per CPU,
b) On processor that have an ISP (e,g 68040),
this variable is useless (MSR bit testing could
be used)
c) On PPC, instead of using the address of the
variable via CPU_IRQ_info.Nest_level a dedicated
SPR could be used.

NOTE: most of this is also true for _Thread_Dispatch_disable_level

END NOTE


Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :

1) try to better understand the actual code,
2) propose concrete ways of enhancing current code
by providing an alternative implementation for MCP750. I
will make my best effort to try to brake nothing but this
is actually hard due to the file layout organisation.
3) make understandable some changes I will probably make
if joel let me do them :-)

Any comments/objections are welcomed as usual.

--


/ ` Eric Valette

/-- o _. Canon CRF

(_, / (_(_( Rue de la touche lambert

35517 Cesson-Sevigne Cedex
FRANCE

Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30
E-mail: valette@…

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File size: 14.5 KB
Line 
1/* 7/18/95                                                                    */
2/*----------------------------------------------------------------------------*/
3/*      Residual Data header definitions and prototypes                       */
4/*----------------------------------------------------------------------------*/
5
6/* Structure map for RESIDUAL on PowerPC Reference Platform                   */
7/* residual.h - Residual data structure passed in r3.                         */
8/*              Load point passed in r4 to boot image.                        */
9/* For enum's: if given in hex then they are bit significant,                 */
10/*             i.e. only one bit is on for each enum                          */
11/* Reserved fields must be filled with zeros.                                */
12
13#ifndef _RESIDUAL_
14#define _RESIDUAL_
15
16#ifndef ASM
17
18#define MAX_CPUS 32                     /* These should be set to the maximum */
19#define MAX_MEMS 64                     /* number possible for this system.   */
20#define MAX_DEVICES 256                 /* Changing these will change the     */
21#define AVE_PNP_SIZE 32                 /* structure, hence the version of    */
22#define MAX_MEM_SEGS 64                 /* this header file.                  */
23
24/*----------------------------------------------------------------------------*/
25/*               Public structures...                                         */
26/*----------------------------------------------------------------------------*/
27
28#include "pnp.h"
29
30typedef enum _L1CACHE_TYPE {
31  NoneCAC = 0,
32  SplitCAC = 1,
33  CombinedCAC = 2
34  } L1CACHE_TYPE;
35
36typedef enum _TLB_TYPE {
37  NoneTLB = 0,
38  SplitTLB = 1,
39  CombinedTLB = 2
40  } TLB_TYPE;
41
42typedef enum _FIRMWARE_SUPPORT {
43  Conventional = 0x01,
44  OpenFirmware = 0x02,
45  Diagnostics = 0x04,
46  LowDebug = 0x08,
47  Multiboot = 0x10,
48  LowClient = 0x20,
49  Hex41 = 0x40,
50  FAT = 0x80,
51  ISO9660 = 0x0100,
52  SCSI_InitiatorID_Override = 0x0200,
53  Tape_Boot = 0x0400,
54  FW_Boot_Path = 0x0800
55  } FIRMWARE_SUPPORT;
56
57typedef enum _FIRMWARE_SUPPLIERS {
58  IBMFirmware = 0x00,
59  MotoFirmware = 0x01,                  /* 7/18/95                            */
60  FirmWorks = 0x02,                     /* 10/5/95                            */
61  Bull = 0x03,                          /* 04/03/96                           */
62  } FIRMWARE_SUPPLIERS;
63
64typedef enum _ENDIAN_SWITCH_METHODS {
65  UsePort92 = 0x01,
66  UsePCIConfigA8 = 0x02,
67  UseFF001030 = 0x03,
68  } ENDIAN_SWITCH_METHODS;
69
70typedef enum _SPREAD_IO_METHODS {
71  UsePort850 = 0x00,
72/*UsePCIConfigA8 = 0x02,*/
73  } SPREAD_IO_METHODS;
74
75typedef struct _VPD {
76
77  /* Box dependent stuff */
78  unsigned char PrintableModel[32];     /* Null terminated string.
79                                           Must be of the form:
80                                           vvv,<20h>,<model designation>,<0x0>
81                                           where vvv is the vendor ID
82                                           e.g. IBM PPS MODEL 6015<0x0>       */
83  unsigned char Serial[16];             /* 12/94:
84                                           Serial Number; must be of the form:
85                                           vvv<serial number> where vvv is the
86                                           vendor ID.
87                                           e.g. IBM60151234567<20h><20h>      */
88  unsigned char Reserved[48];
89  unsigned long FirmwareSupplier;       /* See FirmwareSuppliers enum         */
90  unsigned long FirmwareSupports;       /* See FirmwareSupport enum           */
91  unsigned long NvramSize;              /* Size of nvram in bytes             */
92  unsigned long NumSIMMSlots;
93  unsigned short EndianSwitchMethod;    /* See EndianSwitchMethods enum       */
94  unsigned short SpreadIOMethod;        /* See SpreadIOMethods enum           */
95  unsigned long SmpIar;
96  unsigned long RAMErrLogOffset;        /* Heap offset to error log           */
97  unsigned long Reserved5;
98  unsigned long Reserved6;
99  unsigned long ProcessorHz;            /* Processor clock frequency in Hertz */
100  unsigned long ProcessorBusHz;         /* Processor bus clock frequency      */
101  unsigned long Reserved7;
102  unsigned long TimeBaseDivisor;        /* (Bus clocks per timebase tic)*1000 */
103  unsigned long WordWidth;              /* Word width in bits                 */
104  unsigned long PageSize;               /* Page size in bytes                 */
105  unsigned long CoherenceBlockSize;     /* Unit of transfer in/out of cache
106                                           for which coherency is maintained;
107                                           normally <= CacheLineSize.         */
108  unsigned long GranuleSize;            /* Unit of lock allocation to avoid   */
109                                        /*   false sharing of locks.          */
110
111  /* L1 Cache variables */
112  unsigned long CacheSize;              /* L1 Cache size in KB. This is the   */
113                                        /*   total size of the L1, whether    */
114                                        /*   combined or split                */
115  unsigned long CacheAttrib;            /* L1CACHE_TYPE                       */
116  unsigned long CacheAssoc;             /* L1 Cache associativity. Use this
117                                           for combined cache. If split, put
118                                           zeros here.                        */
119  unsigned long CacheLineSize;          /* L1 Cache line size in bytes. Use
120                                           for combined cache. If split, put
121                                           zeros here.                        */
122  /* For split L1 Cache: (= combined if combined cache) */
123  unsigned long I_CacheSize;
124  unsigned long I_CacheAssoc;
125  unsigned long I_CacheLineSize;
126  unsigned long D_CacheSize;
127  unsigned long D_CacheAssoc;
128  unsigned long D_CacheLineSize;
129
130  /* Translation Lookaside Buffer variables */
131  unsigned long TLBSize;                /* Total number of TLBs on the system */
132  unsigned long TLBAttrib;              /* Combined I+D or split TLB          */
133  unsigned long TLBAssoc;               /* TLB Associativity. Use this for
134                                           combined TLB. If split, put zeros
135                                           here.                              */
136  /* For split TLB: (= combined if combined TLB) */
137  unsigned long I_TLBSize;
138  unsigned long I_TLBAssoc;
139  unsigned long D_TLBSize;
140  unsigned long D_TLBAssoc;
141
142  unsigned long ExtendedVPD;            /* Offset to extended VPD area;
143                                           null if unused                     */
144  } VPD;
145
146typedef enum _DEVICE_FLAGS {
147  Enabled = 0x4000,                     /* 1 - PCI device is enabled          */
148  Integrated = 0x2000,
149  Failed = 0x1000,                      /* 1 - device failed POST code tests  */
150  Static = 0x0800,                      /* 0 - dynamically configurable
151                                           1 - static                         */
152  Dock = 0x0400,                        /* 0 - not a docking station device
153                                           1 - is a docking station device    */
154  Boot = 0x0200,                        /* 0 - device cannot be used for BOOT
155                                           1 - can be a BOOT device           */
156  Configurable = 0x0100,                /* 1 - device is configurable         */
157  Disableable = 0x80,                   /* 1 - device can be disabled         */
158  PowerManaged = 0x40,                  /* 0 - not managed; 1 - managed       */
159  ReadOnly = 0x20,                      /* 1 - device is read only            */
160  Removable = 0x10,                     /* 1 - device is removable            */
161  ConsoleIn = 0x08,
162  ConsoleOut = 0x04,
163  Input = 0x02,
164  Output = 0x01
165  } DEVICE_FLAGS;
166
167typedef enum _BUS_ID {
168  ISADEVICE = 0x01,
169  EISADEVICE = 0x02,
170  PCIDEVICE = 0x04,
171  PCMCIADEVICE = 0x08,
172  PNPISADEVICE = 0x10,
173  MCADEVICE = 0x20,
174  MXDEVICE = 0x40,                      /* Devices on mezzanine bus           */
175  PROCESSORDEVICE = 0x80,               /* Devices on processor bus           */
176  VMEDEVICE = 0x100,
177  } BUS_ID;
178
179typedef struct _DEVICE_ID {
180  unsigned long BusId;                  /* See BUS_ID enum above              */
181  unsigned long DevId;                  /* Big Endian format                  */
182  unsigned long SerialNum;              /* For multiple usage of a single
183                                           DevId                              */
184  unsigned long Flags;                  /* See DEVICE_FLAGS enum above        */
185  unsigned char BaseType;               /* See pnp.h for bit definitions      */
186  unsigned char SubType;                /* See pnp.h for bit definitions      */
187  unsigned char Interface;              /* See pnp.h for bit definitions      */
188  unsigned char Spare;
189  } DEVICE_ID;
190
191typedef union _BUS_ACCESS {
192  struct _PnPAccess{
193    unsigned char CSN;
194    unsigned char LogicalDevNumber;
195    unsigned short ReadDataPort;
196    } PnPAccess;
197  struct _ISAAccess{
198    unsigned char SlotNumber;           /* ISA Slot Number generally not
199                                           available; 0 if unknown            */
200    unsigned char LogicalDevNumber;
201    unsigned short ISAReserved;
202    } ISAAccess;
203  struct _MCAAccess{
204    unsigned char SlotNumber;
205    unsigned char LogicalDevNumber;
206    unsigned short MCAReserved;
207    } MCAAccess;
208  struct _PCMCIAAccess{
209    unsigned char SlotNumber;
210    unsigned char LogicalDevNumber;
211    unsigned short PCMCIAReserved;
212    } PCMCIAAccess;
213  struct _EISAAccess{
214    unsigned char SlotNumber;
215    unsigned char FunctionNumber;
216    unsigned short EISAReserved;
217    } EISAAccess;
218  struct _PCIAccess{
219    unsigned char BusNumber;
220    unsigned char DevFuncNumber;
221    unsigned short PCIReserved;
222    } PCIAccess;
223  struct _ProcBusAccess{
224    unsigned char BusNumber;
225    unsigned char BUID;
226    unsigned short ProcBusReserved;
227    } ProcBusAccess;
228  } BUS_ACCESS;
229
230/* Per logical device information */
231typedef struct _PPC_DEVICE {
232  DEVICE_ID DeviceId;
233  BUS_ACCESS BusAccess;
234
235  /* The following three are offsets into the DevicePnPHeap */
236  /* All are in PnP compressed format                       */
237  unsigned long AllocatedOffset;        /* Allocated resource description     */
238  unsigned long PossibleOffset;         /* Possible resource description      */
239  unsigned long CompatibleOffset;       /* Compatible device identifiers      */
240  } PPC_DEVICE;
241
242typedef enum _CPU_STATE {
243  CPU_GOOD = 0,                         /* CPU is present, and active         */
244  CPU_GOOD_FW = 1,                      /* CPU is present, and in firmware    */
245  CPU_OFF = 2,                          /* CPU is present, but inactive       */
246  CPU_FAILED = 3,                       /* CPU is present, but failed POST    */
247  CPU_NOT_PRESENT = 255                 /* CPU not present                    */
248  } CPU_STATE;
249
250typedef struct _PPC_CPU {
251  unsigned long CpuType;                /* Result of mfspr from Processor
252                                           Version Register (PVR).
253                                           PVR(0-15) = Version (e.g. 601)
254                                           PVR(16-31 = EC Level               */
255  unsigned char CpuNumber;              /* CPU Number for this processor      */
256  unsigned char CpuState;               /* CPU State, see CPU_STATE enum      */
257  unsigned short Reserved;
258  } PPC_CPU;
259
260typedef struct _PPC_MEM {
261  unsigned long SIMMSize;               /* 0 - absent or bad
262                                           8M, 32M (in MB)                    */
263  } PPC_MEM;
264
265typedef enum _MEM_USAGE {
266  Other = 0x8000,
267  ResumeBlock = 0x4000,                 /* for use by power management        */
268  SystemROM = 0x2000,                   /* Flash memory (populated)           */
269  UnPopSystemROM = 0x1000,              /* Unpopulated part of SystemROM area */
270  IOMemory = 0x0800,
271  SystemIO = 0x0400,
272  SystemRegs = 0x0200,
273  PCIAddr = 0x0100,
274  PCIConfig = 0x80,
275  ISAAddr = 0x40,
276  Unpopulated = 0x20,                   /* Unpopulated part of System Memory  */
277  Free = 0x10,                          /* Free part of System Memory         */
278  BootImage = 0x08,                     /* BootImage part of System Memory    */
279  FirmwareCode = 0x04,                  /* FirmwareCode part of System Memory */
280  FirmwareHeap = 0x02,                  /* FirmwareHeap part of System Memory */
281  FirmwareStack = 0x01                  /* FirmwareStack part of System Memory*/
282  } MEM_USAGE;
283
284typedef struct _MEM_MAP {
285  unsigned long Usage;                  /* See MEM_USAGE above                */
286  unsigned long BasePage;               /* Page number measured in 4KB pages  */
287  unsigned long PageCount;              /* Page count measured in 4KB pages   */
288  } MEM_MAP;
289
290typedef struct _RESIDUAL {
291  unsigned long ResidualLength;         /* Length of Residual                 */
292  unsigned char Version;                /* of this data structure             */
293  unsigned char Revision;               /* of this data structure             */
294  unsigned short EC;                    /* of this data structure             */
295  /* VPD */
296  VPD VitalProductData;
297  /* CPU */
298  unsigned short MaxNumCpus;            /* Max CPUs in this system            */
299  unsigned short ActualNumCpus;         /* ActualNumCpus < MaxNumCpus means   */
300                                        /* that there are unpopulated or      */
301                                        /* otherwise unusable cpu locations   */
302  PPC_CPU Cpus[MAX_CPUS];
303  /* Memory */
304  unsigned long TotalMemory;            /* Total amount of memory installed   */
305  unsigned long GoodMemory;             /* Total amount of good memory        */
306  unsigned long ActualNumMemSegs;
307  MEM_MAP Segs[MAX_MEM_SEGS];
308  unsigned long ActualNumMemories;
309  PPC_MEM Memories[MAX_MEMS];
310  /* Devices */
311  unsigned long ActualNumDevices;
312  PPC_DEVICE Devices[MAX_DEVICES];
313  unsigned char DevicePnPHeap[2*MAX_DEVICES*AVE_PNP_SIZE];
314  } RESIDUAL;
315
316#ifndef NULL
317#define NULL    0
318#endif
319
320extern RESIDUAL residualCopy;
321
322extern void print_residual_device_info(void);
323#ifndef __BOOT__
324extern PPC_DEVICE *residual_find_device(RESIDUAL *res, unsigned long BusMask,
325                                        unsigned char * DevID, int BaseType,
326                                        int SubType, int Interface, int n);
327#else
328extern PPC_DEVICE *residual_find_device(unsigned long BusMask,
329                                        unsigned char * DevID, int BaseType,
330                                        int SubType, int Interface, int n);
331#endif
332extern PnP_TAG_PACKET *PnP_find_packet(unsigned char *p, unsigned packet_tag,
333                                       int n);
334extern PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p,
335                                                    unsigned packet_type,
336                                                    int n);
337extern PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p,
338                                                    unsigned packet_type,
339                                                    int n);
340#endif /* ASM */
341#endif  /* ndef _RESIDUAL_ */
342
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