source: rtems/c/src/lib/libbsp/powerpc/motorola_powerpc/residual/pnp.h @ ba46ffa6

4.104.114.84.95
Last change on this file since ba46ffa6 was ba46ffa6, checked in by Joel Sherrill <joel.sherrill@…>, on 06/14/99 at 16:51:13

This is a large patch from Eric Valette <valette@…> that was
described in the message following this paragraph. This patch also includes
a mcp750 BSP.

From valette@… Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@…>
To: joel@…
Cc: raguet@…, rtems-snapshots@…, valette@…
Subject: Questions/Suggestion? regarding RTEMS PowerPC code (long)

Dear knowledgeable RTEMS powerpc users,

As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.

In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.

the MCP750 is a COMPACT PCI powerpc board with :

1) a MPC750 233 MHz processor,
2) a raven bus bridge/PCI controller that
implement an OPENPIC compliant interrupt controller,
3) a VIA 82C586 PCI/ISA bridge that offers a PC
compliant IO for keyboard, serial line, IDE, and
the well known PC 8259 cascaded PIC interrupt
architecture model,
4) a DEC 21140 Ethernet controller,
5) the PPCBUG Motorola firmware in flash,
6) A DEC PCI bridge,

This architecture is common to most Motorola 60x/7xx
board except that :

1) on VME board, the DEC PCI bridge is replaced by
a VME chipset,
2) the VIA 82C586 PCI/ISA bridge is replaced by
another bridge that is almost fully compatible
with the via bridge...

So the port should be a rather close basis for many
60x/7xx motorola board...

On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.

Now the questions/suggestions I have :

1) EXCEPTION CODE


As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :

a) Except for the decrementer exception (and
maybe some other on mpc8xx), exceptions are
not recoverable and the handler just need to print
the full context and go to the firmware or debugger...
b) The interrupt switch is only necessary for the
decrementer and external interrupt (at least on
6xx,7xx).
c) The full context for exception is never saved and
thus cannot be used by debugger... I do understand
the most important for interrupts low level code
is to save the minimal context enabling to call C
code for performance reasons. On non recoverable
exception on the other hand, the most important is
to save the maximum information concerning proc status
in order to analyze the reason of the fault. At
least we will need this in order to implement the
port of RGDB on PPC

==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)

See remark about files/directory layout organization in 4)

2) Current Implementation of ISR low level code


I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S

#if (PPC_USE_SPRG)

mfmsr r5
mfspr r6, sprg2

#else

lwz r6,msr_initial(r11)
lis r5,~PPC_MSR_DISABLE_MASK@ha
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
and r6,r6,r5
mfmsr r5

#endif

Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :

a) I want the MSR[IR] and MSR[DR] to be set for
performance reasons and also because I need DBAT
support to have access to PCI memory space as the
interrupt controller is in the PCI space.

Reading the code, I see others have the same kind of request :

/* SCE 980217

*

  • We need address translation ON when we call our ISR routine

mtmsr r5

*/

This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...

Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO
acknowledged.

I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...

So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)

I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.

3) R2/R13 manipulation for EABI implementation


I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).

So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or
handling.

The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.

=> I propose to suppress any specific code for r2 and
r13 in the EABI case.

4) Code layout organization (yes again :-))


I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.

a) exec/score/cpu/* vs lib/libcpu/cpu/*.

I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.

This include at least :

a) registers access routine (e.g GET_MSR_Value),
b) interrupt masking/unmasking routines,
c) cache_mngt_routine,
d) mmu_mngt_routine,
e) Routines to connect the raw_exception, raw_interrupt
handler,

b) lib/libcpu/cpu/powerpc/*

With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x) the directory structure
is fine (except maybe the names that are not homogeneous)

powerpc

ppc421 mpc821 ...

I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.

So, except if the support of automake provides a better solution
I would like to propose something like this :

powerpc

mpc421 mpc821 ... mpc750 shared wrapup

with the following rules :

a) "shared" would act as a source container for sources that may
be shared among processors. Needed files would be compiled inside
the processor specific directory using the vpath Makefile
mechanism. "shared" may also contain compilation code
for routine that are really shared and not worth to inline...
(did not found many things so far as registers access routine
ARE WORTH INLINING)... In the case something is compiled there,
it should create libcpushared.a

b) layout under processor specific directory is free provided
that

1)the result of the compilation process exports :

libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu

2) each processor specific directory creates
a library called libcpuspecific.a

Note that this organization enables to have a file that
is nearly the same than in shared but that must differ
because of processor differences...

c) "wrapup" should create libcpu.a using libcpushared.a
libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu

The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...

Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...

NB: I have done this for mpc750 and other processors could just use
similar Makefiles...

c) The exec/score/cpu/powerpc directory layout.

I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...

Besides that I do not understand why

1) things are compiled in the wrap directory,
2) some includes are moved to rtems/score,

I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor
directory),

5) Interrupt handling API


Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :


| OPEN | <-----|8259|
| PIC | | | 2 ------
|(RAVEN)| | | <-----|8259|
| | | | | | 11
| | | | | | <----
| | | | | |
| | | | | |


------
| VIA PCI/ISA bridge
| x
-------- PCI interrupts

OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :

1) there is no way to specify priorities among
interrupts handler. This is REALLY a bad thing.
For me it is as importnat as having priorities
for threads...
2) for my implementation, each ISR should
contain the code that acknowledge the RAVEN
and 8259 cascade, modify interrupt mask on both
chips, and reenable interrupt at processor level,
..., restore then on interrupt return,.... This code
is actually similar to code located in some
genpvec.c powerpc files,
3) I must update _ISR_Nesting_level because
irq.inl use it...
4) the libchip code connects the ISR via set_vector
but the libchip handler code does not contain any code to
manipulate external interrupt controller hardware
in order to acknoledge the interrupt or re-enable
them (except for the target hardware of course)
So this code is broken unless set_vector adds an
additionnal prologue/epilogue before calling/returning
from in order to acknoledge/mask the raven and the
8259 PICS... => Anyway already EACH BSP MUST REWRITE
PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT
SET_VECTOR.

I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :

1) Once the driver supplied methods is called the
only things the ISR has to do is to worry about the
external hardware that triggered the interrupt.
Everything on openpic/VIA/processor would have been
done by the low levels (same things as set-vector)
2) The caller will need to supply the on/off/isOn
routine that are fundamental to correctly implements
debuggers/performance monitoring is a portable way
3) A globally configurable interrupt priorities
mechanism...

I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).

Additional note : I think the _ISR_Is_in_progress()
inline routine should be :

1) Put in a processor specific section,
2) Should not rely on a global variable,

As :

a) on symmetric MP, there is one interrupt level
per CPU,
b) On processor that have an ISP (e,g 68040),
this variable is useless (MSR bit testing could
be used)
c) On PPC, instead of using the address of the
variable via CPU_IRQ_info.Nest_level a dedicated
SPR could be used.

NOTE: most of this is also true for _Thread_Dispatch_disable_level

END NOTE


Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :

1) try to better understand the actual code,
2) propose concrete ways of enhancing current code
by providing an alternative implementation for MCP750. I
will make my best effort to try to brake nothing but this
is actually hard due to the file layout organisation.
3) make understandable some changes I will probably make
if joel let me do them :-)

Any comments/objections are welcomed as usual.

--


/ ` Eric Valette

/-- o _. Canon CRF

(_, / (_(_( Rue de la touche lambert

35517 Cesson-Sevigne Cedex
FRANCE

Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30
E-mail: valette@…

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Line 
1/* 11/02/95                                                                   */
2/*----------------------------------------------------------------------------*/
3/*      Plug and Play header definitions                                      */
4/*----------------------------------------------------------------------------*/
5
6/* Structure map for PnP on PowerPC Reference Platform                        */
7/* See Plug and Play ISA Specification, Version 1.0, May 28, 1993.  It        */
8/* (or later versions) is available on Compuserve in the PLUGPLAY area.       */
9/* This code has extensions to that specification, namely new short and       */
10/* long tag types for platform dependent information                          */
11
12/* Warning: LE notation used throughout this file                             */
13
14/* For enum's: if given in hex then they are bit significant, i.e.            */
15/* only one bit is on for each enum                                           */
16
17#ifndef _PNP_
18#define _PNP_
19
20#ifndef ASM
21#define MAX_MEM_REGISTERS 9
22#define MAX_IO_PORTS 20
23#define MAX_IRQS 7
24/*#define MAX_DMA_CHANNELS 7*/
25
26/* Interrupt controllers */
27
28#define PNPinterrupt0 "PNP0000"      /* AT Interrupt Controller               */
29#define PNPinterrupt1 "PNP0001"      /* EISA Interrupt Controller             */
30#define PNPinterrupt2 "PNP0002"      /* MCA Interrupt Controller              */
31#define PNPinterrupt3 "PNP0003"      /* APIC                                  */
32#define PNPExtInt     "IBM000D"      /* PowerPC Extended Interrupt Controller */
33
34/* Timers */
35
36#define PNPtimer0     "PNP0100"      /* AT Timer                              */
37#define PNPtimer1     "PNP0101"      /* EISA Timer                            */
38#define PNPtimer2     "PNP0102"      /* MCA Timer                             */
39
40/* DMA controllers */
41
42#define PNPdma0       "PNP0200"      /* AT DMA Controller                     */
43#define PNPdma1       "PNP0201"      /* EISA DMA Controller                   */
44#define PNPdma2       "PNP0202"      /* MCA DMA Controller                    */
45
46/* start of August 15, 1994 additions */
47/* CMOS */
48#define PNPCMOS       "IBM0009"      /* CMOS                                  */
49
50/* L2 Cache */
51#define PNPL2         "IBM0007"      /* L2 Cache                              */
52
53/* NVRAM */
54#define PNPNVRAM      "IBM0008"      /* NVRAM                                 */
55
56/* Power Management */
57#define PNPPM         "IBM0005"      /* Power Management                      */
58/* end of August 15, 1994 additions */
59
60/* Keyboards */
61
62#define PNPkeyboard0  "PNP0300"      /* IBM PC/XT KB Cntlr (83 key, no mouse) */
63#define PNPkeyboard1  "PNP0301"      /* Olivetti ICO (102 key)                */
64#define PNPkeyboard2  "PNP0302"      /* IBM PC/AT KB Cntlr (84 key)           */
65#define PNPkeyboard3  "PNP0303"      /* IBM Enhanced (101/2 key, PS/2 mouse)  */
66#define PNPkeyboard4  "PNP0304"      /* Nokia 1050 KB Cntlr                   */
67#define PNPkeyboard5  "PNP0305"      /* Nokia 9140 KB Cntlr                   */
68#define PNPkeyboard6  "PNP0306"      /* Standard Japanese KB Cntlr            */
69#define PNPkeyboard7  "PNP0307"      /* Microsoft Windows (R) KB Cntlr        */
70
71/* Parallel port controllers */
72
73#define PNPparallel0 "PNP0400"       /* Standard LPT Parallel Port            */
74#define PNPparallel1 "PNP0401"       /* ECP Parallel Port                     */
75#define PNPepp       "IBM001C"       /* EPP Parallel Port                     */
76
77/* Serial port controllers */
78
79#define PNPserial0   "PNP0500"       /* Standard PC Serial port               */
80#define PNPSerial1   "PNP0501"       /* 16550A Compatible Serial port         */
81
82/* Disk controllers */
83
84#define PNPdisk0     "PNP0600"       /* Generic ESDI/IDE/ATA Compat HD Cntlr  */
85#define PNPdisk1     "PNP0601"       /* Plus Hardcard II                      */
86#define PNPdisk2     "PNP0602"       /* Plus Hardcard IIXL/EZ                 */
87
88/* Diskette controllers */
89
90#define PNPdiskette0 "PNP0700"       /* PC Standard Floppy Disk Controller    */
91
92/* Display controllers */
93
94#define PNPdisplay0  "PNP0900"       /* VGA Compatible                        */
95#define PNPdisplay1  "PNP0901"       /* Video Seven VGA                       */
96#define PNPdisplay2  "PNP0902"       /* 8514/A Compatible                     */
97#define PNPdisplay3  "PNP0903"       /* Trident VGA                           */
98#define PNPdisplay4  "PNP0904"       /* Cirrus Logic Laptop VGA               */
99#define PNPdisplay5  "PNP0905"       /* Cirrus Logic VGA                      */
100#define PNPdisplay6  "PNP0906"       /* Tseng ET4000 or ET4000/W32            */
101#define PNPdisplay7  "PNP0907"       /* Western Digital VGA                   */
102#define PNPdisplay8  "PNP0908"       /* Western Digital Laptop VGA            */
103#define PNPdisplay9  "PNP0909"       /* S3                                    */
104#define PNPdisplayA  "PNP090A"       /* ATI Ultra Pro/Plus (Mach 32)          */
105#define PNPdisplayB  "PNP090B"       /* ATI Ultra (Mach 8)                    */
106#define PNPdisplayC  "PNP090C"       /* XGA Compatible                        */
107#define PNPdisplayD  "PNP090D"       /* ATI VGA Wonder                        */
108#define PNPdisplayE  "PNP090E"       /* Weitek P9000 Graphics Adapter         */
109#define PNPdisplayF  "PNP090F"       /* Oak Technology VGA                    */
110
111/* Peripheral busses */
112
113#define PNPbuses0    "PNP0A00"       /* ISA Bus                               */
114#define PNPbuses1    "PNP0A01"       /* EISA Bus                              */
115#define PNPbuses2    "PNP0A02"       /* MCA Bus                               */
116#define PNPbuses3    "PNP0A03"       /* PCI Bus                               */
117#define PNPbuses4    "PNP0A04"       /* VESA/VL Bus                           */
118
119/* RTC, BIOS, planar devices */
120
121#define PNPspeaker0  "PNP0800"       /* AT Style Speaker Sound                */
122#define PNPrtc0      "PNP0B00"       /* AT RTC                                */
123#define PNPpnpbios0  "PNP0C00"       /* PNP BIOS (only created by root enum)  */
124#define PNPpnpbios1  "PNP0C01"       /* System Board Memory Device            */
125#define PNPpnpbios2  "PNP0C02"       /* Math Coprocessor                      */
126#define PNPpnpbios3  "PNP0C03"       /* PNP BIOS Event Notification Interrupt */
127
128/* PCMCIA controller */
129
130#define PNPpcmcia0   "PNP0E00"       /* Intel 82365 Compatible PCMCIA Cntlr   */
131
132/* Mice */
133
134#define PNPmouse0    "PNP0F00"       /* Microsoft Bus Mouse                   */
135#define PNPmouse1    "PNP0F01"       /* Microsoft Serial Mouse                */
136#define PNPmouse2    "PNP0F02"       /* Microsoft Inport Mouse                */
137#define PNPmouse3    "PNP0F03"       /* Microsoft PS/2 Mouse                  */
138#define PNPmouse4    "PNP0F04"       /* Mousesystems Mouse                    */
139#define PNPmouse5    "PNP0F05"       /* Mousesystems 3 Button Mouse - COM2    */
140#define PNPmouse6    "PNP0F06"       /* Genius Mouse - COM1                   */
141#define PNPmouse7    "PNP0F07"       /* Genius Mouse - COM2                   */
142#define PNPmouse8    "PNP0F08"       /* Logitech Serial Mouse                 */
143#define PNPmouse9    "PNP0F09"       /* Microsoft Ballpoint Serial Mouse      */
144#define PNPmouseA    "PNP0F0A"       /* Microsoft PNP Mouse                   */
145#define PNPmouseB    "PNP0F0B"       /* Microsoft PNP Ballpoint Mouse         */
146
147/* Modems */
148
149#define PNPmodem0    "PNP9000"       /* Specific IDs TBD                      */
150
151/* Network controllers */
152
153#define PNPnetworkC9 "PNP80C9"       /* IBM Token Ring                        */
154#define PNPnetworkCA "PNP80CA"       /* IBM Token Ring II                     */
155#define PNPnetworkCB "PNP80CB"       /* IBM Token Ring II/Short               */
156#define PNPnetworkCC "PNP80CC"       /* IBM Token Ring 4/16Mbs                */
157#define PNPnetwork27 "PNP8327"       /* IBM Token Ring (All types)            */
158#define PNPnetworket "IBM0010"       /* IBM Ethernet used by Power PC         */
159#define PNPneteisaet "IBM2001"       /* IBM Ethernet EISA adapter             */
160#define PNPAMD79C970 "IBM0016"       /* AMD 79C970 (PCI Ethernet)             */
161
162/* SCSI controllers */
163
164#define PNPscsi0     "PNPA000"       /* Adaptec 154x Compatible SCSI Cntlr    */
165#define PNPscsi1     "PNPA001"       /* Adaptec 174x Compatible SCSI Cntlr    */
166#define PNPscsi2     "PNPA002"       /* Future Domain 16-700 Compat SCSI Cntlr*/
167#define PNPscsi3     "PNPA003"       /* Panasonic CDROM Adapter (SBPro/SB16)  */
168#define PNPscsiF     "IBM000F"       /* NCR 810 SCSI Controller               */
169#define PNPscsi825   "IBM001B"       /* NCR 825 SCSI Controller               */
170#define PNPscsi875   "IBM0018"       /* NCR 875 SCSI Controller               */
171
172/* Sound/Video, Multimedia */
173
174#define PNPmm0       "PNPB000"       /* Sound Blaster Compatible Sound Device */
175#define PNPmm1       "PNPB001"       /* MS Windows Sound System Compat Device */
176#define PNPmmF       "IBM000E"       /* Crystal CS4231 Audio Device           */
177#define PNPv7310     "IBM0015"       /* ASCII V7310 Video Capture Device      */
178#define PNPmm4232    "IBM0017"       /* Crystal CS4232 Audio Device           */
179#define PNPpmsyn     "IBM001D"       /* YMF 289B chip (Yamaha)                */
180#define PNPgp4232    "IBM0012"       /* Crystal CS4232 Game Port              */
181#define PNPmidi4232  "IBM0013"       /* Crystal CS4232 MIDI                   */
182
183/* Operator Panel */
184#define PNPopctl     "IBM000B"       /* Operator's panel                      */
185
186/* Service Processor */
187#define PNPsp        "IBM0011"       /* IBM Service Processor                 */
188#define PNPLTsp      "IBM001E"       /* Lightning/Terlingua Support Processor */
189#define PNPLTmsp     "IBM001F"       /* Lightning/Terlingua Mini-SP           */
190
191/* Memory Controller */
192#define PNPmemctl    "IBM000A"       /* Memory controller                     */
193
194/* Graphics Assist */
195#define PNPg_assist  "IBM0014"       /* Graphics Assist                       */
196
197/* Miscellaneous Device Controllers */
198#define PNPtablet    "IBM0019"       /* IBM Tablet Controller                 */
199
200/* PNP Packet Handles */
201
202#define S1_Packet                0x0A   /* Version resource                   */
203#define S2_Packet                0x15   /* Logical DEVID (without flags)      */
204#define S2_Packet_flags          0x16   /* Logical DEVID (with flags)         */
205#define S3_Packet                0x1C   /* Compatible device ID               */
206#define S4_Packet                0x22   /* IRQ resource (without flags)       */
207#define S4_Packet_flags          0x23   /* IRQ resource (with flags)          */
208#define S5_Packet                0x2A   /* DMA resource                       */
209#define S6_Packet                0x30   /* Depend funct start (w/o priority)  */
210#define S6_Packet_priority       0x31   /* Depend funct start (w/ priority)   */
211#define S7_Packet                0x38   /* Depend funct end                   */
212#define S8_Packet                0x47   /* I/O port resource (w/o fixed loc)  */
213#define S9_Packet_fixed          0x4B   /* I/O port resource (w/ fixed loc)   */
214#define S14_Packet               0x71   /* Vendor defined                     */
215#define S15_Packet               0x78   /* End of resource (w/o checksum)     */
216#define S15_Packet_checksum      0x79   /* End of resource (w/ checksum)      */
217#define L1_Packet                0x81   /* Memory range                       */
218#define L1_Shadow                0x20   /* Memory is shadowable               */
219#define L1_32bit_mem             0x18   /* 32-bit memory only                 */
220#define L1_8_16bit_mem           0x10   /* 8- and 16-bit supported            */
221#define L1_Decode_Hi             0x04   /* decode supports high address       */
222#define L1_Cache                 0x02   /* read cacheable, write-through      */
223#define L1_Writeable             0x01   /* Memory is writeable                */
224#define L2_Packet                0x82   /* ANSI ID string                     */
225#define L3_Packet                0x83   /* Unicode ID string                  */
226#define L4_Packet                0x84   /* Vendor defined                     */
227#define L5_Packet                0x85   /* Large I/O                          */
228#define L6_Packet                0x86   /* 32-bit Fixed Loc Mem Range Desc    */
229#define END_TAG                  0x78   /* End of resource                    */
230#define DF_START_TAG             0x30   /* Dependent function start           */
231#define DF_START_TAG_priority    0x31   /* Dependent function start           */
232#define DF_END_TAG               0x38   /* Dependent function end             */
233#define SUBOPTIMAL_CONFIGURATION 0x2    /* Priority byte sub optimal config   */
234
235/* Device Base Type Codes */
236
237typedef enum _PnP_BASE_TYPE {
238  Reserved = 0,
239  MassStorageDevice = 1,
240  NetworkInterfaceController = 2,
241  DisplayController = 3,
242  MultimediaController = 4,
243  MemoryController = 5,
244  BridgeController = 6,
245  CommunicationsDevice = 7,
246  SystemPeripheral = 8,
247  InputDevice = 9,
248  ServiceProcessor = 0x0A,              /* 11/2/95                            */
249  } PnP_BASE_TYPE;
250
251/* Device Sub Type Codes */
252
253typedef enum _PnP_SUB_TYPE {
254  SCSIController = 0,
255  IDEController = 1,
256  FloppyController = 2,
257  IPIController = 3,
258  OtherMassStorageController = 0x80,
259
260  EthernetController = 0,
261  TokenRingController = 1,
262  FDDIController = 2,
263  OtherNetworkController = 0x80,
264
265  VGAController= 0,
266  SVGAController= 1,
267  XGAController= 2,
268  OtherDisplayController = 0x80,
269
270  VideoController = 0,
271  AudioController = 1,
272  OtherMultimediaController = 0x80,
273
274  RAM = 0,
275  FLASH = 1,
276  OtherMemoryDevice = 0x80,
277
278  HostProcessorBridge = 0,
279  ISABridge = 1,
280  EISABridge = 2,
281  MicroChannelBridge = 3,
282  PCIBridge = 4,
283  PCMCIABridge = 5,
284  VMEBridge = 6,
285  OtherBridgeDevice = 0x80,
286
287  RS232Device = 0,
288  ATCompatibleParallelPort = 1,
289  OtherCommunicationsDevice = 0x80,
290
291  ProgrammableInterruptController = 0,
292  DMAController = 1,
293  SystemTimer = 2,
294  RealTimeClock = 3,
295  L2Cache = 4,
296  NVRAM = 5,
297  PowerManagement = 6,
298  CMOS = 7,
299  OperatorPanel = 8,
300  ServiceProcessorClass1 = 9,
301  ServiceProcessorClass2 = 0xA,
302  ServiceProcessorClass3 = 0xB,
303  GraphicAssist = 0xC,
304  SystemPlanar = 0xF,                   /* 10/5/95                            */
305  OtherSystemPeripheral = 0x80,
306
307  KeyboardController = 0,
308  Digitizer = 1,
309  MouseController = 2,
310  TabletController = 3,                 /* 10/27/95                           */
311  OtherInputController = 0x80,
312
313  GeneralMemoryController = 0,
314  } PnP_SUB_TYPE;
315
316/* Device Interface Type Codes */
317
318typedef enum _PnP_INTERFACE {
319  General = 0,
320  GeneralSCSI = 0,
321  GeneralIDE = 0,
322  ATACompatible = 1,
323
324  GeneralFloppy = 0,
325  Compatible765 = 1,
326  NS398_Floppy = 2,                     /* NS Super I/O wired to use index
327                                           register at port 398 and data
328                                           register at port 399               */
329  NS26E_Floppy = 3,                     /* Ports 26E and 26F                  */
330  NS15C_Floppy = 4,                     /* Ports 15C and 15D                  */
331  NS2E_Floppy = 5,                      /* Ports 2E and 2F                    */
332  CHRP_Floppy = 6,                      /* CHRP Floppy in PR*P system         */
333
334  GeneralIPI = 0,
335
336  GeneralEther = 0,
337  GeneralToken = 0,
338  GeneralFDDI = 0,
339
340  GeneralVGA = 0,
341  GeneralSVGA = 0,
342  GeneralXGA = 0,
343
344  GeneralVideo = 0,
345  GeneralAudio = 0,
346  CS4232Audio = 1,                      /* CS 4232 Plug 'n Play Configured    */
347
348  GeneralRAM = 0,
349  GeneralFLASH = 0,
350  PCIMemoryController = 0,              /* PCI Config Method                  */
351  RS6KMemoryController = 1,             /* RS6K Config Method                 */
352
353  GeneralHostBridge = 0,
354  GeneralISABridge = 0,
355  GeneralEISABridge = 0,
356  GeneralMCABridge = 0,
357  GeneralPCIBridge = 0,
358  PCIBridgeDirect = 0,
359  PCIBridgeIndirect = 1,
360  PCIBridgeRS6K = 2,
361  GeneralPCMCIABridge = 0,
362  GeneralVMEBridge = 0,
363
364  GeneralRS232 = 0,
365  COMx = 1,
366  Compatible16450 = 2,
367  Compatible16550 = 3,
368  NS398SerPort = 4,                     /* NS Super I/O wired to use index
369                                           register at port 398 and data
370                                           register at port 399               */
371  NS26ESerPort = 5,                     /* Ports 26E and 26F                  */
372  NS15CSerPort = 6,                     /* Ports 15C and 15D                  */
373  NS2ESerPort = 7,                      /* Ports 2E and 2F                    */
374
375  GeneralParPort = 0,
376  LPTx = 1,
377  NS398ParPort = 2,                     /* NS Super I/O wired to use index
378                                           register at port 398 and data
379                                           register at port 399               */
380  NS26EParPort = 3,                     /* Ports 26E and 26F                  */
381  NS15CParPort = 4,                     /* Ports 15C and 15D                  */
382  NS2EParPort = 5,                      /* Ports 2E and 2F                    */
383
384  GeneralPIC = 0,
385  ISA_PIC = 1,
386  EISA_PIC = 2,
387  MPIC = 3,
388  RS6K_PIC = 4,
389
390  GeneralDMA = 0,
391  ISA_DMA = 1,
392  EISA_DMA = 2,
393
394  GeneralTimer = 0,
395  ISA_Timer = 1,
396  EISA_Timer = 2,
397  GeneralRTC = 0,
398  ISA_RTC = 1,
399
400  StoreThruOnly = 1,
401  StoreInEnabled = 2,
402  RS6KL2Cache = 3,
403
404  IndirectNVRAM = 0,                    /* Indirectly addressed               */
405  DirectNVRAM = 1,                      /* Memory Mapped                      */
406  IndirectNVRAM24 = 2,                  /* Indirectly addressed - 24 bit      */
407
408  GeneralPowerManagement = 0,
409  EPOWPowerManagement = 1,
410  PowerControl = 2,                    /* d1378                               */
411
412  GeneralCMOS = 0,
413
414  GeneralOPPanel = 0,
415  HarddiskLight = 1,
416  CDROMLight = 2,
417  PowerLight = 3,
418  KeyLock = 4,
419  ANDisplay = 5,                        /* AlphaNumeric Display               */
420  SystemStatusLED = 6,                  /* 3 digit 7 segment LED              */
421  CHRP_SystemStatusLED = 7,             /* CHRP LEDs in PR*P system           */
422
423  GeneralServiceProcessor = 0,
424
425  TransferData = 1,
426  IGMC32 = 2,
427  IGMC64 = 3,
428
429  GeneralSystemPlanar = 0,              /* 10/5/95                            */
430
431  } PnP_INTERFACE;
432
433/* PnP resources */
434
435/* Compressed ASCII is 5 bits per char; 00001=A ... 11010=Z */
436
437typedef struct _SERIAL_ID {
438  unsigned char VendorID0;              /*    Bit(7)=0                        */
439                                        /*    Bits(6:2)=1st character in      */
440                                        /*       compressed ASCII             */
441                                        /*    Bits(1:0)=2nd character in      */
442                                        /*       compressed ASCII bits(4:3)   */
443  unsigned char VendorID1;              /*    Bits(7:5)=2nd character in      */
444                                        /*       compressed ASCII bits(2:0)   */
445                                        /*    Bits(4:0)=3rd character in      */
446                                        /*       compressed ASCII             */
447  unsigned char VendorID2;              /* Product number - vendor assigned   */
448  unsigned char VendorID3;              /* Product number - vendor assigned   */
449
450/* Serial number is to provide uniqueness if more than one board of same      */
451/* type is in system.  Must be "FFFFFFFF" if feature not supported.           */
452
453  unsigned char Serial0;                /* Unique serial number bits (7:0)    */
454  unsigned char Serial1;                /* Unique serial number bits (15:8)   */
455  unsigned char Serial2;                /* Unique serial number bits (23:16)  */
456  unsigned char Serial3;                /* Unique serial number bits (31:24)  */
457  unsigned char Checksum;
458  } SERIAL_ID;
459
460typedef enum _PnPItemName {
461  Unused = 0,
462  PnPVersion = 1,
463  LogicalDevice = 2,
464  CompatibleDevice = 3,
465  IRQFormat = 4,
466  DMAFormat = 5,
467  StartDepFunc = 6,
468  EndDepFunc = 7,
469  IOPort = 8,
470  FixedIOPort = 9,
471  Res1 = 10,
472  Res2 = 11,
473  Res3 = 12,
474  SmallVendorItem = 14,
475  EndTag = 15,
476  MemoryRange = 1,
477  ANSIIdentifier = 2,
478  UnicodeIdentifier = 3,
479  LargeVendorItem = 4,
480  MemoryRange32 = 5,
481  MemoryRangeFixed32 = 6,
482  } PnPItemName;
483
484/* Define a bunch of access functions for the bits in the tag field */
485
486/* Tag type - 0 = small; 1 = large */
487#define tag_type(t) (((t) & 0x80)>>7)
488#define set_tag_type(t,v) (t = (t & 0x7f) | ((v)<<7))
489
490/* Small item name is 4 bits - one of PnPItemName enum above */
491#define tag_small_item_name(t) (((t) & 0x78)>>3)
492#define set_tag_small_item_name(t,v) (t = (t & 0x07) | ((v)<<3))
493
494/* Small item count is 3 bits - count of further bytes in packet */
495#define tag_small_count(t) ((t) & 0x07)
496#define set_tag_count(t,v) (t = (t & 0x78) | (v))
497
498/* Large item name is 7 bits - one of PnPItemName enum above */
499#define tag_large_item_name(t) ((t) & 0x7f)
500#define set_tag_large_item_name(t,v) (t = (t | 0x80) | (v))
501
502/* a PnP resource is a bunch of contiguous TAG packets ending with an end tag */
503
504typedef union _PnP_TAG_PACKET {
505  struct _S1_Pack{                      /* VERSION PACKET                     */
506    unsigned char Tag;                  /* small tag = 0x0a                   */
507    unsigned char Version[2];           /* PnP version, Vendor version        */
508    } S1_Pack;
509
510  struct _S2_Pack{                      /* LOGICAL DEVICE ID PACKET           */
511    unsigned char Tag;                  /* small tag = 0x15 or 0x16           */
512    unsigned char DevId[4];             /* Logical device id                  */
513    unsigned char Flags[2];             /* bit(0) boot device;                */
514                                        /* bit(7:1) cmd in range x31-x37      */
515                                        /* bit(7:0) cmd in range x28-x3f (opt)*/
516    } S2_Pack;
517
518  struct _S3_Pack{                      /* COMPATIBLE DEVICE ID PACKET        */
519    unsigned char Tag;                  /* small tag = 0x1c                   */
520    unsigned char CompatId[4];          /* Compatible device id               */
521    } S3_Pack;
522
523  struct _S4_Pack{                      /* IRQ PACKET                         */
524    unsigned char Tag;                  /* small tag = 0x22 or 0x23           */
525    unsigned char IRQMask[2];           /* bit(0) is IRQ0, ...;               */
526                                        /* bit(0) is IRQ8 ...                 */
527    unsigned char IRQInfo;              /* optional; assume bit(0)=1; else    */
528                                        /*  bit(0) - high true edge sensitive */
529                                        /*  bit(1) - low true edge sensitive  */
530                                        /*  bit(2) - high true level sensitive*/
531                                        /*  bit(3) - low true level sensitive */
532                                        /*  bit(7:4) - must be 0              */
533    } S4_Pack;
534
535  struct _S5_Pack{                      /* DMA PACKET                         */
536    unsigned char Tag;                  /* small tag = 0x2a                   */
537    unsigned char DMAMask;              /* bit(0) is channel 0 ...            */
538    unsigned char DMAInfo;
539    } S5_Pack;
540
541  struct _S6_Pack{                      /* START DEPENDENT FUNCTION PACKET    */
542    unsigned char Tag;                  /* small tag = 0x30 or 0x31           */
543    unsigned char Priority;             /* Optional; if missing then x01; else*/
544                                        /*  x00 = best possible               */
545                                        /*  x01 = acceptible                  */
546                                        /*  x02 = sub-optimal but functional  */
547    } S6_Pack;
548
549  struct _S7_Pack{                      /* END DEPENDENT FUNCTION PACKET      */
550    unsigned char Tag;                  /* small tag = 0x38                   */
551    } S7_Pack;
552
553  struct _S8_Pack{                      /* VARIABLE I/O PORT PACKET           */
554    unsigned char Tag;                  /* small tag x47                      */
555    unsigned char IOInfo;               /* x0  = decode only bits(9:0);       */
556#define  ISAAddr16bit         0x01      /* x01 = decode bits(15:0)            */
557    unsigned char RangeMin[2];          /* Min base address                   */
558    unsigned char RangeMax[2];          /* Max base address                   */
559    unsigned char IOAlign;              /* base alignmt, incr in 1B blocks    */
560    unsigned char IONum;                /* number of contiguous I/O ports     */
561    } S8_Pack;
562
563  struct _S9_Pack{                      /* FIXED I/O PORT PACKET              */
564    unsigned char Tag;                  /* small tag = 0x4b                   */
565    unsigned char Range[2];             /* base address 10 bits               */
566    unsigned char IONum;                /* number of contiguous I/O ports     */
567    } S9_Pack;
568
569  struct _S14_Pack{                     /* VENDOR DEFINED PACKET              */
570    unsigned char Tag;                  /* small tag = 0x7m m = 1-7           */
571    union _S14_Data{
572      unsigned char Data[7];            /* Vendor defined                     */
573      struct _S14_PPCPack{              /* Pr*p s14 pack                      */
574         unsigned char Type;            /* 00=non-IBM                         */
575         unsigned char PPCData[6];      /* Vendor defined                     */
576        } S14_PPCPack;
577      } S14_Data;
578    } S14_Pack;
579
580  struct _S15_Pack{                     /* END PACKET                         */
581    unsigned char Tag;                  /* small tag = 0x78 or 0x79           */
582    unsigned char Check;                /* optional - checksum                */
583    } S15_Pack;
584
585  struct _L1_Pack{                      /* MEMORY RANGE PACKET                */
586    unsigned char Tag;                  /* large tag = 0x81                   */
587    unsigned char Count0;               /* x09                                */
588    unsigned char Count1;               /* x00                                */
589    unsigned char Data[9];              /* a variable array of bytes,         */
590                                        /* count in tag                       */
591    } L1_Pack;
592
593  struct _L2_Pack{                      /* ANSI ID STRING PACKET              */
594    unsigned char Tag;                  /* large tag = 0x82                   */
595    unsigned char Count0;               /* Length of string                   */
596    unsigned char Count1;
597    unsigned char Identifier[1];        /* a variable array of bytes,         */
598                                        /* count in tag                       */
599    } L2_Pack;
600
601  struct _L3_Pack{                      /* UNICODE ID STRING PACKET           */
602    unsigned char Tag;                  /* large tag = 0x83                   */
603    unsigned char Count0;               /* Length + 2 of string               */
604    unsigned char Count1;
605    unsigned char Country0;             /* TBD                                */
606    unsigned char Country1;             /* TBD                                */
607    unsigned char Identifier[1];        /* a variable array of bytes,         */
608                                        /* count in tag                       */
609    } L3_Pack;
610
611  struct _L4_Pack{                      /* VENDOR DEFINED PACKET              */
612    unsigned char Tag;                  /* large tag = 0x84                   */
613    unsigned char Count0;
614    unsigned char Count1;
615    union _L4_Data{
616      unsigned char Data[1];            /* a variable array of bytes,         */
617                                        /* count in tag                       */
618      struct _L4_PPCPack{               /* Pr*p L4 packet                     */
619         unsigned char Type;            /* 00=non-IBM                         */
620         unsigned char PPCData[1];      /* a variable array of bytes,         */
621                                        /* count in tag                       */
622        } L4_PPCPack;
623      } L4_Data;
624    } L4_Pack;
625
626  struct _L5_Pack{
627    unsigned char Tag;                  /* large tag = 0x85                   */
628    unsigned char Count0;               /* Count = 17                         */
629    unsigned char Count1;
630    unsigned char Data[17];
631    } L5_Pack;
632
633  struct _L6_Pack{
634    unsigned char Tag;                  /* large tag = 0x86                   */
635    unsigned char Count0;               /* Count = 9                          */
636    unsigned char Count1;
637    unsigned char Data[9];
638    } L6_Pack;
639
640  } PnP_TAG_PACKET;
641
642#endif /* ASM */
643#endif  /* ndef _PNP_ */
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