source: rtems/c/src/lib/libbsp/powerpc/motorola_powerpc/openpic/openpic.h @ ba46ffa6
Last change on this file since ba46ffa6 was ba46ffa6, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 14, 1999 at 4:51:13 PM

This is a large patch from Eric Valette <valette@…> that was
described in the message following this paragraph. This patch also includes
a mcp750 BSP.

From valette@… Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@…>
To: joel@…
Cc: raguet@…, rtems-snapshots@…, valette@…
Subject: Questions/Suggestion? regarding RTEMS PowerPC code (long)

Dear knowledgeable RTEMS powerpc users,

As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.

In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.

the MCP750 is a COMPACT PCI powerpc board with :

1) a MPC750 233 MHz processor,
2) a raven bus bridge/PCI controller that
implement an OPENPIC compliant interrupt controller,
3) a VIA 82C586 PCI/ISA bridge that offers a PC
compliant IO for keyboard, serial line, IDE, and
the well known PC 8259 cascaded PIC interrupt
architecture model,
4) a DEC 21140 Ethernet controller,
5) the PPCBUG Motorola firmware in flash,
6) A DEC PCI bridge,

This architecture is common to most Motorola 60x/7xx
board except that :

1) on VME board, the DEC PCI bridge is replaced by
a VME chipset,
2) the VIA 82C586 PCI/ISA bridge is replaced by
another bridge that is almost fully compatible
with the via bridge...

So the port should be a rather close basis for many
60x/7xx motorola board...

On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.

Now the questions/suggestions I have :


As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :

a) Except for the decrementer exception (and
maybe some other on mpc8xx), exceptions are
not recoverable and the handler just need to print
the full context and go to the firmware or debugger...
b) The interrupt switch is only necessary for the
decrementer and external interrupt (at least on
c) The full context for exception is never saved and
thus cannot be used by debugger... I do understand
the most important for interrupts low level code
is to save the minimal context enabling to call C
code for performance reasons. On non recoverable
exception on the other hand, the most important is
to save the maximum information concerning proc status
in order to analyze the reason of the fault. At
least we will need this in order to implement the
port of RGDB on PPC

==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)

See remark about files/directory layout organization in 4)

2) Current Implementation of ISR low level code

I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S


mfmsr r5
mfspr r6, sprg2


lwz r6,msr_initial(r11)
and r6,r6,r5
mfmsr r5


Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :

a) I want the MSR[IR] and MSR[DR] to be set for
performance reasons and also because I need DBAT
support to have access to PCI memory space as the
interrupt controller is in the PCI space.

Reading the code, I see others have the same kind of request :

/* SCE 980217


  • We need address translation ON when we call our ISR routine

mtmsr r5


This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...

Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO

I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...

So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)

I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.

3) R2/R13 manipulation for EABI implementation

I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).

So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or

The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.

=> I propose to suppress any specific code for r2 and
r13 in the EABI case.

4) Code layout organization (yes again :-))

I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.

a) exec/score/cpu/* vs lib/libcpu/cpu/*.

I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.

This include at least :

a) registers access routine (e.g GET_MSR_Value),
b) interrupt masking/unmasking routines,
c) cache_mngt_routine,
d) mmu_mngt_routine,
e) Routines to connect the raw_exception, raw_interrupt

b) lib/libcpu/cpu/powerpc/*

With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x) the directory structure
is fine (except maybe the names that are not homogeneous)


ppc421 mpc821 ...

I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.

So, except if the support of automake provides a better solution
I would like to propose something like this :


mpc421 mpc821 ... mpc750 shared wrapup

with the following rules :

a) "shared" would act as a source container for sources that may
be shared among processors. Needed files would be compiled inside
the processor specific directory using the vpath Makefile
mechanism. "shared" may also contain compilation code
for routine that are really shared and not worth to inline...
(did not found many things so far as registers access routine
ARE WORTH INLINING)... In the case something is compiled there,
it should create libcpushared.a

b) layout under processor specific directory is free provided

1)the result of the compilation process exports :

libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu

2) each processor specific directory creates
a library called libcpuspecific.a

Note that this organization enables to have a file that
is nearly the same than in shared but that must differ
because of processor differences...

c) "wrapup" should create libcpu.a using libcpushared.a
libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu

The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...

Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...

NB: I have done this for mpc750 and other processors could just use
similar Makefiles...

c) The exec/score/cpu/powerpc directory layout.

I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...

Besides that I do not understand why

1) things are compiled in the wrap directory,
2) some includes are moved to rtems/score,

I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor

5) Interrupt handling API

Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :

| OPEN | <-----|8259|
| PIC | | | 2 ------
|(RAVEN)| | | <-----|8259|
| | | | | | 11
| | | | | | <----
| | | | | |
| | | | | |

| VIA PCI/ISA bridge
| x
-------- PCI interrupts

OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :

1) there is no way to specify priorities among
interrupts handler. This is REALLY a bad thing.
For me it is as importnat as having priorities
for threads...
2) for my implementation, each ISR should
contain the code that acknowledge the RAVEN
and 8259 cascade, modify interrupt mask on both
chips, and reenable interrupt at processor level,
..., restore then on interrupt return,.... This code
is actually similar to code located in some
genpvec.c powerpc files,
3) I must update _ISR_Nesting_level because
irq.inl use it...
4) the libchip code connects the ISR via set_vector
but the libchip handler code does not contain any code to
manipulate external interrupt controller hardware
in order to acknoledge the interrupt or re-enable
them (except for the target hardware of course)
So this code is broken unless set_vector adds an
additionnal prologue/epilogue before calling/returning
from in order to acknoledge/mask the raven and the
8259 PICS... => Anyway already EACH BSP MUST REWRITE

I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :

1) Once the driver supplied methods is called the
only things the ISR has to do is to worry about the
external hardware that triggered the interrupt.
Everything on openpic/VIA/processor would have been
done by the low levels (same things as set-vector)
2) The caller will need to supply the on/off/isOn
routine that are fundamental to correctly implements
debuggers/performance monitoring is a portable way
3) A globally configurable interrupt priorities

I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).

Additional note : I think the _ISR_Is_in_progress()
inline routine should be :

1) Put in a processor specific section,
2) Should not rely on a global variable,

As :

a) on symmetric MP, there is one interrupt level
per CPU,
b) On processor that have an ISP (e,g 68040),
this variable is useless (MSR bit testing could
be used)
c) On PPC, instead of using the address of the
variable via CPU_IRQ_info.Nest_level a dedicated
SPR could be used.

NOTE: most of this is also true for _Thread_Dispatch_disable_level


Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :

1) try to better understand the actual code,
2) propose concrete ways of enhancing current code
by providing an alternative implementation for MCP750. I
will make my best effort to try to brake nothing but this
is actually hard due to the file layout organisation.
3) make understandable some changes I will probably make
if joel let me do them :-)

Any comments/objections are welcomed as usual.


/ ` Eric Valette

/-- o _. Canon CRF

(_, / (_(_( Rue de la touche lambert

35517 Cesson-Sevigne Cedex

Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30
E-mail: valette@…

  • Property mode set to 100644
File size: 8.6 KB
2 *  linux/openpic.h -- OpenPIC definitions
3 *
4 *  Copyright (C) 1997 Geert Uytterhoeven
5 *
6 *  This file is based on the following documentation:
7 *
8 *      The Open Programmable Interrupt Controller (PIC)
9 *      Register Interface Specification Revision 1.2
10 *
11 *      Issue Date: October 1995
12 *
13 *      Issued jointly by Advanced Micro Devices and Cyrix Corporation
14 *
15 *      AMD is a registered trademark of Advanced Micro Devices, Inc.
16 *      Copyright (C) 1995, Advanced Micro Devices, Inc. and Cyrix, Inc.
17 *      All Rights Reserved.
18 *
19 *  To receive a copy of this documentation, send an email to
20 *
21 *  This file is subject to the terms and conditions of the GNU General Public
22 *  License.  See the file COPYING in the main directory of this archive
23 *  for more details.
24 */
26#ifndef _RTEMS_OPENPIC_H
27#define _RTEMS_OPENPIC_H
30    /*
31     *  OpenPIC supports up to 2048 interrupt sources and up to 32 processors
32     */
34#define OPENPIC_MAX_SOURCES     2048
37#define OPENPIC_NUM_TIMERS      4
38#define OPENPIC_NUM_IPI         4
39#define OPENPIC_NUM_PRI         16
40#define OPENPIC_NUM_VECTORS     256
43    /*
44     *  Vector numbers
45     */
47#define OPENPIC_VEC_SOURCE      0x10    /* and up */
48#define OPENPIC_VEC_TIMER       0x40    /* and up */
49#define OPENPIC_VEC_IPI         0x50    /* and up */
50#define OPENPIC_VEC_SPURIOUS    99
53    /*
54     *  OpenPIC Registers are 32 bits and aligned on 128 bit boundaries
55     */
57typedef struct _OpenPIC_Reg {
58    unsigned int Reg;                                   /* Little endian! */
59    char Pad[0xc];
60} OpenPIC_Reg;
63    /*
64     *  Per Processor Registers
65     */
67typedef struct _OpenPIC_Processor {
68    /*
69     *  Private Shadow Registers (for SLiC backwards compatibility)
70     */
71    unsigned int IPI0_Dispatch_Shadow;                  /* Write Only */
72    char Pad1[0x4];
73    unsigned int IPI0_Vector_Priority_Shadow;           /* Read/Write */
74    char Pad2[0x34];
75    /*
76     *  Interprocessor Interrupt Command Ports
77     */
78    OpenPIC_Reg _IPI_Dispatch[OPENPIC_NUM_IPI]; /* Write Only */
79    /*
80     *  Current Task Priority Register
81     */
82    OpenPIC_Reg _Current_Task_Priority;         /* Read/Write */
83    char Pad3[0x10];
84    /*
85     *  Interrupt Acknowledge Register
86     */
87    OpenPIC_Reg _Interrupt_Acknowledge;         /* Read Only */
88    /*
89     *  End of Interrupt (EOI) Register
90     */
91    OpenPIC_Reg _EOI;                           /* Read/Write */
92    char Pad5[0xf40];
93} OpenPIC_Processor;
96    /*
97     *  Timer Registers
98     */
100typedef struct _OpenPIC_Timer {
101    OpenPIC_Reg _Current_Count;                 /* Read Only */
102    OpenPIC_Reg _Base_Count;                    /* Read/Write */
103    OpenPIC_Reg _Vector_Priority;               /* Read/Write */
104    OpenPIC_Reg _Destination;                   /* Read/Write */
105} OpenPIC_Timer;
108    /*
109     *  Global Registers
110     */
112typedef struct _OpenPIC_Global {
113    /*
114     *  Feature Reporting Registers
115     */
116    OpenPIC_Reg _Feature_Reporting0;            /* Read Only */
117    OpenPIC_Reg _Feature_Reporting1;            /* Future Expansion */
118    /*
119     *  Global Configuration Registers
120     */
121    OpenPIC_Reg _Global_Configuration0;         /* Read/Write */
122    OpenPIC_Reg _Global_Configuration1;         /* Future Expansion */
123    /*
124     *  Vendor Specific Registers
125     */
126    OpenPIC_Reg _Vendor_Specific[4];
127    /*
128     *  Vendor Identification Register
129     */
130    OpenPIC_Reg _Vendor_Identification;         /* Read Only */
131    /*
132     *  Processor Initialization Register
133     */
134    OpenPIC_Reg _Processor_Initialization;      /* Read/Write */
135    /*
136     *  IPI Vector/Priority Registers
137     */
138    OpenPIC_Reg _IPI_Vector_Priority[OPENPIC_NUM_IPI];  /* Read/Write */
139    /*
140     *  Spurious Vector Register
141     */
142    OpenPIC_Reg _Spurious_Vector;               /* Read/Write */
143    /*
144     *  Global Timer Registers
145     */
146    OpenPIC_Reg _Timer_Frequency;               /* Read/Write */
147    OpenPIC_Timer Timer[OPENPIC_NUM_TIMERS];
148    char Pad1[0xee00];
149} OpenPIC_Global;
152    /*
153     *  Interrupt Source Registers
154     */
156typedef struct _OpenPIC_Source {
157    OpenPIC_Reg _Vector_Priority;               /* Read/Write */
158    OpenPIC_Reg _Destination;                   /* Read/Write */
159} OpenPIC_Source;
162    /*
163     *  OpenPIC Register Map
164     */
166struct OpenPIC {
167    char Pad1[0x1000];
168    /*
169     *  Global Registers
170     */
171    OpenPIC_Global Global;
172    /*
173     *  Interrupt Source Configuration Registers
174     */
175    OpenPIC_Source Source[OPENPIC_MAX_SOURCES];
176    /*
177     *  Per Processor Registers
178     */
179    OpenPIC_Processor Processor[OPENPIC_MAX_PROCESSORS];
182extern volatile struct OpenPIC *OpenPIC;
183extern unsigned int OpenPIC_NumInitSenses;
184extern unsigned char *OpenPIC_InitSenses;
187    /*
188     *  Current Task Priority Register
189     */
191#define OPENPIC_CURRENT_TASK_PRIORITY_MASK      0x0000000f
193    /*
194     *  Who Am I Register
195     */
197#define OPENPIC_WHO_AM_I_ID_MASK                0x0000001f
199    /*
200     *  Feature Reporting Register 0
201     */
203#define OPENPIC_FEATURE_LAST_SOURCE_MASK        0x07ff0000
207#define OPENPIC_FEATURE_VERSION_MASK            0x000000ff
209    /*
210     *  Global Configuration Register 0
211     */
213#define OPENPIC_CONFIG_RESET                    0x80000000
215#define OPENPIC_CONFIG_BASE_MASK                0x000fffff
217    /*
218     *  Vendor Identification Register
219     */
221#define OPENPIC_VENDOR_ID_STEPPING_MASK         0x00ff0000
223#define OPENPIC_VENDOR_ID_DEVICE_ID_MASK        0x0000ff00
225#define OPENPIC_VENDOR_ID_VENDOR_ID_MASK        0x000000ff
227    /*
228     *  Vector/Priority Registers
229     */
231#define OPENPIC_MASK                            0x80000000
232#define OPENPIC_ACTIVITY                        0x40000000      /* Read Only */
233#define OPENPIC_PRIORITY_MASK                   0x000f0000
234#define OPENPIC_PRIORITY_SHIFT                  16
235#define OPENPIC_VECTOR_MASK                     0x000000ff
238    /*
239     *  Interrupt Source Registers
240     */
242#define OPENPIC_SENSE_POLARITY                  0x00800000      /* Undoc'd */
243#define OPENPIC_SENSE_LEVEL                     0x00400000
246    /*
247     *  Timer Registers
248     */
250#define OPENPIC_COUNT_MASK                      0x7fffffff
251#define OPENPIC_TIMER_TOGGLE                    0x80000000
252#define OPENPIC_TIMER_COUNT_INHIBIT             0x80000000
255    /*
256     *  Aliases to make life simpler
257     */
259/* Per Processor Registers */
260#define IPI_Dispatch(i)                 _IPI_Dispatch[i].Reg
261#define Current_Task_Priority           _Current_Task_Priority.Reg
262#define Interrupt_Acknowledge           _Interrupt_Acknowledge.Reg
263#define EOI                             _EOI.Reg
265/* Global Registers */
266#define Feature_Reporting0              _Feature_Reporting0.Reg
267#define Feature_Reporting1              _Feature_Reporting1.Reg
268#define Global_Configuration0           _Global_Configuration0.Reg
269#define Global_Configuration1           _Global_Configuration1.Reg
270#define Vendor_Specific(i)              _Vendor_Specific[i].Reg
271#define Vendor_Identification           _Vendor_Identification.Reg
272#define Processor_Initialization        _Processor_Initialization.Reg
273#define IPI_Vector_Priority(i)          _IPI_Vector_Priority[i].Reg
274#define Spurious_Vector                 _Spurious_Vector.Reg
275#define Timer_Frequency                 _Timer_Frequency.Reg
277/* Timer Registers */
278#define Current_Count                   _Current_Count.Reg
279#define Base_Count                      _Base_Count.Reg
280#define Vector_Priority                 _Vector_Priority.Reg
281#define Destination                     _Destination.Reg
283/* Interrupt Source Registers */
284#define Vector_Priority                 _Vector_Priority.Reg
285#define Destination                     _Destination.Reg
288    /*
289     *  Vendor and Device IDs
290     */
292#define OPENPIC_VENDOR_ID_APPLE         0x14
296    /*
297     *  OpenPIC Operations
298     */
300/* Global Operations */
301extern void openpic_init(int);
302extern void openpic_reset(void);
303extern void openpic_enable_8259_pass_through(void);
304extern void openpic_disable_8259_pass_through(void);
305extern unsigned int openpic_irq(unsigned int cpu);
306extern void openpic_eoi(unsigned int cpu);
307extern unsigned int openpic_get_priority(unsigned int cpu);
308extern void openpic_set_priority(unsigned int cpu, unsigned int pri);
309extern unsigned int openpic_get_spurious(void);
310extern void openpic_set_spurious(unsigned int vector);
311extern void openpic_init_processor(unsigned int cpumask);
313/* Interprocessor Interrupts */
314extern void openpic_initipi(unsigned int ipi, unsigned int pri, unsigned int vector);
315extern void openpic_cause_IPI(unsigned int cpu, unsigned int ipi, unsigned int cpumask);
317/* Timer Interrupts */
318extern void openpic_inittimer(unsigned int timer, unsigned int pri, unsigned int vector);
319extern void openpic_maptimer(unsigned int timer, unsigned int cpumask);
321/* Interrupt Sources */
322extern void openpic_enable_irq(unsigned int irq);
323extern void openpic_disable_irq(unsigned int irq);
324extern void openpic_initirq(unsigned int irq, unsigned int pri, unsigned int vector, int polarity,
325                            int is_level);
326extern void openpic_mapirq(unsigned int irq, unsigned int cpumask);
327extern void openpic_set_sense(unsigned int irq, int sense);
329#endif /* RTEMS_OPENPIC_H */
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