source: rtems/c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h @ 9cf283a

4.104.114.95
Last change on this file since 9cf283a was 9cf283a, checked in by Joel Sherrill <joel.sherrill@…>, on 12/11/07 at 15:50:38

2007-12-11 Joel Sherrill <joel.sherrill@…>

  • include/bsp.h: Eliminate copies of the Configuration Table. Use the RTEMS provided accessor macros to obtain configuration fields.
  • Property mode set to 100644
File size: 7.4 KB
Line 
1/*
2 *  bsp.h  -- contain BSP API definition.
3 *
4 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
5 *
6 *  The license and distribution terms for this file may be
7 *  found in found in the file LICENSE in this distribution or at
8 *  http://www.rtems.com/license/LICENSE.
9 *
10 * $Id$
11 */
12#ifndef _BSP_H
13#define _BSP_H
14
15#include <bspopts.h>
16
17#include <rtems.h>
18#include <rtems/console.h>
19#include <libcpu/io.h>
20#include <rtems/clockdrv.h>
21#include <bsp/vectors.h>
22
23/*
24 *  confdefs.h overrides for this BSP:
25 *   - termios serial ports (defaults to 1)
26 *   - Interrupt stack space is not minimum if defined.
27 */
28
29#if !defined(mvme2100)
30#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
31#endif
32
33/*
34 * diagram illustrating the role of the configuration
35 * constants
36 *  PCI_MEM_WIN0:        CPU starting addr where PCI memory space is visible
37 *  PCI_MEM_BASE:        CPU address of PCI mem addr. zero. (regardless of this
38 *                       address being 'visible' or not!).
39 * _VME_A32_WIN0_ON_PCI: PCI starting addr of the 1st window to VME
40 * _VME_A32_WIN0_ON_VME: VME address of that same window
41 *
42 * AFAIK, only PreP boards have a non-zero PCI_MEM_BASE (i.e., an offset between
43 * CPU and PCI addresses). The mvme2300 'ppcbug' firmware configures the PCI
44 * bus using PCI base addresses! I.e., drivers need to add PCI_MEM_BASE to
45 * the base address read from PCI config.space in order to translate that
46 * into a CPU address.
47 *
48 * NOTE: VME addresses should NEVER be translated using these constants!
49 *       they are strictly for BSP internal use. Drivers etc. should use
50 *       the translation routines int VME.h (BSP_vme2local_adrs/BSP_local2vme_adrs).
51 *
52 *           CPU ADDR                  PCI_ADDR                                VME ADDR
53 *
54 *           00000000                  XXXXXXXX                                XXXXXXXX
55 *    ^  ^   ........         
56 *    |  |
57 *    |  |  e.g., RAM                  XXXXXXXX
58 *    |  |                                                                     00000000
59 *    |  |  .........                                                          ^
60 *    |  |            (possible offset                                         |
61 *    |  |             between pci and XXXXXXXX                                | ......
62 *    |  |             cpu addresses)                                          |
63 *    |  v                                                                     |
64 *    |  PCI_MEM_BASE  ------------->  00000000 ---------------                |
65 *    |     ........                   ........               ^                |
66 *    |                                invisible              |                |
67 *    |     ........                   from CPU               |                |
68 *    v                                                       |                |
69 *       PCI_MEM_WIN0 =============  first visible PCI addr   |                |
70 *                                                            |                |
71 *        pci devices   pci window                            |                |
72 *       visible here                                         v                v
73 *                      mapped by   ========== _VME_A32_WIN0_ON_PCI =======  _VME_A32_WIN0_ON_VME
74 *                                                 vme window
75 *        VME devices   hostbridge                 mapped by
76 *       visible here                              universe
77 *                    =====================================================
78 *
79 */
80
81/* fundamental addresses for BSP (CHRPxxx and PREPxxx are from libcpu/io.h) */
82#if defined(mvme2100)
83#define _IO_BASE                CHRP_ISA_IO_BASE
84#define _ISA_MEM_BASE           CHRP_ISA_MEM_BASE
85/* address of our ram on the PCI bus   */
86#define PCI_DRAM_OFFSET         CHRP_PCI_DRAM_OFFSET
87/* offset of pci memory as seen from the CPU */
88#define PCI_MEM_BASE            0
89/* where (in CPU addr. space) does the PCI window start */
90#define PCI_MEM_WIN0            0x80000000
91
92#else
93#define _IO_BASE                PREP_ISA_IO_BASE
94#define _ISA_MEM_BASE           PREP_ISA_MEM_BASE
95/* address of our ram on the PCI bus   */
96#define PCI_DRAM_OFFSET         PREP_PCI_DRAM_OFFSET
97/* offset of pci memory as seen from the CPU */
98#define PCI_MEM_BASE            PREP_ISA_MEM_BASE
99#define PCI_MEM_WIN0            0
100#endif
101
102
103/*
104 *  Base address definitions for several devices
105 *
106 *  MVME2100 is very similar but has fewer devices and uses on-CPU EPIC
107 *  implementation of OpenPIC controller.  It also cannot be probed to
108 *  find out what it is which is VERY different from other Motorola boards.
109 */
110
111#if defined(mvme2100)
112#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x01e10000)
113/* #define BSP_UART_IOBASE_COM1     (0xffe10000) */
114#define BSP_OPEN_PIC_BASE_OFFSET 0x40000
115
116#define MVME_HAS_DEC21140
117#else
118#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x3f8)
119#define BSP_UART_IOBASE_COM2 ((_IO_BASE)+0x2f8)
120
121#define BSP_KBD_IOBASE       ((_IO_BASE)+0x60)
122#define BSP_VGA_IOBASE       ((_IO_BASE)+0x3c0)
123
124#if defined(mvme2300)
125#define MVME_HAS_DEC21140
126#endif
127#endif
128
129#define BSP_CONSOLE_PORT        BSP_UART_COM1
130#define BSP_UART_BAUD_BASE      115200
131
132#include <bsp/openpic.h>
133/* BSP_PIC_DO_EOI is optionally used by the 'vmeUniverse' driver
134 * to implement VME IRQ priorities in software.
135 * Note that this requires support by the interrupt controller
136 * driver (cf. libbsp/shared/powerpc/irq/openpic_i8259_irq.c)
137 * and the BSP-specific universe initialization/configuration
138 * (cf. libbsp/shared/powerpc/vme/VMEConfig.h vme_universe.c)
139 *
140 * ********* IMPORTANT NOTE ********
141 * When deriving from this file (new BSPs)
142 * DO NOT define "BSP_PIC_DO_EOI" if you don't know what
143 * you are doing i.e., w/o implementing the required pieces
144 * mentioned above.
145 * ********* IMPORTANT NOTE ********
146 */
147#define BSP_PIC_DO_EOI openpic_eoi(0)
148
149#ifndef ASM
150#define outport_byte(port,value) outb(value,port)
151#define outport_word(port,value) outw(value,port)
152#define outport_long(port,value) outl(value,port)
153
154#define inport_byte(port,value) (value = inb(port))
155#define inport_word(port,value) (value = inw(port))
156#define inport_long(port,value) (value = inl(port))
157
158/*
159 * Vital Board data Start using DATA RESIDUAL
160 */
161
162/*
163 * Total memory using RESIDUAL DATA
164 */
165extern unsigned int BSP_mem_size;
166/*
167 * Start of the heap
168 */
169extern unsigned int BSP_heap_start;
170/*
171 * PCI Bus Frequency
172 */
173extern unsigned int BSP_bus_frequency;
174/*
175 * processor clock frequency
176 */
177extern unsigned int BSP_processor_frequency;
178/*
179 * Time base divisior (how many tick for 1 second).
180 */
181extern unsigned int BSP_time_base_divisor;
182
183/*
184 * String passed by the bootloader.
185 */
186extern char *BSP_commandline_string;
187
188#define BSP_Convert_decrementer( _value ) \
189  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
190
191extern void BSP_panic(char *s);
192extern void rtemsReboot(void);
193/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */
194extern int BSP_disconnect_clock_handler (void);
195extern int BSP_connect_clock_handler (void);
196
197/* clear hostbridge errors
198 *
199 * NOTE: The routine returns always (-1) if 'enableMCP==1'
200 *       [semantics needed by libbspExt] if the MCP input is not wired.
201 *       It returns and clears the error bits of the PCI status register.
202 *       MCP support is disabled because:
203 *         a) the 2100 has no raven chip
204 *         b) the raven (2300) would raise machine check interrupts
205 *            on PCI config space access to empty slots.
206 */
207extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
208
209#endif
210
211#endif
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