source: rtems/c/src/lib/libbsp/powerpc/motorola_powerpc/include/bsp.h @ 0a0d67c5

4.104.114.84.9
Last change on this file since 0a0d67c5 was 0a0d67c5, checked in by Ralf Corsepius <ralf.corsepius@…>, on Apr 1, 2004 at 10:11:40 AM

2004-04-01 Ralf Corsepius <ralf_corsepius@…>

  • include/bsp.h: Include <rtems/clockdrv.h> instead of <clockdrv.h>.
  • include/bsp.h: Include <rtems/console.h> instead of <console.h>.
  • Property mode set to 100644
File size: 4.2 KB
Line 
1/*
2 *  bsp.h  -- contain BSP API definition.
3 *
4 *  Copyright (C) 1999 Eric Valette. valette@crf.canon.fr
5 *
6 *  The license and distribution terms for this file may be
7 *  found in found in the file LICENSE in this distribution or at
8 *  http://www.rtems.com/license/LICENSE.
9 *
10 * $Id$
11 */
12#ifndef LIBBSP_POWERPC_MOTOROLA_SHARED_BSP_H
13#define LIBBSP_POWERPC_MOTOROLA_SHARED_BSP_H
14
15#include <bspopts.h>
16
17#include <rtems.h>
18#include <rtems/console.h>
19#include <libcpu/io.h>
20#include <rtems/clockdrv.h>
21#include <bsp/vectors.h>
22
23/*
24 *  confdefs.h overrides for this BSP:
25 *   - termios serial ports (defaults to 1)
26 *   - Interrupt stack space is not minimum if defined.
27 */
28
29#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2
30#define CONFIGURE_INTERRUPT_STACK_MEMORY  (16 * 1024)
31
32/* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */
33#define _IO_BASE                        PREP_ISA_IO_BASE
34#define _ISA_MEM_BASE           PREP_ISA_MEM_BASE
35/* address of our ram on the PCI bus   */
36#define PCI_DRAM_OFFSET         PREP_PCI_DRAM_OFFSET
37/* offset of pci memory as seen from the CPU */
38#define PCI_MEM_BASE            PREP_ISA_MEM_BASE
39
40/*
41 *  base address definitions for several devices
42 *
43 */
44#define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x3f8)
45#define BSP_UART_IOBASE_COM2 ((_IO_BASE)+0x2f8)
46#define BSP_KBD_IOBASE       ((_IO_BASE)+0x60)
47#define BSP_VGA_IOBASE       ((_IO_BASE)+0x3c0)
48
49#define BSP_CONSOLE_PORT        BSP_UART_COM1
50#define BSP_UART_BAUD_BASE      115200
51 
52#include <bsp/openpic.h>
53#define BSP_PIC_DO_EOI openpic_eoi(0)
54
55
56#ifndef ASM
57#define outport_byte(port,value) outb(value,port)
58#define outport_word(port,value) outw(value,port)
59#define outport_long(port,value) outl(value,port)
60
61#define inport_byte(port,value) (value = inb(port))
62#define inport_word(port,value) (value = inw(port))
63#define inport_long(port,value) (value = inl(port))
64/*
65 * Vital Board data Start using DATA RESIDUAL
66 */
67/*
68 * Total memory using RESIDUAL DATA
69 */
70extern unsigned int BSP_mem_size;
71/*
72 * PCI Bus Frequency
73 */
74extern unsigned int BSP_bus_frequency;
75/*
76 * processor clock frequency
77 */
78extern unsigned int BSP_processor_frequency;
79/*
80 * Time base divisior (how many tick for 1 second).
81 */
82extern unsigned int BSP_time_base_divisor;
83
84#define BSP_Convert_decrementer( _value ) \
85  ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value)))
86
87extern rtems_configuration_table  BSP_Configuration;
88extern void BSP_panic(char *s);
89extern void rtemsReboot(void);
90/* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */
91extern int BSP_disconnect_clock_handler (void);
92extern int BSP_connect_clock_handler (void);
93
94/* clear hostbridge errors
95 *
96 * enableMCP: whether to enable MCP checkstop / machine check interrupts
97 *            on the hostbridge and in HID0.
98 *
99 *            NOTE: HID0 and MEREN are left alone if this flag is 0
100 *
101 * quiet    : be silent
102 *
103 * RETURNS  : raven MERST register contents (lowermost 16 bits), 0 if
104 *            there were no errors
105 */
106extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet);
107
108
109/*
110 *  TM27 stuff
111 */
112
113#if defined(USE_ENHANCED_INTR_API) && defined(RTEMS_TM27)
114
115#include <bsp/irq.h>
116
117#define MUST_WAIT_FOR_INTERRUPT 1
118
119void nullFunc() {}
120static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER,
121                                              0,
122                                              (rtems_irq_enable)nullFunc,
123                                              (rtems_irq_disable)nullFunc,
124                                              (rtems_irq_is_enabled) nullFunc};
125void Install_tm27_vector(void (*_handler)())
126{
127  clockIrqData.hdl = _handler;
128  if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
129        printk("Error installing clock interrupt handler!\n");
130        rtems_fatal_error_occurred(1);
131  }
132}
133
134#define Cause_tm27_intr()  \
135  do { \
136    uint32_t   _clicks = 8; \
137    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
138  } while (0)
139
140
141#define Clear_tm27_intr() \
142  do { \
143    uint32_t   _clicks = 0xffffffff; \
144    asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
145  } while (0)
146
147#define Lower_tm27_intr() \
148  do { \
149    uint32_t   _msr = 0; \
150    _ISR_Set_level( 0 ); \
151    asm volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
152    _msr |=  0x8002; \
153    asm volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
154  } while (0)
155#endif
156
157
158#endif
159
160#endif
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