[23090f33] | 1 | /* |
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| 2 | * bsp.h -- contain BSP API definition. |
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| 3 | * |
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| 4 | * Copyright (C) 1999 Eric Valette. valette@crf.canon.fr |
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| 5 | * |
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| 6 | * The license and distribution terms for this file may be |
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| 7 | * found in found in the file LICENSE in this distribution or at |
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| 8 | * http://www.rtems.com/license/LICENSE. |
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| 9 | * |
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| 10 | * $Id$ |
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| 11 | */ |
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| 12 | #ifndef LIBBSP_POWERPC_MOTOROLA_SHARED_BSP_H |
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| 13 | #define LIBBSP_POWERPC_MOTOROLA_SHARED_BSP_H |
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| 14 | |
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| 15 | #include <bspopts.h> |
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| 16 | |
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| 17 | #include <rtems.h> |
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[0a0d67c5] | 18 | #include <rtems/console.h> |
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[23090f33] | 19 | #include <libcpu/io.h> |
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[0a0d67c5] | 20 | #include <rtems/clockdrv.h> |
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[23090f33] | 21 | #include <bsp/vectors.h> |
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| 22 | |
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| 23 | /* |
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| 24 | * confdefs.h overrides for this BSP: |
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| 25 | * - termios serial ports (defaults to 1) |
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| 26 | * - Interrupt stack space is not minimum if defined. |
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| 27 | */ |
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| 28 | |
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| 29 | #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 |
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| 30 | #define CONFIGURE_INTERRUPT_STACK_MEMORY (16 * 1024) |
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| 31 | |
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| 32 | /* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */ |
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| 33 | #define _IO_BASE PREP_ISA_IO_BASE |
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| 34 | #define _ISA_MEM_BASE PREP_ISA_MEM_BASE |
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| 35 | /* address of our ram on the PCI bus */ |
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| 36 | #define PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET |
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| 37 | /* offset of pci memory as seen from the CPU */ |
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| 38 | #define PCI_MEM_BASE PREP_ISA_MEM_BASE |
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| 39 | |
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| 40 | /* |
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| 41 | * base address definitions for several devices |
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| 42 | * |
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| 43 | */ |
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| 44 | #define BSP_UART_IOBASE_COM1 ((_IO_BASE)+0x3f8) |
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| 45 | #define BSP_UART_IOBASE_COM2 ((_IO_BASE)+0x2f8) |
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| 46 | #define BSP_KBD_IOBASE ((_IO_BASE)+0x60) |
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| 47 | #define BSP_VGA_IOBASE ((_IO_BASE)+0x3c0) |
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| 48 | |
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| 49 | #define BSP_CONSOLE_PORT BSP_UART_COM1 |
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| 50 | #define BSP_UART_BAUD_BASE 115200 |
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| 51 | |
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| 52 | #include <bsp/openpic.h> |
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| 53 | #define BSP_PIC_DO_EOI openpic_eoi(0) |
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| 54 | |
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| 55 | |
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| 56 | #ifndef ASM |
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| 57 | #define outport_byte(port,value) outb(value,port) |
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| 58 | #define outport_word(port,value) outw(value,port) |
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| 59 | #define outport_long(port,value) outl(value,port) |
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| 60 | |
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| 61 | #define inport_byte(port,value) (value = inb(port)) |
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| 62 | #define inport_word(port,value) (value = inw(port)) |
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| 63 | #define inport_long(port,value) (value = inl(port)) |
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| 64 | /* |
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| 65 | * Vital Board data Start using DATA RESIDUAL |
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| 66 | */ |
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| 67 | /* |
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| 68 | * Total memory using RESIDUAL DATA |
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| 69 | */ |
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| 70 | extern unsigned int BSP_mem_size; |
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| 71 | /* |
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| 72 | * PCI Bus Frequency |
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| 73 | */ |
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| 74 | extern unsigned int BSP_bus_frequency; |
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| 75 | /* |
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| 76 | * processor clock frequency |
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| 77 | */ |
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| 78 | extern unsigned int BSP_processor_frequency; |
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| 79 | /* |
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| 80 | * Time base divisior (how many tick for 1 second). |
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| 81 | */ |
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| 82 | extern unsigned int BSP_time_base_divisor; |
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| 83 | |
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| 84 | #define BSP_Convert_decrementer( _value ) \ |
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| 85 | ((unsigned long long) ((((unsigned long long)BSP_time_base_divisor) * 1000000ULL) /((unsigned long long) BSP_bus_frequency)) * ((unsigned long long) (_value))) |
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| 86 | |
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| 87 | extern rtems_configuration_table BSP_Configuration; |
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| 88 | extern void BSP_panic(char *s); |
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| 89 | extern void rtemsReboot(void); |
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| 90 | /* extern int printk(const char *, ...) __attribute__((format(printf, 1, 2))); */ |
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| 91 | extern int BSP_disconnect_clock_handler (void); |
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| 92 | extern int BSP_connect_clock_handler (void); |
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| 93 | |
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| 94 | /* clear hostbridge errors |
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| 95 | * |
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| 96 | * enableMCP: whether to enable MCP checkstop / machine check interrupts |
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| 97 | * on the hostbridge and in HID0. |
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| 98 | * |
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| 99 | * NOTE: HID0 and MEREN are left alone if this flag is 0 |
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| 100 | * |
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| 101 | * quiet : be silent |
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| 102 | * |
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| 103 | * RETURNS : raven MERST register contents (lowermost 16 bits), 0 if |
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| 104 | * there were no errors |
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| 105 | */ |
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| 106 | extern unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet); |
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| 107 | |
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| 108 | |
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| 109 | /* |
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| 110 | * TM27 stuff |
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| 111 | */ |
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| 112 | |
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| 113 | #if defined(USE_ENHANCED_INTR_API) && defined(RTEMS_TM27) |
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| 114 | |
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| 115 | #include <bsp/irq.h> |
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| 116 | |
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| 117 | #define MUST_WAIT_FOR_INTERRUPT 1 |
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| 118 | |
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| 119 | void nullFunc() {} |
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| 120 | static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER, |
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| 121 | 0, |
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| 122 | (rtems_irq_enable)nullFunc, |
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| 123 | (rtems_irq_disable)nullFunc, |
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| 124 | (rtems_irq_is_enabled) nullFunc}; |
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| 125 | void Install_tm27_vector(void (*_handler)()) |
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| 126 | { |
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| 127 | clockIrqData.hdl = _handler; |
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| 128 | if (!BSP_install_rtems_irq_handler (&clockIrqData)) { |
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| 129 | printk("Error installing clock interrupt handler!\n"); |
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| 130 | rtems_fatal_error_occurred(1); |
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| 131 | } |
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| 132 | } |
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| 133 | |
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| 134 | #define Cause_tm27_intr() \ |
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| 135 | do { \ |
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[d352678] | 136 | uint32_t _clicks = 8; \ |
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[23090f33] | 137 | asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ |
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| 138 | } while (0) |
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| 139 | |
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| 140 | |
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| 141 | #define Clear_tm27_intr() \ |
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| 142 | do { \ |
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[d352678] | 143 | uint32_t _clicks = 0xffffffff; \ |
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[23090f33] | 144 | asm volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \ |
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| 145 | } while (0) |
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| 146 | |
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| 147 | #define Lower_tm27_intr() \ |
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| 148 | do { \ |
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[d352678] | 149 | uint32_t _msr = 0; \ |
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[23090f33] | 150 | _ISR_Set_level( 0 ); \ |
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| 151 | asm volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ |
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| 152 | _msr |= 0x8002; \ |
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| 153 | asm volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \ |
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| 154 | } while (0) |
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| 155 | #endif |
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| 156 | |
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| 157 | |
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| 158 | #endif |
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| 159 | |
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| 160 | #endif |
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