source: rtems/c/src/lib/libbsp/powerpc/motorola_powerpc/console/console.c @ ba46ffa6

4.104.114.84.95
Last change on this file since ba46ffa6 was ba46ffa6, checked in by Joel Sherrill <joel.sherrill@…>, on 06/14/99 at 16:51:13

This is a large patch from Eric Valette <valette@…> that was
described in the message following this paragraph. This patch also includes
a mcp750 BSP.

From valette@… Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@…>
To: joel@…
Cc: raguet@…, rtems-snapshots@…, valette@…
Subject: Questions/Suggestion? regarding RTEMS PowerPC code (long)

Dear knowledgeable RTEMS powerpc users,

As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.

In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.

the MCP750 is a COMPACT PCI powerpc board with :

1) a MPC750 233 MHz processor,
2) a raven bus bridge/PCI controller that
implement an OPENPIC compliant interrupt controller,
3) a VIA 82C586 PCI/ISA bridge that offers a PC
compliant IO for keyboard, serial line, IDE, and
the well known PC 8259 cascaded PIC interrupt
architecture model,
4) a DEC 21140 Ethernet controller,
5) the PPCBUG Motorola firmware in flash,
6) A DEC PCI bridge,

This architecture is common to most Motorola 60x/7xx
board except that :

1) on VME board, the DEC PCI bridge is replaced by
a VME chipset,
2) the VIA 82C586 PCI/ISA bridge is replaced by
another bridge that is almost fully compatible
with the via bridge...

So the port should be a rather close basis for many
60x/7xx motorola board...

On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.

Now the questions/suggestions I have :

1) EXCEPTION CODE


As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :

a) Except for the decrementer exception (and
maybe some other on mpc8xx), exceptions are
not recoverable and the handler just need to print
the full context and go to the firmware or debugger...
b) The interrupt switch is only necessary for the
decrementer and external interrupt (at least on
6xx,7xx).
c) The full context for exception is never saved and
thus cannot be used by debugger... I do understand
the most important for interrupts low level code
is to save the minimal context enabling to call C
code for performance reasons. On non recoverable
exception on the other hand, the most important is
to save the maximum information concerning proc status
in order to analyze the reason of the fault. At
least we will need this in order to implement the
port of RGDB on PPC

==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)

See remark about files/directory layout organization in 4)

2) Current Implementation of ISR low level code


I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S

#if (PPC_USE_SPRG)

mfmsr r5
mfspr r6, sprg2

#else

lwz r6,msr_initial(r11)
lis r5,~PPC_MSR_DISABLE_MASK@ha
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
and r6,r6,r5
mfmsr r5

#endif

Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :

a) I want the MSR[IR] and MSR[DR] to be set for
performance reasons and also because I need DBAT
support to have access to PCI memory space as the
interrupt controller is in the PCI space.

Reading the code, I see others have the same kind of request :

/* SCE 980217

*

  • We need address translation ON when we call our ISR routine

mtmsr r5

*/

This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...

Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO
acknowledged.

I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...

So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)

I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.

3) R2/R13 manipulation for EABI implementation


I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).

So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or
handling.

The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.

=> I propose to suppress any specific code for r2 and
r13 in the EABI case.

4) Code layout organization (yes again :-))


I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.

a) exec/score/cpu/* vs lib/libcpu/cpu/*.

I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.

This include at least :

a) registers access routine (e.g GET_MSR_Value),
b) interrupt masking/unmasking routines,
c) cache_mngt_routine,
d) mmu_mngt_routine,
e) Routines to connect the raw_exception, raw_interrupt
handler,

b) lib/libcpu/cpu/powerpc/*

With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x) the directory structure
is fine (except maybe the names that are not homogeneous)

powerpc

ppc421 mpc821 ...

I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.

So, except if the support of automake provides a better solution
I would like to propose something like this :

powerpc

mpc421 mpc821 ... mpc750 shared wrapup

with the following rules :

a) "shared" would act as a source container for sources that may
be shared among processors. Needed files would be compiled inside
the processor specific directory using the vpath Makefile
mechanism. "shared" may also contain compilation code
for routine that are really shared and not worth to inline...
(did not found many things so far as registers access routine
ARE WORTH INLINING)... In the case something is compiled there,
it should create libcpushared.a

b) layout under processor specific directory is free provided
that

1)the result of the compilation process exports :

libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu

2) each processor specific directory creates
a library called libcpuspecific.a

Note that this organization enables to have a file that
is nearly the same than in shared but that must differ
because of processor differences...

c) "wrapup" should create libcpu.a using libcpushared.a
libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu

The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...

Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...

NB: I have done this for mpc750 and other processors could just use
similar Makefiles...

c) The exec/score/cpu/powerpc directory layout.

I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...

Besides that I do not understand why

1) things are compiled in the wrap directory,
2) some includes are moved to rtems/score,

I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor
directory),

5) Interrupt handling API


Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :


| OPEN | <-----|8259|
| PIC | | | 2 ------
|(RAVEN)| | | <-----|8259|
| | | | | | 11
| | | | | | <----
| | | | | |
| | | | | |


------
| VIA PCI/ISA bridge
| x
-------- PCI interrupts

OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :

1) there is no way to specify priorities among
interrupts handler. This is REALLY a bad thing.
For me it is as importnat as having priorities
for threads...
2) for my implementation, each ISR should
contain the code that acknowledge the RAVEN
and 8259 cascade, modify interrupt mask on both
chips, and reenable interrupt at processor level,
..., restore then on interrupt return,.... This code
is actually similar to code located in some
genpvec.c powerpc files,
3) I must update _ISR_Nesting_level because
irq.inl use it...
4) the libchip code connects the ISR via set_vector
but the libchip handler code does not contain any code to
manipulate external interrupt controller hardware
in order to acknoledge the interrupt or re-enable
them (except for the target hardware of course)
So this code is broken unless set_vector adds an
additionnal prologue/epilogue before calling/returning
from in order to acknoledge/mask the raven and the
8259 PICS... => Anyway already EACH BSP MUST REWRITE
PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT
SET_VECTOR.

I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :

1) Once the driver supplied methods is called the
only things the ISR has to do is to worry about the
external hardware that triggered the interrupt.
Everything on openpic/VIA/processor would have been
done by the low levels (same things as set-vector)
2) The caller will need to supply the on/off/isOn
routine that are fundamental to correctly implements
debuggers/performance monitoring is a portable way
3) A globally configurable interrupt priorities
mechanism...

I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).

Additional note : I think the _ISR_Is_in_progress()
inline routine should be :

1) Put in a processor specific section,
2) Should not rely on a global variable,

As :

a) on symmetric MP, there is one interrupt level
per CPU,
b) On processor that have an ISP (e,g 68040),
this variable is useless (MSR bit testing could
be used)
c) On PPC, instead of using the address of the
variable via CPU_IRQ_info.Nest_level a dedicated
SPR could be used.

NOTE: most of this is also true for _Thread_Dispatch_disable_level

END NOTE


Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :

1) try to better understand the actual code,
2) propose concrete ways of enhancing current code
by providing an alternative implementation for MCP750. I
will make my best effort to try to brake nothing but this
is actually hard due to the file layout organisation.
3) make understandable some changes I will probably make
if joel let me do them :-)

Any comments/objections are welcomed as usual.

--


/ ` Eric Valette

/-- o _. Canon CRF

(_, / (_(_( Rue de la touche lambert

35517 Cesson-Sevigne Cedex
FRANCE

Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30
E-mail: valette@…

  • Property mode set to 100644
File size: 10.1 KB
Line 
1/*-------------------------------------------------------------------------+
2| console.c v1.1 - PC386 BSP - 1997/08/07
3+--------------------------------------------------------------------------+
4| This file contains the PC386 console I/O package.
5+--------------------------------------------------------------------------+
6| (C) Copyright 1997 -
7| - NavIST Group - Real-Time Distributed Systems and Industrial Automation
8|
9| http://pandora.ist.utl.pt
10|
11| Instituto Superior Tecnico * Lisboa * PORTUGAL
12+--------------------------------------------------------------------------+
13| Disclaimer:
14|
15| This file is provided "AS IS" without warranty of any kind, either
16| expressed or implied.
17+--------------------------------------------------------------------------+
18| This code is based on:
19|   console.c,v 1.4 1995/12/19 20:07:23 joel Exp - go32 BSP
20| With the following copyright notice:
21| **************************************************************************
22| *  COPYRIGHT (c) 1989-1998.
23| *  On-Line Applications Research Corporation (OAR).
24| *  Copyright assigned to U.S. Government, 1994.
25| *
26| *  The license and distribution terms for this file may be
27| *  found in found in the file LICENSE in this distribution or at
28| *  http://www.OARcorp.com/rtems/license.html.
29| **************************************************************************
30|
31|  $Id$
32+--------------------------------------------------------------------------*/
33
34#include <stdio.h>
35#include <stdlib.h>
36#include <assert.h>
37#undef __assert
38void __assert (const char *file, int line, const char *msg);
39
40#include <bsp.h>
41#include <bsp/irq.h>
42#include <rtems/libio.h>
43#include <termios.h>
44#include <bsp/uart.h>
45#include <bsp/consoleIo.h>
46
47/* Definitions for BSPConsolePort */
48#define BSP_CONSOLE_PORT_CONSOLE (-1)
49#define BSP_CONSOLE_PORT_COM1    (BSP_UART_COM1)
50#define BSP_CONSOLE_PORT_COM2    (BSP_UART_COM2)
51/*
52 * Possible value for console input/output :
53 *      BSP_CONSOLE_PORT_CONSOLE
54 *      BSP_UART_COM1
55 *      BSP_UART_COM2
56 */
57
58int BSPConsolePort = BSP_UART_COM1;
59
60/* int BSPConsolePort = BSP_UART_COM2;  */
61int BSPBaseBaud    = 115200;
62
63/*-------------------------------------------------------------------------+
64| External Prototypes
65+--------------------------------------------------------------------------*/
66
67static int  conSetAttr(int minor, const struct termios *);
68static void isr_on(const rtems_irq_connect_data *);
69static void isr_off(const rtems_irq_connect_data *);
70static int  isr_is_on(const rtems_irq_connect_data *);
71
72
73static rtems_irq_connect_data console_isr_data = {BSP_ISA_UART_COM1_IRQ,
74                                                   BSP_uart_termios_isr_com1,
75                                                   isr_on,
76                                                   isr_off,
77                                                   isr_is_on};
78
79static void
80isr_on(const rtems_irq_connect_data *unused)
81{
82  return;
83}
84                                                   
85static void
86isr_off(const rtems_irq_connect_data *unused)
87{
88  return;
89}
90
91static int
92isr_is_on(const rtems_irq_connect_data *irq)
93{
94  return BSP_irq_enabled_at_i8259s(irq->name);
95}
96
97void console_reserve_resources(rtems_configuration_table *conf)
98{
99    if(BSPConsolePort != BSP_CONSOLE_PORT_CONSOLE)
100    {
101      rtems_termios_reserve_resources(conf, 1);
102    }
103   
104  return;
105}
106
107void __assert (const char *file, int line, const char *msg)
108{
109    static   char exit_msg[] = "EXECUTIVE SHUTDOWN! Any key to reboot...";
110  unsigned char  ch;
111   
112  /*
113   * Note we cannot call exit or printf from here,
114   * assert can fail inside ISR too
115   */
116
117   /*
118    * Close console
119   */
120  close(2);
121  close(1);
122  close(0);
123
124  printk("\nassert failed: %s: ", file);
125  printk("%d: ", line);
126  printk("%s\n\n", msg);
127  printk(exit_msg);
128  ch = debug_getc();
129  printk("\n\n");
130  rtemsReboot();
131
132}
133
134
135/*-------------------------------------------------------------------------+
136| Console device driver INITIALIZE entry point.
137+--------------------------------------------------------------------------+
138| Initilizes the I/O console (keyboard + VGA display) driver.
139+--------------------------------------------------------------------------*/
140rtems_device_driver
141console_initialize(rtems_device_major_number major,
142                   rtems_device_minor_number minor,
143                   void                      *arg)
144{
145  rtems_status_code status;
146
147  /*
148   *  The video was initialized in the start.s code and does not need
149   *  to be reinitialized.
150   */
151
152
153  /*
154   * Set up TERMIOS
155   */
156  rtems_termios_initialize ();
157     
158  /*
159   * Do device-specific initialization
160   */
161     
162  /* 9600-8-N-1 */
163  BSP_uart_init(BSPConsolePort, 9600, 0);
164     
165     
166  /* Set interrupt handler */
167  if(BSPConsolePort == BSP_UART_COM1)
168    {
169      console_isr_data.name = BSP_ISA_UART_COM1_IRQ;
170      console_isr_data.hdl  = BSP_uart_termios_isr_com1;
171         
172    }
173  else
174    {
175      assert(BSPConsolePort == BSP_UART_COM2);
176      console_isr_data.name = BSP_ISA_UART_COM2_IRQ;
177      console_isr_data.hdl  = BSP_uart_termios_isr_com2;
178    }
179
180  status = BSP_install_rtems_irq_handler(&console_isr_data);
181
182  if (!status){
183    printk("Error installing serial console interrupt handler!\n");
184    rtems_fatal_error_occurred(status);
185  }
186  /*
187   * Register the device
188   */
189  status = rtems_io_register_name ("/dev/console", major, 0);
190  if (status != RTEMS_SUCCESSFUL)
191    {
192      printk("Error registering console device!\n");
193      rtems_fatal_error_occurred (status);
194    }
195
196  if(BSPConsolePort == BSP_UART_COM1)
197    {
198      printk("Initialized console on port COM1 9600-8-N-1\n\n");
199    }
200  else
201    {
202      printk("Initialized console on port COM2 9600-8-N-1\n\n");
203    }
204  return RTEMS_SUCCESSFUL;
205} /* console_initialize */
206
207
208static int console_open_count = 0;
209
210static int console_last_close(int major, int minor, void *arg)
211{
212  BSP_remove_rtems_irq_handler (&console_isr_data);
213
214  return 0;
215}
216
217/*-------------------------------------------------------------------------+
218| Console device driver OPEN entry point
219+--------------------------------------------------------------------------*/
220rtems_device_driver
221console_open(rtems_device_major_number major,
222                rtems_device_minor_number minor,
223                void                      *arg)
224{
225  rtems_status_code              status;
226  static rtems_termios_callbacks cb =
227  {
228    NULL,                     /* firstOpen */
229    console_last_close,       /* lastClose */
230    NULL,                     /* pollRead */
231    BSP_uart_termios_write_com1, /* write */
232    conSetAttr,               /* setAttributes */
233    NULL,                     /* stopRemoteTx */
234    NULL,                     /* startRemoteTx */
235    1                         /* outputUsesInterrupts */
236  };
237
238  if(BSPConsolePort == BSP_UART_COM2)
239    {
240      cb.write = BSP_uart_termios_write_com2;
241    }
242
243  status = rtems_termios_open (major, minor, arg, &cb);
244
245  if(status != RTEMS_SUCCESSFUL)
246    {
247      printk("Error openning console device\n");
248      return status;
249    }
250
251  /*
252   * Pass data area info down to driver
253   */
254  BSP_uart_termios_set(BSPConsolePort,
255                         ((rtems_libio_open_close_args_t *)arg)->iop->data1);
256  /* Enable interrupts  on channel */
257  BSP_uart_intr_ctrl(BSPConsolePort, BSP_UART_INTR_CTRL_TERMIOS);
258
259  return RTEMS_SUCCESSFUL;
260}
261
262/*-------------------------------------------------------------------------+
263| Console device driver CLOSE entry point
264+--------------------------------------------------------------------------*/
265rtems_device_driver
266console_close(rtems_device_major_number major,
267              rtems_device_minor_number minor,
268              void                      *arg)
269{
270  rtems_device_driver res = RTEMS_SUCCESSFUL;
271
272  res =  rtems_termios_close (arg);
273 
274  return res;
275} /* console_close */
276
277 
278/*-------------------------------------------------------------------------+
279| Console device driver READ entry point.
280+--------------------------------------------------------------------------+
281| Read characters from the I/O console. We only have stdin.
282+--------------------------------------------------------------------------*/
283rtems_device_driver
284console_read(rtems_device_major_number major,
285             rtems_device_minor_number minor,
286             void                      *arg)
287{
288  rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *)arg;
289  char                  *buffer  = rw_args->buffer;
290  int            count, maximum  = rw_args->count;
291
292  return rtems_termios_read (arg);
293} /* console_read */
294 
295
296/*-------------------------------------------------------------------------+
297| Console device driver WRITE entry point.
298+--------------------------------------------------------------------------+
299| Write characters to the I/O console. Stderr and stdout are the same.
300+--------------------------------------------------------------------------*/
301rtems_device_driver
302console_write(rtems_device_major_number major,
303              rtems_device_minor_number minor,
304              void                    * arg)
305{
306  rtems_libio_rw_args_t *rw_args = (rtems_libio_rw_args_t *)arg;
307  char                  *buffer  = rw_args->buffer;
308  int            count, maximum  = rw_args->count;
309
310  return rtems_termios_write (arg);
311 
312} /* console_write */
313
314
315 
316/*
317 * Handle ioctl request.
318 */
319rtems_device_driver
320console_control(rtems_device_major_number major,
321                rtems_device_minor_number minor,
322                void                      * arg
323)
324{
325  return rtems_termios_ioctl (arg);
326}
327
328static int
329conSetAttr(int minor, const struct termios *t)
330{
331  int baud;
332
333  switch (t->c_cflag & CBAUD)
334    {
335    case B50:   
336      baud = 50;
337      break;
338    case B75:   
339      baud = 75;       
340      break;
341    case B110: 
342      baud = 110;       
343      break;
344    case B134: 
345      baud = 134;       
346      break;
347    case B150: 
348      baud = 150;       
349      break;
350    case B200:
351      baud = 200;       
352      break;
353    case B300: 
354      baud = 300;
355      break;
356    case B600: 
357      baud = 600;       
358      break;
359    case B1200:
360      baud = 1200;
361      break;
362    case B1800:
363      baud = 1800;     
364      break;
365    case B2400:
366      baud = 2400;
367      break;
368    case B4800:
369      baud = 4800;
370      break;
371    case B9600:
372      baud = 9600;
373      break;
374    case B19200:
375      baud = 19200;
376      break;
377    case B38400:
378      baud = 38400;
379      break;
380    case B57600:       
381      baud = 57600;
382      break;
383    case B115200:
384      baud = 115200;
385      break;
386    default:
387      baud = 0;
388      rtems_fatal_error_occurred (RTEMS_INTERNAL_ERROR);
389      return 0;
390    }
391
392  BSP_uart_set_baud(BSPConsolePort, baud);
393
394  return 0;
395}
396
397
398
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