source: rtems/c/src/lib/libbsp/powerpc/mcp750/bootloader/misc.c @ ba46ffa6

4.104.114.84.95
Last change on this file since ba46ffa6 was ba46ffa6, checked in by Joel Sherrill <joel.sherrill@…>, on 06/14/99 at 16:51:13

This is a large patch from Eric Valette <valette@…> that was
described in the message following this paragraph. This patch also includes
a mcp750 BSP.

From valette@… Mon Jun 14 10:03:08 1999
Date: Tue, 18 May 1999 01:30:14 +0200 (CEST)
From: VALETTE Eric <valette@…>
To: joel@…
Cc: raguet@…, rtems-snapshots@…, valette@…
Subject: Questions/Suggestion? regarding RTEMS PowerPC code (long)

Dear knowledgeable RTEMS powerpc users,

As some of you may know, I'm currently finalizing a port
of RTEMS on a MCP750 Motorola board. I have done most
of it but have some questions to ask before submitting
the port.

In order to understand some of the changes I have made
or would like to make, maybe it is worth describing the
MCP750 Motorola board.

the MCP750 is a COMPACT PCI powerpc board with :

1) a MPC750 233 MHz processor,
2) a raven bus bridge/PCI controller that
implement an OPENPIC compliant interrupt controller,
3) a VIA 82C586 PCI/ISA bridge that offers a PC
compliant IO for keyboard, serial line, IDE, and
the well known PC 8259 cascaded PIC interrupt
architecture model,
4) a DEC 21140 Ethernet controller,
5) the PPCBUG Motorola firmware in flash,
6) A DEC PCI bridge,

This architecture is common to most Motorola 60x/7xx
board except that :

1) on VME board, the DEC PCI bridge is replaced by
a VME chipset,
2) the VIA 82C586 PCI/ISA bridge is replaced by
another bridge that is almost fully compatible
with the via bridge...

So the port should be a rather close basis for many
60x/7xx motorola board...

On this board, I already have ported Linux 2.2.3 and
use it both as a development and target board.

Now the questions/suggestions I have :

1) EXCEPTION CODE


As far as I know exceptions on PPC are handled like
interrupts. I dislike this very much as :

a) Except for the decrementer exception (and
maybe some other on mpc8xx), exceptions are
not recoverable and the handler just need to print
the full context and go to the firmware or debugger...
b) The interrupt switch is only necessary for the
decrementer and external interrupt (at least on
6xx,7xx).
c) The full context for exception is never saved and
thus cannot be used by debugger... I do understand
the most important for interrupts low level code
is to save the minimal context enabling to call C
code for performance reasons. On non recoverable
exception on the other hand, the most important is
to save the maximum information concerning proc status
in order to analyze the reason of the fault. At
least we will need this in order to implement the
port of RGDB on PPC

==> I wrote an API for connecting raw exceptions (and thus
raw interrupts) for mpc750. It should be valid for most
powerpc processors... I hope to find a way to make this coexist
with actual code layout. The code is actually located
in lib/libcpu/powerpc/mpc750 and is thus optional
(provided I write my own version of exec/score/cpu/powerpc/cpu.c ...)

See remark about files/directory layout organization in 4)

2) Current Implementation of ISR low level code


I do not understand why the MSR EE flags is cleared
again in exec/score/cpu/powerpc/irq_stubs.S

#if (PPC_USE_SPRG)

mfmsr r5
mfspr r6, sprg2

#else

lwz r6,msr_initial(r11)
lis r5,~PPC_MSR_DISABLE_MASK@ha
ori r5,r5,~PPC_MSR_DISABLE_MASK@l
and r6,r6,r5
mfmsr r5

#endif

Reading the doc, when a decrementer interrupt or an
external interrupt is active, the MSR EE flag is already
cleared. BTW if exception/interrupt could occur, it would
trash SRR0 and SRR1. In fact the code may be useful to set
MSR[RI] that re-enables exception processing. BTW I will need
to set other value in MSR to handle interrupts :

a) I want the MSR[IR] and MSR[DR] to be set for
performance reasons and also because I need DBAT
support to have access to PCI memory space as the
interrupt controller is in the PCI space.

Reading the code, I see others have the same kind of request :

/* SCE 980217

*

  • We need address translation ON when we call our ISR routine

mtmsr r5

*/

This is just another prof that even the lowest level
IRQ code is fundamentally board dependent and
not simply processor dependent especially when
the processor use external interrupt controller
because it has a single interrupt request line...

Note that if you look at the PPC code high level interrupt
handling code, as the "set_vector" routine that really connects
the interrupt is in the BSP/startup/genpvec.c,
the fact that IRQ handling is BSP specific is DE-FACTO
acknowledged.

I know I have already expressed this and understand that this
would require some heavy change in the code but believe
me you will reach a point where you will not be able
to find a compatible while optimum implementation for low level
interrupt handling code...) In my case this is already true...

So please consider removing low level IRQ handling from
exec/score/cpu/* and only let there exception handling code...
Exceptions are usually only processor dependent and do
not depend on external hardware mechanism to be masked or
acknowledged or re-enabled (there are probably exception but ...)

I have already done this for pc386 bsp but need to make it again.
This time I will even propose an API.

3) R2/R13 manipulation for EABI implementation


I do not understand the handling of r2 and r13 in the
EABI case. The specification for r2 says pointer to sdata2,
sbss2 section => constant. However I do not see -ffixed-r2
passed to any compilation system in make/custom/*
(for info linux does this on PPC).

So either this is a default compiler option when choosing
powerpc-rtems and thus we do not need to do anything with
this register as all the code is compiled with this compiler
and linked together OR this register may be used by rtems code
and then we do not need any special initialization or
handling.

The specification for r13 says pointer to the small data
area. r13 argumentation is the same except that as far
as I know the usage of the small data area requires
specific compiler support so that access to variables is
compiled via loading the LSB in a register and then
using r13 to get full address... It is like a small
memory model and it was present in IBM C compilers.

=> I propose to suppress any specific code for r2 and
r13 in the EABI case.

4) Code layout organization (yes again :-))


I think there are a number of design flaws in the way
the code is for ppc organized and I will try to point them out.
I have been beaten by this again on this new port, and
was beaten last year while modifying code for pc386.

a) exec/score/cpu/* vs lib/libcpu/cpu/*.

I think that too many things are put in exec/score/cpu that
have nothing to do with RTEMS internals but are rather
related to CPU feature.

This include at least :

a) registers access routine (e.g GET_MSR_Value),
b) interrupt masking/unmasking routines,
c) cache_mngt_routine,
d) mmu_mngt_routine,
e) Routines to connect the raw_exception, raw_interrupt
handler,

b) lib/libcpu/cpu/powerpc/*

With a processor family as exuberant as the powerpc family,
and their well known subtle differences (604 vs 750) or
unfortunately majors (8xx vs 60x) the directory structure
is fine (except maybe the names that are not homogeneous)

powerpc

ppc421 mpc821 ...

I only needed to add mpc750. But the fact that libcpu.a was not
produced was a pain and the fact that this organization may
duplicates code is also problematic.

So, except if the support of automake provides a better solution
I would like to propose something like this :

powerpc

mpc421 mpc821 ... mpc750 shared wrapup

with the following rules :

a) "shared" would act as a source container for sources that may
be shared among processors. Needed files would be compiled inside
the processor specific directory using the vpath Makefile
mechanism. "shared" may also contain compilation code
for routine that are really shared and not worth to inline...
(did not found many things so far as registers access routine
ARE WORTH INLINING)... In the case something is compiled there,
it should create libcpushared.a

b) layout under processor specific directory is free provided
that

1)the result of the compilation process exports :

libcpu/powerpc/"PROC"/*.h in $(PROJECT_INCLUDE)/libcpu

2) each processor specific directory creates
a library called libcpuspecific.a

Note that this organization enables to have a file that
is nearly the same than in shared but that must differ
because of processor differences...

c) "wrapup" should create libcpu.a using libcpushared.a
libcpuspecific.a and export it $(PROJECT_INCLUDE)/libcpu

The only thing I have no ideal solution is the way to put shared
definitions in "shared" and only processor specific definition
in "proc". To give a concrete example, most MSR bit definition
are shared among PPC processors and only some differs. if we create
a single msr.h in shared it will have ifdef. If in msr.h we
include libcpu/msr_c.h we will need to have it in each prowerpc
specific directory (even empty). Opinions are welcomed ...

Note that a similar mechanism exist in libbsp/i386 that also
contains a shared directory that is used by several bsp
like pc386 and i386ex and a similar wrapup mechanism...

NB: I have done this for mpc750 and other processors could just use
similar Makefiles...

c) The exec/score/cpu/powerpc directory layout.

I think the directory layout should be the same than the
libcpu/powerpc. As it is not, there are a lot of ifdefs
inside the code... And of course low level interrupt handling
code should be removed...

Besides that I do not understand why

1) things are compiled in the wrap directory,
2) some includes are moved to rtems/score,

I think the "preinstall" mechanism enables to put
everything in the current directory (or better in a per processor
directory),

5) Interrupt handling API


Again :-). But I think that using all the features the PIC
offers is a MUST for RT system. I already explained in the
prologue of this (long and probably boring) mail that the MCP750
boards offers an OPENPIC compliant architecture and that
the VIA 82586 PCI/ISA bridge offers a PC compatible IO and
PIC mapping. Here is a logical view of the RAVEN/VIA 82586
interrupt mapping :


| OPEN | <-----|8259|
| PIC | | | 2 ------
|(RAVEN)| | | <-----|8259|
| | | | | | 11
| | | | | | <----
| | | | | |
| | | | | |


------
| VIA PCI/ISA bridge
| x
-------- PCI interrupts

OPENPIC offers interrupt priorities among PCI interrupts
and interrupt selective masking. The 8259 offers the same kind
of feature. With actual powerpc interrupt code :

1) there is no way to specify priorities among
interrupts handler. This is REALLY a bad thing.
For me it is as importnat as having priorities
for threads...
2) for my implementation, each ISR should
contain the code that acknowledge the RAVEN
and 8259 cascade, modify interrupt mask on both
chips, and reenable interrupt at processor level,
..., restore then on interrupt return,.... This code
is actually similar to code located in some
genpvec.c powerpc files,
3) I must update _ISR_Nesting_level because
irq.inl use it...
4) the libchip code connects the ISR via set_vector
but the libchip handler code does not contain any code to
manipulate external interrupt controller hardware
in order to acknoledge the interrupt or re-enable
them (except for the target hardware of course)
So this code is broken unless set_vector adds an
additionnal prologue/epilogue before calling/returning
from in order to acknoledge/mask the raven and the
8259 PICS... => Anyway already EACH BSP MUST REWRITE
PART OF INTERRUPT HANDLING CODE TO CORRECTLY IMPLEMENT
SET_VECTOR.

I would rather offer an API similar to the one provided
in libbsp/i386/shared/irq/irq.h so that :

1) Once the driver supplied methods is called the
only things the ISR has to do is to worry about the
external hardware that triggered the interrupt.
Everything on openpic/VIA/processor would have been
done by the low levels (same things as set-vector)
2) The caller will need to supply the on/off/isOn
routine that are fundamental to correctly implements
debuggers/performance monitoring is a portable way
3) A globally configurable interrupt priorities
mechanism...

I have nothing against providing a compatible
set_vector just to make libchip happy but
as I have already explained in other
mails (months ago), I really think that the ISR
connection should be handled by the BSP and that no
code containing irq connection should exist the
rtems generic layers... Thus I really dislike
libchip on this aspect because in a long term
it will force to adopt the less reach API
for interrupt handling that exists (set_vector).

Additional note : I think the _ISR_Is_in_progress()
inline routine should be :

1) Put in a processor specific section,
2) Should not rely on a global variable,

As :

a) on symmetric MP, there is one interrupt level
per CPU,
b) On processor that have an ISP (e,g 68040),
this variable is useless (MSR bit testing could
be used)
c) On PPC, instead of using the address of the
variable via CPU_IRQ_info.Nest_level a dedicated
SPR could be used.

NOTE: most of this is also true for _Thread_Dispatch_disable_level

END NOTE


Please do not take what I said in the mail as a criticism for
anyone who submitted ppc code. Any code present helped me
a lot understanding PPC behavior. I just wanted by this
mail to :

1) try to better understand the actual code,
2) propose concrete ways of enhancing current code
by providing an alternative implementation for MCP750. I
will make my best effort to try to brake nothing but this
is actually hard due to the file layout organisation.
3) make understandable some changes I will probably make
if joel let me do them :-)

Any comments/objections are welcomed as usual.

--


/ ` Eric Valette

/-- o _. Canon CRF

(_, / (_(_( Rue de la touche lambert

35517 Cesson-Sevigne Cedex
FRANCE

Tel: +33 (0)2 99 87 68 91 Fax: +33 (0)2 99 84 11 30
E-mail: valette@…

  • Property mode set to 100644
File size: 13.9 KB
Line 
1/*
2 * arch/ppc/prepboot/misc.c
3 *
4 *  Copyright (C) 1998 Gabriel Paubert, paubert@iram.es
5 *
6 *  This file is based on arch/ppc/boot misc.c in previous versions of
7 * Linux/PPC but has been so extensively changed that only a few lines
8 * remain from the original.
9 *
10 *  This file is subject to the terms and conditions of the GNU General Public
11 *  License.  See the file COPYING in the main directory of this archive
12 *  for more details.
13 */
14
15#include <sys/types.h>
16#include <string.h>
17#include <libcpu/cpu.h>
18#include "bootldr.h"
19#include <libcpu/spr.h>
20#include "zlib.h"
21#include <libcpu/page.h>
22#include <libcpu/byteorder.h>
23
24SPR_RW(DEC)
25SPR_RO(PVR)
26
27struct inode;
28struct wait_queue;
29struct buffer_head;
30typedef struct { int counter; } atomic_t;
31
32
33typedef struct page {
34        /* these must be first (free area handling) */
35        struct page *next;
36        struct page *prev;
37        struct inode *inode;
38        unsigned long offset;
39        struct page *next_hash;
40        atomic_t count;
41        unsigned long flags;    /* atomic flags, some possibly updated asynchronously */
42        struct wait_queue *wait;
43        struct page **pprev_hash;
44        struct buffer_head * buffers;
45} mem_map_t;
46
47
48extern opaque mm_private, pci_private, v86_private, console_private;
49
50#define CONSOLE_ON_SERIAL       "console=ttyS0"
51
52extern struct console_io vacuum_console_functions;
53extern opaque log_console_setup, serial_console_setup, vga_console_setup;
54
55boot_data __bd = {0, 0, 0, 0, 0, 0, 0, 0,
56                  32, 0, 0, 0, 0, 0, 0,
57                  &mm_private,
58                  NULL,
59                  &pci_private,
60                  NULL,
61                  &v86_private,
62                  "root=/dev/hdc1"     
63                 };
64
65static void exit(void) __attribute__((noreturn));
66
67static void exit(void) {
68        printk("\nOnly way out is to press the reset button!\n");
69        asm volatile("": : :"memory");
70        while(1);
71}
72
73
74void hang(const char *s, u_long x, ctxt *p) {
75        u_long *r1;
76#ifdef DEBUG
77        print_all_maps("\nMemory mappings at exception time:\n");
78#endif
79        printk("%s %lx NIP: %p LR: %p\n"
80               "Callback trace (stack:return address)\n",
81               s, x, (void *) p->nip, (void *) p->lr);
82        asm volatile("lwz %0,0(1); lwz %0,0(%0); lwz %0,0(%0)": "=b" (r1));
83        while(r1) {
84                printk("  %p:%p\n", r1, (void *) r1[1]);
85                r1 = (u_long *) *r1;
86        }
87        exit();
88};
89
90
91void *zalloc(void *x, unsigned items, unsigned size)
92{
93        void *p = salloc(items*size);
94
95        if (!p) {
96                printk("oops... not enough memory for gunzip\n");
97        }
98        return p;
99}
100
101void zfree(void *x, void *addr, unsigned nb)
102{
103        sfree(addr);
104}
105
106#define HEAD_CRC        2
107#define EXTRA_FIELD     4
108#define ORIG_NAME       8
109#define COMMENT         0x10
110#define RESERVED        0xe0
111
112#define DEFLATED        8
113
114
115void gunzip(void *dst, int dstlen, unsigned char *src, int *lenp)
116{
117        z_stream s;
118        int r, i, flags;
119
120        /* skip header */
121        i = 10;
122        flags = src[3];
123        if (src[2] != DEFLATED || (flags & RESERVED) != 0) {
124                printk("bad gzipped data\n");
125                exit();
126        }
127        if ((flags & EXTRA_FIELD) != 0)
128                i = 12 + src[10] + (src[11] << 8);
129        if ((flags & ORIG_NAME) != 0)
130                while (src[i++] != 0)
131                        ;
132        if ((flags & COMMENT) != 0)
133                while (src[i++] != 0)
134                        ;
135        if ((flags & HEAD_CRC) != 0)
136                i += 2;
137        if (i >= *lenp) {
138                printk("gunzip: ran out of data in header\n");
139                exit();
140        }
141       
142        s.zalloc = zalloc;
143        s.zfree = zfree;
144        r = inflateInit2(&s, -MAX_WBITS);
145        if (r != Z_OK) {
146                printk("inflateInit2 returned %d\n", r);
147                exit();
148        }
149        s.next_in = src + i;
150        s.avail_in = *lenp - i;
151        s.next_out = dst;
152        s.avail_out = dstlen;
153        r = inflate(&s, Z_FINISH);
154        if (r != Z_OK && r != Z_STREAM_END) {
155                printk("inflate returned %d\n", r);
156                exit();
157        }
158        *lenp = s.next_out - (unsigned char *) dst;
159        inflateEnd(&s);
160}
161
162void decompress_kernel(int kernel_size, void * zimage_start, int len,
163                       void * initrd_start, int initrd_len ) {
164        u_char *parea;
165        RESIDUAL* rescopy;
166        int zimage_size= len;
167
168        /* That's a mess, we have to copy the residual data twice just in
169         * case it happens to be in the low memory area where the kernel
170         * is going to be unpacked. Later we have to copy it back to
171         * lower addresses because only the lowest part of memory is mapped
172         * during boot.
173         */
174        parea=__palloc(kernel_size, PA_LOW);
175        if(!parea) {
176                printk("Not enough memory to uncompress the kernel.");
177                exit();
178        }
179        /* Note that this clears the bss as a side effect, so some code
180         * with ugly special case for SMP could be removed from the kernel!
181         */
182        memset(parea, 0, kernel_size);
183        printk("\nUncompressing the kernel...\n");
184        rescopy=salloc(sizeof(RESIDUAL));
185        /* Let us hope that residual data is aligned on word boundary */
186        *rescopy =  *bd->residual;
187        bd->residual = (void *)PAGE_ALIGN(kernel_size);
188
189        gunzip(parea, kernel_size, zimage_start, &zimage_size);
190
191        bd->of_entry = 0;
192        bd->load_address = 0;
193        bd->r6 = (char *)bd->residual+PAGE_ALIGN(sizeof(RESIDUAL));
194        bd->r7 = bd->r6+strlen(bd->cmd_line);
195        if ( initrd_len ) {
196                /* We have to leave some room for the hash table and for the
197                 * whole array of struct page. The hash table would be better
198                 * located at the end of memory if possible. With some bridges
199                 * DMA from the last pages of memory is slower because
200                 * prefetching from PCI has to be disabled to avoid accessing
201                 * non existing memory. So it is the ideal place to put the
202                 * hash table.
203                 */
204                unsigned tmp = rescopy->TotalMemory;
205                /* It's equivalent to tmp & (-tmp), but using the negation
206                 * operator on unsigned variables looks so ugly.
207                 */
208                if ((tmp & (~tmp+1)) != tmp) tmp <<= 1; /* Next power of 2 */
209                tmp /= 256; /* Size of hash table */
210                if (tmp> (2<<20)) tmp=2<<20;
211                tmp = tmp*2 + 0x40000; /* Alignment can double size + 256 kB */
212                tmp += (rescopy->TotalMemory / PAGE_SIZE)
213                               * sizeof(struct page);
214                bd->load_address = (void *)PAGE_ALIGN((int)bd->r7 + tmp);
215                bd->of_entry = (char *)bd->load_address+initrd_len;
216        }
217#ifdef DEBUG
218        printk("Kernel at 0x%p, size=0x%x\n", NULL, kernel_size);
219        printk("Initrd at 0x%p, size=0x%x\n",bd->load_address, initrd_len);
220        printk("Residual data at 0x%p\n", bd->residual);
221        printk("Command line at 0x%p\n",bd->r6);
222#endif
223        printk("done\nNow booting...\n");
224        MMUoff();       /* We need to access address 0 ! */
225        codemove(0, parea, kernel_size, bd->cache_lsize);
226        codemove(bd->residual, rescopy, sizeof(RESIDUAL), bd->cache_lsize);
227        codemove(bd->r6, bd->cmd_line, sizeof(bd->cmd_line), bd->cache_lsize);
228        /* codemove checks for 0 length */
229        codemove(bd->load_address, initrd_start, initrd_len, bd->cache_lsize);
230}
231
232void
233setup_hw(void)
234{
235        char *cp, ch;
236        register RESIDUAL * res;
237        /* PPC_DEVICE * nvram; */
238        struct pci_dev *p, *default_vga;
239        int timer, err;
240        u_short default_vga_cmd;
241        static unsigned int indic;
242       
243        indic = 0;
244       
245        res=bd->residual;
246        default_vga=NULL;
247        default_vga_cmd = 0;
248
249#define vpd res->VitalProductData
250        if (_read_PVR()>>16 != 1) {
251                if ( res && vpd.ProcessorBusHz ) {
252                        ticks_per_ms = vpd.ProcessorBusHz/
253                            (vpd.TimeBaseDivisor ? vpd.TimeBaseDivisor : 4000);
254                } else {
255                        ticks_per_ms = 16500; /* assume 66 MHz on bus */
256                }
257        }
258       
259        select_console(CONSOLE_LOG);
260
261        /* We check that the keyboard is present and immediately
262         * select the serial console if not.
263         */
264        err = kbdreset();
265        if (err) select_console(CONSOLE_SERIAL);
266
267        printk("\nModel: %s\nSerial: %s\n"
268               "Processor/Bus frequencies (Hz): %ld/%ld\n"
269               "Time Base Divisor: %ld\n"
270               "Memory Size: %x\n",
271               vpd.PrintableModel,
272               vpd.Serial,
273               vpd.ProcessorHz,
274               vpd.ProcessorBusHz,
275               (vpd.TimeBaseDivisor ? vpd.TimeBaseDivisor : 4000),
276               res->TotalMemory);
277        printk("Original MSR: %lx\nOriginal HID0: %lx\nOriginal R31: %lx\n",
278               bd->o_msr, bd->o_hid0, bd->o_r31);
279
280        /* This reconfigures all the PCI subsystem */
281        pci_init();
282       
283        /* The Motorola NT firmware does not set the correct mem size */
284        if ( vpd.FirmwareSupplier == 0x10000 ) {
285                int memsize;
286                memsize = find_max_mem(bd->pci_devices);
287                if ( memsize != res->TotalMemory ) {
288                        printk("Changed Memory size from %lx to %x\n",
289                                res->TotalMemory, memsize);
290                        res->TotalMemory = memsize;
291                        res->GoodMemory = memsize;
292                }
293        }
294#define ENABLE_VGA_USAGE
295#undef ENABLE_VGA_USAGE
296#ifdef ENABLE_VGA_USAGE
297        /* Find the primary VGA device, chosing the first one found
298         * if none is enabled. The basic loop structure has been copied
299         * from linux/drivers/char/bttv.c by Alan Cox.
300         */
301        for (p = bd->pci_devices; p; p = p->next) {
302                u_short cmd;
303                if (p->class != PCI_CLASS_NOT_DEFINED_VGA &&
304                    ((p->class) >> 16 != PCI_BASE_CLASS_DISPLAY))
305                        continue;
306                if (p->bus->number != 0) {
307                        printk("VGA device not on bus 0 not initialized!\n");
308                        continue;
309                }
310                /* Only one can be active in text mode, which for now will
311                 * be assumed as equivalent to having I/O response enabled.
312                 */
313                pci_read_config_word(p, PCI_COMMAND, &cmd);
314                if(cmd & PCI_COMMAND_IO || !default_vga) {
315                        default_vga=p;
316                        default_vga_cmd=cmd;
317                }
318        }
319
320        /* Disable the enabled VGA device, if any. */
321        if (default_vga)
322                pci_write_config_word(default_vga, PCI_COMMAND,
323                                      default_vga_cmd&
324                                      ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
325        init_v86();
326        /* Same loop copied from bttv.c, this time doing the serious work */
327        for (p = bd->pci_devices; p; p = p->next) {
328                u_short cmd;
329                if (p->class != PCI_CLASS_NOT_DEFINED_VGA &&
330                    ((p->class) >> 16 != PCI_BASE_CLASS_DISPLAY))
331                        continue;
332                if (p->bus->number != 0) continue;
333                pci_read_config_word(p, PCI_COMMAND, &cmd);
334                pci_write_config_word(p, PCI_COMMAND,
335                                      cmd|PCI_COMMAND_IO|PCI_COMMAND_MEMORY);
336                printk("Calling the emulator.\n");
337                em86_main(p);
338                pci_write_config_word(p, PCI_COMMAND, cmd);
339        }       
340
341        cleanup_v86_mess();
342#endif 
343        /* Reenable the primary VGA device */
344        if (default_vga) {
345                pci_write_config_word(default_vga, PCI_COMMAND,
346                                      default_vga_cmd|
347                                      (PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
348                if (err) {
349                        printk("Keyboard error %d, using serial console!\n",
350                               err);
351                } else {
352                        select_console(CONSOLE_VGA);
353                }
354        } else if (!err) {
355                select_console(CONSOLE_SERIAL);
356                if (bd->cmd_line[0] == '\0') {
357                  strcat(&bd->cmd_line[0], CONSOLE_ON_SERIAL);
358                }
359                else {
360                  int s = strlen (bd->cmd_line);
361                  bd->cmd_line[s + 1] = ' ';
362                  bd->cmd_line[s + 2] = '\0';
363                  strcat(&bd->cmd_line[0], CONSOLE_ON_SERIAL);
364                }
365        }
366#if 0
367        /* In the future we may use the NVRAM to store default
368         * kernel parameters.
369         */
370        nvram=residual_find_device(~0UL, NULL, SystemPeripheral, NVRAM,
371                                   ~0UL, 0);
372        if (nvram) {
373                PnP_TAG_PACKET * pkt;
374                switch (nvram->DevId.Interface) {       
375                case IndirectNVRAM:
376                          pkt=PnP_find_packet(res->DevicePnpHeap
377                                      +nvram->AllocatedOffset,
378                                              )
379                }
380        }
381#endif
382
383        printk("\nRTEMS 4.x/PPC load: ");
384        timer = 0;
385        cp = bd->cmd_line+strlen(bd->cmd_line);
386        while (timer++ < 5*1000) {
387                if (debug_tstc()) {
388                        while ((ch = debug_getc()) != '\n' && ch != '\r') {
389                                if (ch == '\b' || ch == 0177) {
390                                        if (cp != bd->cmd_line) {
391                                                cp--;
392                                                printk("\b \b");
393                                        }
394                                } else {
395                                        *cp++ = ch;
396                                        debug_putc(ch);
397                                }
398                        }
399                        break;  /* Exit 'timer' loop */
400                }
401                udelay(1000);  /* 1 msec */
402        }
403        *cp = 0;
404}
405
406
407/* Functions to deal with the residual data */
408static int same_DevID(unsigned short vendor,
409               unsigned short Number,
410               char * str)
411{
412        static unsigned const char hexdigit[]="0123456789ABCDEF";
413        if (strlen(str)!=7) return 0;
414        if ( ( ((vendor>>10)&0x1f)+'A'-1 == str[0])  &&
415             ( ((vendor>>5)&0x1f)+'A'-1 == str[1])   &&
416             ( (vendor&0x1f)+'A'-1 == str[2])        &&
417             (hexdigit[(Number>>12)&0x0f] == str[3]) &&
418             (hexdigit[(Number>>8)&0x0f] == str[4])  &&
419             (hexdigit[(Number>>4)&0x0f] == str[5])  &&
420             (hexdigit[Number&0x0f] == str[6]) ) return 1;
421        return 0;
422}
423
424PPC_DEVICE *residual_find_device(unsigned long BusMask,
425                         unsigned char * DevID,
426                         int BaseType,
427                         int SubType,
428                         int Interface,
429                         int n)
430{
431        int i;
432        RESIDUAL *res = bd->residual;
433        if ( !res || !res->ResidualLength ) return NULL;
434        for (i=0; i<res->ActualNumDevices; i++) {
435#define Dev res->Devices[i].DeviceId
436                if ( (Dev.BusId&BusMask)                                  &&
437                     (BaseType==-1 || Dev.BaseType==BaseType)             &&
438                     (SubType==-1 || Dev.SubType==SubType)                &&
439                     (Interface==-1 || Dev.Interface==Interface)          &&
440                     (DevID==NULL || same_DevID((Dev.DevId>>16)&0xffff,
441                                                Dev.DevId&0xffff, DevID)) &&
442                     !(n--) ) return res->Devices+i;
443#undef Dev
444        }
445        return 0;
446}
447
448PnP_TAG_PACKET *PnP_find_packet(unsigned char *p,
449                                unsigned packet_tag,
450                                int n)
451{
452        unsigned mask, masked_tag, size;
453        if(!p) return 0;
454        if (tag_type(packet_tag)) mask=0xff; else mask=0xF8;
455        masked_tag = packet_tag&mask;
456        for(; *p != END_TAG; p+=size) {
457                if ((*p & mask) == masked_tag && !(n--))
458                        return (PnP_TAG_PACKET *) p;
459                if (tag_type(*p))
460                        size=ld_le16((unsigned short *)(p+1))+3;
461                else
462                        size=tag_small_count(*p)+1;
463        }
464        return 0; /* not found */
465}
466
467PnP_TAG_PACKET *PnP_find_small_vendor_packet(unsigned char *p,
468                                             unsigned packet_type,
469                                             int n)
470{
471        int next=0;
472        while (p) {
473                p = (unsigned char *) PnP_find_packet(p, 0x70, next);
474                if (p && p[1]==packet_type && !(n--))
475                        return (PnP_TAG_PACKET *) p;
476                next = 1;
477        };
478        return 0; /* not found */
479}
480
481PnP_TAG_PACKET *PnP_find_large_vendor_packet(unsigned char *p,
482                                           unsigned packet_type,
483                                           int n)
484{
485        int next=0;
486        while (p) {
487                p = (unsigned char *) PnP_find_packet(p, 0x84, next);
488                if (p && p[3]==packet_type && !(n--))
489                        return (PnP_TAG_PACKET *) p;
490                next = 1;
491        };
492        return 0; /* not found */
493}
494
495/* Find out the amount of installed memory. For MPC105 and IBM 660 this
496 * can be done by finding the bank with the highest memory ending address
497 */
498int
499find_max_mem( struct pci_dev *dev )
500{
501        u_char banks,tmp;
502        int i, top, max;
503
504        max = 0;
505        for ( ; dev; dev = dev->next) {
506                if ( ((dev->vendor == PCI_VENDOR_ID_MOTOROLA) &&
507                      (dev->device == PCI_DEVICE_ID_MOTOROLA_MPC105)) ||
508                     ((dev->vendor == PCI_VENDOR_ID_IBM) &&
509                      (dev->device == 0x0037/*IBM 660 Bridge*/)) ) {
510                        pci_read_config_byte(dev, 0xa0, &banks);
511                        for (i = 0; i < 8; i++) {
512                                if ( banks & (1<<i) ) {
513                                        pci_read_config_byte(dev, 0x90+i, &tmp);
514                                        top = tmp;
515                                        pci_read_config_byte(dev, 0x98+i, &tmp);
516                                        top |= (tmp&3)<<8;
517                                        if ( top > max ) max = top;
518                                }
519                        }
520                        if ( max ) return ((max+1)<<20);
521                        else return(0);
522                }
523        }
524        return(0);
525}
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