| 1 | /* start.S |
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| 2 | * |
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| 3 | * This file contains the entry veneer for RTEMS programs |
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| 4 | * on the MBX8xx board. |
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| 5 | * It jumps to the BSP which is responsible for performing |
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| 6 | * all remaining initialization. |
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| 7 | * |
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| 8 | * This file is based on several others: |
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| 9 | * |
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| 10 | * (1) start360.s from the gen68360 BSP by |
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| 11 | * W. Eric Norum (eric@skatter.usask.ca) |
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| 12 | * with the following copyright and license: |
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| 13 | * |
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| 14 | * COPYRIGHT (c) 1989-1998. |
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| 15 | * On-Line Applications Research Corporation (OAR). |
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| 16 | * Copyright assigned to U.S. Government, 1994. |
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| 17 | * |
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| 18 | * The license and distribution terms for this file may in |
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| 19 | * the file LICENSE in this distribution or at |
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| 20 | * http://www.OARcorp.com/rtems/license.html. |
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| 21 | * |
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| 22 | * (2) start.s for the eth_comm port by |
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| 23 | * Jay Monkman (jmonkman@fracsa.com), |
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| 24 | * which itself is based on the |
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| 25 | * |
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| 26 | * (3) dlentry.s for the Papyrus BSP, written by: |
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| 27 | * Andrew Bray <andy@i-cubed.co.uk> |
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| 28 | * with the following copyright and license: |
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| 29 | * |
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| 30 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 31 | * |
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| 32 | * (4) start860.S for the MBX821/MBX860, written by: |
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| 33 | * Darlene A. Stewart <darlene.stewart@iit.nrc.ca> |
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| 34 | * Copyright (c) 1999, National Research Council of Canada |
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| 35 | * |
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| 36 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 37 | * without any express or implied warranty: |
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| 38 | * permission to use, copy, modify, and distribute this file |
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| 39 | * for any purpose is hereby granted without fee, provided that |
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| 40 | * the above copyright notice and this notice appears in all |
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| 41 | * copies, and that the name of i-cubed limited not be used in |
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| 42 | * advertising or publicity pertaining to distribution of the |
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| 43 | * software without specific, written prior permission. |
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| 44 | * i-cubed limited makes no representations about the suitability |
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| 45 | * of this software for any purpose. |
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| 46 | * |
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| 47 | * Modifications (for MBX8xx) of respective RTEMS files: |
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| 48 | * Copyright (c) 1999, National Research Council of Canada |
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| 49 | */ |
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| 50 | |
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| 51 | #include "asm.h" |
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| 52 | |
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| 53 | /* |
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| 54 | * The initial stack is set to run BELOW the code base address. |
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| 55 | * (between the vectors and text sections) |
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| 56 | * |
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| 57 | * All the entry veneer has to do is to clear the BSS. |
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| 58 | */ |
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| 59 | |
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| 60 | /* |
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| 61 | * GDB likes to have debugging information for the entry veneer. |
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| 62 | * Play compiler and provide some DWARF information. |
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| 63 | * |
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| 64 | * CHANGE TO SUIT YOUR SETUP! |
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| 65 | */ |
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| 66 | |
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| 67 | .section .entry,"ax",@progbits |
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| 68 | .L_text_b: |
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| 69 | .L_LC1: |
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| 70 | .previous |
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| 71 | |
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| 72 | .section .debug_sfnames |
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| 73 | .L_sfnames_b: |
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| 74 | .byte "rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/" |
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| 75 | .byte 0 |
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| 76 | .L_F0: |
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| 77 | .byte "start.S" |
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| 78 | .byte 0 |
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| 79 | .previous |
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| 80 | |
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| 81 | .section .line |
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| 82 | .L_line_b: |
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| 83 | .4byte .L_line_e-.L_line_b |
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| 84 | .4byte .L_text_b |
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| 85 | .L_LE1: |
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| 86 | .L_line_last: |
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| 87 | .4byte 0x0 |
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| 88 | .2byte 0xffff |
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| 89 | .4byte .L_text_e-.L_text_b |
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| 90 | .L_line_e: |
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| 91 | .previous |
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| 92 | |
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| 93 | .section .debug_srcinfo |
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| 94 | .L_srcinfo_b: |
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| 95 | .4byte .L_line_b |
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| 96 | .4byte .L_sfnames_b |
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| 97 | .4byte .L_text_b |
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| 98 | .4byte .L_text_e |
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| 99 | .4byte 0xffffffff |
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| 100 | .4byte .L_LE1-.L_line_b |
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| 101 | .4byte .L_F0-.L_sfnames_b |
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| 102 | .4byte .L_line_last-.L_line_b |
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| 103 | .4byte 0xffffffff |
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| 104 | .previous |
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| 105 | |
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| 106 | .section .debug_pubnames |
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| 107 | .4byte .L_debug_b |
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| 108 | .4byte .L_P0 |
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| 109 | .byte "start" |
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| 110 | .byte 0 |
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| 111 | .4byte 0x0 |
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| 112 | .byte 0 |
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| 113 | .previous |
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| 114 | |
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| 115 | .section .debug_aranges |
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| 116 | .4byte .L_debug_b |
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| 117 | .4byte .L_text_b |
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| 118 | .4byte .L_text_e-.L_text_b |
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| 119 | .4byte 0 |
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| 120 | .4byte 0 |
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| 121 | .4byte 0 |
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| 122 | .4byte 0 |
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| 123 | .4byte 0 |
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| 124 | .4byte 0 |
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| 125 | .4byte 0x0 |
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| 126 | .4byte 0x0 |
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| 127 | .previous |
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| 128 | |
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| 129 | .section .debug |
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| 130 | .L_debug_b: |
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| 131 | .L_D1: |
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| 132 | .4byte .L_D1_e-.L_D1 |
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| 133 | .2byte 0x11 /* TAG_compile_unit */ |
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| 134 | .2byte 0x12 /* AT_sibling */ |
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| 135 | .4byte .L_D2 |
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| 136 | .2byte 0x38 /* AT_name */ |
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| 137 | .byte "start.S" |
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| 138 | .byte 0 |
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| 139 | .2byte 0x258 /* AT_producer */ |
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| 140 | .byte "GAS 2.5.2" |
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| 141 | .byte 0 |
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| 142 | .2byte 0x111 /* AT_low_pc */ |
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| 143 | .4byte .L_text_b |
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| 144 | .2byte 0x121 /* AT_high_pc */ |
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| 145 | .4byte .L_text_e |
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| 146 | .2byte 0x106 /* AT_stmt_list */ |
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| 147 | .4byte .L_line_b |
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| 148 | .2byte 0x1b8 /* AT_comp_dir */ |
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| 149 | .byte "rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/" |
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| 150 | .byte 0 |
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| 151 | .2byte 0x8006 /* AT_sf_names */ |
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| 152 | .4byte .L_sfnames_b |
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| 153 | .2byte 0x8016 /* AT_src_info */ |
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| 154 | .4byte .L_srcinfo_b |
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| 155 | .L_D1_e: |
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| 156 | .L_P0: |
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| 157 | .L_D3: |
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| 158 | .4byte .L_D3_e-.L_D3 |
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| 159 | .2byte 0x6 /* TAG_global_subroutine */ |
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| 160 | .2byte 0x12 /* AT_sibling */ |
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| 161 | .4byte .L_D4 |
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| 162 | .2byte 0x38 /* AT_name */ |
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| 163 | .byte "start" |
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| 164 | .byte 0 |
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| 165 | .2byte 0x278 /* AT_prototyped */ |
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| 166 | .byte 0 |
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| 167 | .2byte 0x111 /* AT_low_pc */ |
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| 168 | .4byte .L_text_b |
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| 169 | .2byte 0x121 /* AT_high_pc */ |
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| 170 | .4byte .L_text_e |
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| 171 | .2byte 0x8041 /* AT_body_begin */ |
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| 172 | .4byte .L_text_b |
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| 173 | .2byte 0x8051 /* AT_body_end */ |
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| 174 | .4byte .L_text_e |
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| 175 | .L_D3_e: |
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| 176 | |
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| 177 | .L_D4: |
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| 178 | .4byte .L_D4_e-.L_D4 |
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| 179 | .align 2 |
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| 180 | .L_D4_e: |
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| 181 | .L_D2: |
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| 182 | .previous |
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| 183 | |
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| 184 | /* |
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| 185 | * Tell C's eabi-ctor's that we have an atexit function, |
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| 186 | * and that it is to register __do_global_dtors. |
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| 187 | */ |
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| 188 | EXTERN_PROC(atexit) |
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| 189 | PUBLIC_VAR(__atexit) |
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| 190 | .section ".sdata","aw" |
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| 191 | .align 2 |
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| 192 | SYM(__atexit): |
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| 193 | EXT_PROC_REF(atexit)@fixup |
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| 194 | .previous |
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| 195 | |
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| 196 | .section ".fixup","aw" |
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| 197 | .align 2 |
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| 198 | EXT_SYM_REF(__atexit) |
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| 199 | .previous |
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| 200 | |
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| 201 | /* That should do it */ |
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| 202 | |
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| 203 | /* |
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| 204 | * Put the entry point in its own section. That way, we can guarantee |
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| 205 | * to put it first in the .text section in the linker script. |
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| 206 | */ |
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| 207 | .section .entry |
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| 208 | |
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| 209 | PUBLIC_VAR (start) |
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| 210 | SYM(start): |
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| 211 | bl .startup /* or bl .spin */ |
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| 212 | base_addr: |
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| 213 | |
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| 214 | /* |
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| 215 | * Parameters from linker |
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| 216 | */ |
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| 217 | toc_pointer: |
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| 218 | .long __GOT_START__ |
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| 219 | bss_length: |
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| 220 | .long bss.size |
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| 221 | bss_addr: |
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| 222 | .long bss.start |
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| 223 | |
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| 224 | PUBLIC_VAR (text_addr) |
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| 225 | text_addr: |
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| 226 | .long text.start |
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| 227 | |
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| 228 | PUBLIC_VAR (text_length) |
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| 229 | text_length: |
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| 230 | .long text.size |
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| 231 | |
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| 232 | /* |
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| 233 | * Spin, if necessary, to acquire control from debugger (CodeWarrior). |
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| 234 | */ |
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| 235 | spin: |
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| 236 | .long 0x0001 |
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| 237 | .spin: |
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| 238 | lis r3, spin@ha |
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| 239 | lwz r3, spin@l(r3) |
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| 240 | cmpwi r3, 0x1 |
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| 241 | beq .spin |
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| 242 | |
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| 243 | /* |
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| 244 | * Initialization code |
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| 245 | */ |
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| 246 | .startup: |
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| 247 | /* Get the start address. */ |
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| 248 | mflr r1 |
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| 249 | |
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| 250 | /* Initialize essential registers. */ |
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| 251 | bl initregs |
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| 252 | nop |
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| 253 | |
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| 254 | /* |
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| 255 | * C_setup. |
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| 256 | */ |
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| 257 | |
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| 258 | /* set toc */ |
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| 259 | lwz r2, toc_pointer-base_addr(r1) |
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| 260 | |
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| 261 | /* Set up stack pointer = beginning of text section - 56 */ |
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| 262 | addi r1, r1, -56-4 |
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| 263 | |
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| 264 | /* Initialize the memory mapped MPC821 registers (done in C). */ |
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| 265 | EXTERN_PROC (_InitMBX8xx) |
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| 266 | bl PROC (_InitMBX8xx) |
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| 267 | nop |
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| 268 | |
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| 269 | /* Clear the bss section. */ |
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| 270 | bl bssclr |
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| 271 | nop |
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| 272 | |
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| 273 | /* clear argc and argv */ |
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| 274 | xor r3, r3, r3 |
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| 275 | xor r4, r4, r4 |
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| 276 | |
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| 277 | EXTERN_PROC (boot_card) |
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| 278 | bl PROC (boot_card) /* call the first C routine */ |
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| 279 | nop |
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| 280 | |
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| 281 | /* we should never return from boot_card, but in case we do ... */ |
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| 282 | /* The next instructions are dependent on your runtime environment */ |
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| 283 | |
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| 284 | /* Return to EPPCBug */ |
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| 285 | lis r10, 0x0400 /* Data cache disable */ |
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| 286 | mtspr 568, r10 |
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| 287 | isync |
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| 288 | |
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| 289 | mtspr 560, r10 /* Instruction cache disable */ |
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| 290 | isync |
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| 291 | |
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| 292 | stop_here: |
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| 293 | li r10, 0x0F00 /* .RETURN */ |
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| 294 | sc |
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| 295 | |
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| 296 | b stop_here |
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| 297 | nop |
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| 298 | |
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| 299 | /* |
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| 300 | * bssclr - zero out bss |
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| 301 | */ |
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| 302 | bssclr: |
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| 303 | lis r3, base_addr@ha |
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| 304 | addi r3, r3, base_addr@l |
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| 305 | lwz r4, bss_addr-base_addr(r3) /* Start of bss */ |
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| 306 | lwz r5, bss_length-base_addr(r3) /* Length of bss */ |
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| 307 | |
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| 308 | rlwinm. r5,r5,30,0x3FFFFFFF /* form length/4 */ |
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| 309 | beqlr /* no bss - return */ |
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| 310 | mtctr r5 /* set ctr reg */ |
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| 311 | |
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| 312 | li r5,0x0000 /* r5 = 0 */ |
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| 313 | clear_bss: |
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| 314 | stw r5,0(r4) /* store r6 */ |
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| 315 | addi r4,r4,0x4 /* update r4 */ |
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| 316 | bdnz clear_bss /* dec counter and loop */ |
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| 317 | |
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| 318 | blr /* return */ |
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| 319 | |
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| 320 | /* |
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| 321 | * initregs |
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| 322 | * Initialize the MSR and basic core PowerPC registers |
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| 323 | * |
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| 324 | * Register usage: |
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| 325 | * r0 - scratch |
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| 326 | */ |
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| 327 | initregs: |
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| 328 | /* |
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| 329 | * Disable address translation. We should already be running in real space, |
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| 330 | * so this should be a no-op, i.e. no need to switch instruction stream |
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| 331 | * addresses from virtual space to real space. Other bits set the processor |
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| 332 | * for big-endian mode, exceptions vectored to 0x000n_nnnn (vectors are |
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| 333 | * already in low memory!), no execution tracing, machine check exceptions |
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| 334 | * enabled, floating-point not available (MPC8xx has none), supervisor |
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| 335 | * priviledge level, external interrupts disabled, power management |
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| 336 | * disabled (normal operation mode). |
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| 337 | */ |
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| 338 | li r0, 0x1000 /* MSR_ME */ |
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| 339 | mtmsr r0 /* Context-synchronizing */ |
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| 340 | isync |
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| 341 | |
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| 342 | /* |
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| 343 | * Clear the exception handling registers. |
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| 344 | * Note SPRG3 is reserved for use by EPPCBug on the MBX8xx. |
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| 345 | */ |
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| 346 | li r0, 0x0000 |
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| 347 | mtdar r0 |
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| 348 | mtspr sprg0, r0 |
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| 349 | mtspr sprg1, r0 |
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| 350 | mtspr sprg2, r0 |
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| 351 | mtspr srr0, r0 |
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| 352 | mtspr srr1, r0 |
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| 353 | |
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| 354 | mr r6, r0 |
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| 355 | mr r7, r0 |
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| 356 | mr r8, r0 |
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| 357 | mr r9, r0 |
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| 358 | mr r10, r0 |
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| 359 | mr r11, r0 |
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| 360 | mr r12, r0 |
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| 361 | mr r13, r0 |
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| 362 | mr r14, r0 |
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| 363 | mr r15, r0 |
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| 364 | mr r16, r0 |
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| 365 | mr r17, r0 |
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| 366 | mr r18, r0 |
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| 367 | mr r19, r0 |
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| 368 | mr r20, r0 |
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| 369 | mr r21, r0 |
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| 370 | mr r22, r0 |
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| 371 | mr r23, r0 |
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| 372 | mr r24, r0 |
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| 373 | mr r25, r0 |
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| 374 | mr r26, r0 |
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| 375 | mr r27, r0 |
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| 376 | mr r28, r0 |
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| 377 | mr r29, r0 |
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| 378 | mr r30, r0 |
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| 379 | mr r31, r0 |
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| 380 | |
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| 381 | blr /* return */ |
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| 382 | |
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| 383 | .L_text_e: |
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