1 | /* |
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2 | * mmutlbtab.c |
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3 | * |
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4 | * This file defines the MMU_TLB_table for the MBX8xx. |
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5 | * |
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6 | * Copyright (c) 1999, National Research Council of Canada |
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7 | * |
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8 | * The license and distribution terms for this file may be |
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9 | * found in the file LICENSE in this distribution or at |
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10 | * http://www.OARcorp.com/rtems/license.html. |
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11 | */ |
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12 | |
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13 | #include <bsp.h> |
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14 | #include <mpc8xx/mmu.h> |
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15 | |
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16 | /* |
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17 | * This MMU_TLB_table is used to statically initialize the Table Lookaside |
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18 | * Buffers in the MMU of the MBX8xx board. |
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19 | * |
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20 | * We initialize the entries in both the instruction and data TLBs |
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21 | * with the same values - a few bits relevant to the data TLB are unused |
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22 | * in the instruction TLB. |
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23 | * |
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24 | * An Effective Page Number (EPN), Tablewalk Control Register (TWC) and |
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25 | * Real Page Number (RPN) value are supplied in the table for each TLB entry. |
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26 | * |
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27 | * The instruction and data TLBs each can hold 32 entries, so _TLB_Table must |
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28 | * not have more than 32 lines in it! |
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29 | * |
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30 | * We set up the virtual memory map so that virtual address of a |
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31 | * location is equal to its real address. |
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32 | */ |
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33 | MMU_TLB_table_t MMU_TLB_table[] = { |
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34 | #if ( defined(mbx860_001b) ) |
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35 | /* |
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36 | * DRAM: CS1, Start address 0x00000000, 2M, |
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37 | * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, |
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38 | * R/W,X for all, no ASID comparison, not cache-inhibited. |
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39 | * Last 512K block is cache-inhibited, but not guarded for use by EPPCBug. |
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40 | * EPN TWC RPN |
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41 | */ |
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42 | { 0x00000200, 0x05, 0x000009FD }, /* DRAM - PS=512K */ |
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43 | { 0x00080200, 0x05, 0x000809FD }, /* DRAM - PS=512K */ |
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44 | { 0x00100200, 0x05, 0x001009FD }, /* DRAM - PS=512K */ |
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45 | { 0x00180200, 0x05, 0x001809FF }, /* DRAM - PS=512K, cache-inhibited */ |
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46 | #elif ( defined(mbx860_002b) || \ |
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47 | defined(mbx860_003b) || \ |
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48 | defined(mbx821_001b) || \ |
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49 | defined(mbx821_002b) || \ |
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50 | defined(mbx821_003b) || \ |
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51 | defined(mbx860_001) || \ |
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52 | defined(mbx860_002) || \ |
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53 | defined(mbx860_003) || \ |
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54 | defined(mbx821_001) || \ |
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55 | defined(mbx821_002) || \ |
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56 | defined(mbx821_003) ) |
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57 | /* |
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58 | * DRAM: CS1, Start address 0x00000000, 4M, |
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59 | * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, |
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60 | * R/W,X for all, no ASID comparison, not cache-inhibited. |
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61 | * Last 512K block is cache-inhibited, but not guarded for use by EPPCBug. |
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62 | * EPN TWC RPN |
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63 | */ |
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64 | { 0x00000200, 0x05, 0x000009FD }, /* DRAM - PS=512K */ |
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65 | { 0x00080200, 0x05, 0x000809FD }, /* DRAM - PS=512K */ |
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66 | { 0x00100200, 0x05, 0x001009FD }, /* DRAM - PS=512K */ |
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67 | { 0x00180200, 0x05, 0x001809FD }, /* DRAM - PS=512K */ |
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68 | { 0x00200200, 0x05, 0x002009FD }, /* DRAM - PS=512K */ |
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69 | { 0x00280200, 0x05, 0x002809FD }, /* DRAM - PS=512K */ |
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70 | { 0x00300200, 0x05, 0x003009FD }, /* DRAM - PS=512K */ |
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71 | { 0x00380200, 0x05, 0x003809FF }, /* DRAM - PS=512K, cache-inhibited */ |
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72 | #elif ( defined(mbx860_004) || \ |
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73 | defined(mbx860_005) || \ |
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74 | defined(mbx860_004b) || \ |
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75 | defined(mbx860_005b) || \ |
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76 | defined(mbx860_006b) || \ |
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77 | defined(mbx821_004) || \ |
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78 | defined(mbx821_005) || \ |
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79 | defined(mbx821_004b) || \ |
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80 | defined(mbx821_005b) || \ |
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81 | defined(mbx821_006b) ) |
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82 | /* |
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83 | * DRAM: CS1, Start address 0x00000000, 16M, |
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84 | * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, |
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85 | * R/W,X for all, no ASID comparison, not cache-inhibited. |
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86 | * EPN TWC RPN |
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87 | */ |
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88 | { 0x00000200, 0x0D, 0x000009FD }, /* DRAM - PS=8M */ |
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89 | { 0x00800200, 0x0D, 0x008009FD }, /* DRAM - PS=8M */ |
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90 | #else |
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91 | #error "MBX board not defined" |
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92 | #endif |
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93 | /* |
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94 | * |
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95 | * NVRAM: CS4, Start address 0xFA000000, 32K, |
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96 | * ASID=0x0, APG=0x0, not guarded memory, copyback data cache policy, |
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97 | * R/W,X for all, no ASID comparison, cache-inhibited. |
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98 | * |
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99 | * EPN TWC RPN |
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100 | */ |
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101 | { 0xFA000200, 0x01, 0xFA0009FF }, /* NVRAM - PS=16K */ |
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102 | { 0xFA004200, 0x01, 0xFA0049FF }, /* NVRAM - PS=16K */ |
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103 | /* |
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104 | * |
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105 | * Board Control/Status Register #1/#2: CS4, Start address 0xFA100000, (4 x 8 bits?) |
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106 | * ASID=0x0, APG=0x0, guarded memory, copyback data cache policy, |
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107 | * R/W,X for all, no ASID comparison, cache-inhibited. |
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108 | * EPN TWC RPN |
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109 | */ |
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110 | { 0xFA100200, 0x11, 0xFA1009F7 }, /* BCSR - PS=4K */ |
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111 | /* |
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112 | * |
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113 | * (IMMR-SPRs) Dual Port RAM: Start address 0xFA200000, 16K, |
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114 | * ASID=0x0, APG=0x0, guarded memory, copyback data cache policy, |
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115 | * R/W,X for all, no ASID comparison, cache-inhibited. |
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116 | * |
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117 | * Note: We use the value in MBXA/PG2, which is also the value that |
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118 | * EPPC-Bug programmed into our boards. The alternative is the value |
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119 | * in MBXA/PG1: 0xFFA00000. This value might well depend on the revision |
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120 | * of the firmware. |
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121 | * EPN TWC RPN |
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122 | */ |
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123 | { 0xFA200200, 0x11, 0xFA2009FF }, /* IMMR - PS=16K */ |
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124 | /* |
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125 | * |
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126 | * Flash: CS0, Start address 0xFE000000, 4M, (BootROM-EPPCBug) |
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127 | * ASID=0x0, APG=0x0, not guarded memory, |
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128 | * R/O,X for all, no ASID comparison, not cache-inhibited. |
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129 | * EPN TWC RPN |
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130 | */ |
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131 | { 0xFE000200, 0x05, 0xFE000CFD }, /* Flash - PS=512K */ |
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132 | { 0xFE080200, 0x05, 0xFE080CFD }, /* Flash - PS=512K */ |
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133 | { 0xFE100200, 0x05, 0xFE100CFD }, /* Flash - PS=512K */ |
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134 | { 0xFE180200, 0x05, 0xFE180CFD }, /* Flash - PS=512K */ |
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135 | { 0xFE200200, 0x05, 0xFE200CFD }, /* Flash - PS=512K */ |
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136 | { 0xFE280200, 0x05, 0xFE280CFD }, /* Flash - PS=512K */ |
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137 | { 0xFE300200, 0x05, 0xFE300CFD }, /* Flash - PS=512K */ |
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138 | { 0xFE380200, 0x05, 0xFE380CFD }, /* Flash - PS=512K */ |
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139 | /* |
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140 | * BootROM: CS7, Start address 0xFC000000, 4M?, (socketed FLASH) |
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141 | * ASID=0x0, APG=0x0, not guarded memory, |
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142 | * R/O,X for all, no ASID comparison, not cache-inhibited. |
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143 | * EPN TWC RPN |
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144 | */ |
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145 | { 0xFC000200, 0x05, 0xFC000CFD }, /* BootROM - PS=512K */ |
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146 | /* |
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147 | * |
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148 | * PCI/ISA I/O Space: CS5, Start address 0x80000000, 512M? |
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149 | * ASID=0x0, APG=0x0, guarded memory, |
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150 | * R/W,X for all, no ASID comparison, cache-inhibited. |
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151 | * EPN TWC RPN |
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152 | */ |
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153 | { 0x80000200, 0x1D, 0x800009FF }, /* PCI I/O - PS=8M */ |
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154 | /* |
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155 | * |
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156 | * PCI/ISA Memory Space: CS5, Start address 0xC0000000, 512M? |
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157 | * ASID=0x0, APG=0x0, guarded memory, |
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158 | * R/W,X for all, no ASID comparison, cache-inhibited. |
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159 | * EPN TWC RPN |
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160 | */ |
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161 | { 0xC0000200, 0x1D, 0xC00009FF }, /* PCI Memory - PS=8M */ |
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162 | /* |
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163 | * |
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164 | * PCI Bridge/QSPAN Registers: CS6, Start address 0xFA210000, 4K |
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165 | * ASID=0x0, APG=0x0, guarded memory, |
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166 | * R/W,X for all, no ASID comparison, cache-inhibited. |
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167 | * EPN TWC RPN |
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168 | */ |
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169 | { 0xFA210200, 0x11, 0xFA2109F7 } /* QSPAN - PS=4K */ |
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170 | }; |
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171 | |
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172 | /* |
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173 | * MMU_N_TLB_Table_Entries is defined here because the size of the |
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174 | * MMU_TLB_table is only known in this file. |
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175 | */ |
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176 | int MMU_N_TLB_Table_Entries = ( sizeof(MMU_TLB_table) / sizeof(MMU_TLB_table[0]) ); |
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