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source: rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c @ c499856

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Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on 03/20/14 at 21:10:47
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1	/*
2	* imbx8xx.c
3	*
4	* MBX860/MBX821 initialization routines.
5	*
6	* Copyright (c) 1999, National Research Council of Canada
7	*
8	* The license and distribution terms for this file may be
9	* found in the file LICENSE in this distribution or at
10	* http://www.rtems.org/license/LICENSE.
11	*/
12
13	#include <bsp.h>
14	#include <bsp/mbx.h>
15
16	/*
17	* EPPCBug rev 1.1 is stupid. It clears the interrupt mask register
18	* in the SIU when it takes control, but does not restore it before
19	* returning control to the program. We thus keep a copy of the
20	* register, and restore it from gdb using the hook facilities.
21	*
22	* We arrange for simask_copy to be initialized to zero so that
23	* it resides in the .data section. This avoids having gdb set
24	* the mask to crud before we get to initialize explicitly. Of
25	* course, the code will not be safely restartable, but then again,
26	* a lot of the library code isn't either, so there!
27	*/
28	uint32_t simask_copy = 0;
29
30	/*
31	* The memory controller's UPMA Ram array values.
32	* The values in table 2-6 and 2-7 in the "MBX Series Embedded
33	* Controller Programmer's Reference Guide", part number MBXA/PG2,
34	* differ from the ones in the older MBX Programmer's Guide, part
35	* number MBXA/PG1. We are assuming that the values in MBXA/PG1
36	* are for the older MBX boards whose part number does not have
37	* the "B" suffix, but we have discovered that the values from
38	* MBXA/PG2 work better, even for the older boards.
39	*
40	* THESE VALUES HAVE ONLY BEEN VERIFIED FOR THE MBX821-001 and
41	* MBX860-002. USE WITH CARE!
42	*
43	* NOTE: The MBXA/PG2 manual lists the clock speed of the MBX821_001B
44	* as being 50 MHz, while the MBXA/IH2.1 manual lists it as 40 MHz.
45	* We think the MBX821_001B is an entry level board and thus is 50 MHz,
46	*/
47	static uint32_t upmaTable[64] = {
48
49	#if ( defined(mbx860_001b) \|\| \
50	defined(mbx821_001b) \|\| \
51	defined(mbx821_001) )
52
53	/* 50 MHz MBX */
54	/*
55	* Note: For the mbx821_001, the following values (from the
56	* MBXA/PG2 manual) work better than, but are different
57	* from those published in the original MBXA/PG1 manual and
58	* initialized by EPPCBug 1.1. In particular, the original
59	* burst-write values do not work! Also, the following values
60	* facilitate higher performance.
61	*/
62	/* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */
63	0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04,
64	0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005,
65
66	/* DRAM 60ns - burst read. (offset 0x08 in UPM RAM) */
67	0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x00AF0C04,
68	0x07AF0C08, 0x0CAF0C04, 0x01AF0C04, 0x0FAF0C08,
69	0x0CAF0C04, 0x01AF0C04, 0x0FAF0C08, 0x0CAF0C04,
70	0x10AF0C04, 0xF0AFC000, 0xF3BF4805, 0xFFFFC005,
71
72	/* DRAM 60ns - single write. (offset 0x18 in UPM RAM) */
73	0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804,
74	0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
75
76	/* DRAM 60ns - burst write. (offset 0x20 in UPM RAM) */
77	0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
78	0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
79	0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005,
80	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
81
82	/* Refresh 60ns. (offset 0x30 in UPM RAM) */
83	0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
84	0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005,
85	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
86
87	/* Exception. (offset 0x3c in UPM RAM) */
88	0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007
89
90	#elif ( defined(mbx860_002b) \|\| \
91	defined(mbx860_003b) \|\| \
92	defined(mbx860_004b) \|\| \
93	defined(mbx860_005b) \|\| \
94	defined(mbx860_006b) \|\| \
95	defined(mbx821_002b) \|\| \
96	defined(mbx821_003b) \|\| \
97	defined(mbx821_004b) \|\| \
98	defined(mbx821_005b) \|\| \
99	defined(mbx821_006b) \|\| \
100	defined(mbx860_001) \|\| \
101	defined(mbx860_002) \|\| \
102	defined(mbx860_003) \|\| \
103	defined(mbx860_004) \|\| \
104	defined(mbx860_005) \|\| \
105	defined(mbx821_002) \|\| \
106	defined(mbx821_003) \|\| \
107	defined(mbx821_004) \|\| \
108	defined(mbx821_005) )
109
110	/* 40 MHz MBX */
111	/*
112	* Note: For the older MBX models (i.e. without the "b"
113	* suffix, e.g. mbx860_001), the following values (from the
114	* MBXA/PG2 manual) work better than, but are different
115	* from those published in the original MBXA/PG1 manual and
116	* initialized by EPPCBug 1.1. In particular, the following
117	* burst-read and burst-write values facilitate higher
118	* performance.
119	*/
120	/* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */
121	0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00,
122	0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
123
124	/* DRAM 60ns - burst read. (offset 0x08 in UPM RAM) */
125	0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08,
126	0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08,
127	0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005,
128	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
129
130	/* DRAM 60ns - single write. (offset 0x18 in UPM RAM) */
131	0xCFFF0004, 0x0FFF4004, 0x0CFF0C00, 0x33FF4804,
132	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
133
134	/* DRAM 60ns - burst write. (offset 0x20 in UPM RAM) */
135	0xCFFF0004, 0x0FFF4004, 0x0CFF0C00, 0x03FF0C0C,
136	0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
137	0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005,
138	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
139
140	/* Refresh 60ns. (offset 0x30 in UPM RAM) */
141	0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
142	0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
143	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
144
145	/* Exception. (offset 0x3c in UPM RAM) */
146	0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007
147	#else
148	#error "MBX board model not specified."
149	#endif
150	};
151
152	#if ( !defined(EPPCBUG_VECTORS) )
153	extern uint32_t simask_copy;
154	#endif
155
156	/*
157	* Initialize MBX8xx
158	*/
159	void _InitMBX8xx (void)
160	{
161	#if ( !defined(EPPCBUG_VECTORS) )
162	uint32_t i;
163	#endif
164	register uint32_t r1;
165
166	/*
167	* Initialize the Debug Enable Register (DER) to an appropriate
168	* value for EPPCBug debugging.
169	* (This value should also work for BDM debugging.)
170	*/
171	r1 = 0x70C67C07; /* All except EXTIE, ALIE, DECIE */
172	_mtspr( M8xx_DER, r1 );
173
174	/*
175	* Initialize the Instruction Support Control Register (ICTRL) to a
176	* an appropriate value for normal operation. A different value,
177	* such as 0x0, may be more appropriate for debugging.
178	*/
179	r1 = 0x00000007;
180	_mtspr( M8xx_ICTRL, r1 );
181
182	/*
183	* Disable and invalidate the instruction and data caches.
184	*/
185	r1 = M8xx_CACHE_CMD_DISABLE;
186	_mtspr( M8xx_IC_CST, r1 );
187	_isync;
188	r1 = M8xx_CACHE_CMD_UNLOCKALL;
189	_mtspr( M8xx_IC_CST, r1 );
190	_isync;
191	r1 = M8xx_CACHE_CMD_INVALIDATE; /* invalidate all */
192	_mtspr( M8xx_IC_CST, r1 );
193	_isync;
194
195	r1 = M8xx_CACHE_CMD_DISABLE;
196	_mtspr( M8xx_DC_CST, r1 );
197	_isync;
198	r1 = M8xx_CACHE_CMD_UNLOCKALL;
199	_mtspr( M8xx_DC_CST, r1 );
200	_isync;
201	r1 = M8xx_CACHE_CMD_INVALIDATE; /* invalidate all */
202	_mtspr( M8xx_DC_CST, r1 );
203	_isync;
204
205	/*
206	* Initialize the Internal Memory Map Register (IMMR)
207	*
208	* Use the value in MBXA/PG2, which is also the value that EPPC-Bug
209	* programmed into our boards. The alternative is the value in
210	* MBXA/PG1: 0xFFA00000. This value might well depend on the revision
211	* of the firmware.
212	*
213	* THIS VALUE IS ALSO DECLARED IN THE linkcmds FILE and mmutlbtab.c!
214	*/
215	r1 = 0xFA200000;
216	_mtspr( M8xx_IMMR, r1 );
217
218	/*
219	* Get the SIU interrupt mask.
220	* imd: accessing m8xx.* should not occure before setting up the immr !
221	*/
222	simask_copy = m8xx.simask;
223
224	/*
225	* Initialize the SIU Module Configuration Register (SIUMCR)
226	* m8xx.siumcr = 0x00602900, the default MBX and firmware value.
227	*/
228	m8xx.siumcr = M8xx_SIUMCR_EARP0 \| M8xx_SIUMCR_DBGC3 \| M8xx_SIUMCR_DBPC0 \|
229	M8xx_SIUMCR_DPC \| M8xx_SIUMCR_MLRC2 \| M8xx_SIUMCR_SEME;
230
231	/*
232	* Initialize the System Protection Control Register (SYPCR).
233	* The SYPCR can only be written once after Reset.
234	* - Enable bus monitor
235	* - Disable software watchdog timer
236	* m8xx.sypcr = 0xFFFFFF88, the default MBX and firmware value.
237	*/
238	m8xx.sypcr = M8xx_SYPCR_SWTC(0xFFFF) \| M8xx_SYPCR_BMT(0xFF) \|
239	M8xx_SYPCR_BME \| M8xx_SYPCR_SWF;
240
241	/* Initialize the SIU Interrupt Edge Level Mask Register (SIEL) */
242	m8xx.siel = 0xAAAA0000; /* Default MBX and firmware value. */
243
244	/* Initialize the Transfer Error Status Register (TESR) */
245	m8xx.tesr = 0xFFFFFFFF; /* Default firmware value. */
246
247	/* Initialize the SDMA Configuration Register (SDCR) */
248	m8xx.sdcr = 0x00000001; /* Default firmware value. */
249
250	/*
251	* Initialize the Timebase Status and Control Register (TBSCR)
252	* m8xx.tbscr = 0x00C3, default MBX and firmware value.
253	*/
254	m8xx.tbscrk = M8xx_UNLOCK_KEY; /* unlock TBSCR */
255	m8xx.tbscr = M8xx_TBSCR_REFA \| M8xx_TBSCR_REFB \|
256	M8xx_TBSCR_TBF \| M8xx_TBSCR_TBE;
257
258	/* Initialize the Real-Time Clock Status and Control Register (RTCSC) */
259	m8xx.rtcsk = M8xx_UNLOCK_KEY; /* unlock RTCSC */
260	m8xx.rtcsc = 0x00C3; /* Default MBX and firmware value. */
261
262	/* Unlock other Real-Time Clock registers */
263	m8xx.rtck = M8xx_UNLOCK_KEY; /* unlock RTC */
264	m8xx.rtseck = M8xx_UNLOCK_KEY; /* unlock RTSEC */
265	m8xx.rtcalk = M8xx_UNLOCK_KEY; /* unlock RTCAL */
266
267	/* Initialize the Periodic Interrupt Status and Control Register (PISCR) */
268	m8xx.piscrk = M8xx_UNLOCK_KEY; /* unlock PISCR */
269	m8xx.piscr = 0x0083; /* Default MBX and firmware value. */
270
271	/* Initialize the System Clock and Reset Control Register (SCCR)
272	* Set the clock sources and division factors:
273	* Timebase Source is GCLK2 / 16
274	* Real-Time Clock Select is EXTCLK (4.192MHz)
275	* Real-Time Clock Divide is /4
276	*/
277	m8xx.sccrk = M8xx_UNLOCK_KEY; /* unlock SCCR */
278	m8xx.sccr = 0x02800000; /* for MBX860/MBX821 */
279
280	#if 0 /* IMD hack: do not init PLL after EPPCbug load */
281	/* Initialize the PLL, Low-Power, and Reset Control Register (PLPRCR) */
282	/* - set the clock speed and set normal power mode */
283	m8xx.plprck = M8xx_UNLOCK_KEY; /* unlock PLPRCR */
284	#if ( defined(mbx821_001) \|\| defined(mbx821_001b) \|\| defined(mbx860_001b) )
285	m8xx.plprcr = 0x5F500000;
286	#elif ( defined(mbx860_005b) \|\| \
287	defined(mbx860_002b) \|\| \
288	defined(mbx860_003b) \|\| \
289	defined(mbx860_004b) \|\| \
290	defined(mbx860_006b) \|\| \
291	defined(mbx821_002b) \|\| \
292	defined(mbx821_003b) \|\| \
293	defined(mbx821_004b) \|\| \
294	defined(mbx821_005b) \|\| \
295	defined(mbx821_006b) )
296	/* Set the multiplication factor to 0 and clear the timer interrupt status*/
297	m8xx.plprcr = 0x00005000;
298	#elif ( defined(mbx860_001) \|\| \
299	defined(mbx860_002) \|\| \
300	defined(mbx860_003) \|\| \
301	defined(mbx860_004) \|\| \
302	defined(mbx860_005) \|\| \
303	defined(mbx821_002) \|\| \
304	defined(mbx821_003) \|\| \
305	defined(mbx821_004) \|\| \
306	defined(mbx821_005))
307	m8xx.plprcr = 0x4C400000;
308	#else
309	#error "MBX board not defined"
310	#endif
311	#endif
312	/* Unlock the timebase and decrementer registers. */
313	m8xx.tbk = M8xx_UNLOCK_KEY;
314	/*
315	* Initialize decrementer register to a large value to
316	* guarantee that a decrementer interrupt will not be
317	* generated before the kernel is fully initialized.
318	*/
319	r1 = 0x7FFFFFFF;
320	_mtspr( M8xx_DEC, r1 );
321
322	/* Initialize the timebase register (TB is 64 bits) */
323	r1 = 0x00000000;
324	_mtspr( M8xx_TBU_WR, r1 );
325	_mtspr( M8xx_TBL_WR, r1 );
326
327	#if 0 /* IMD hack: do not init UPMs after EPPCbug load */
328	/*
329	* Memory Controller Initialization
330	*/
331
332	/*
333	* User Programmable Machine A (UPMA) Initialization
334	*
335	* If this initialization code is running from DRAM, it is very
336	* dangerous to change the value of any UPMA Ram array word from
337	* what the firmware (EPPCBug) initialized it to. Thus we don't
338	* initialize UPMA if EPPCBUG_VECTORS is defined; we assume EPPCBug
339	* has done the appropriate initialization.
340	*
341	* An exception to our rule, is that, for the older MBX boards
342	* (those without the "B" suffix, e.g. MBX821-001 and MBX860-002),
343	* we do re-initialize the burst-read and burst-write values with
344	* values that are more efficient. Also, in the MBX821 case,
345	* the burst-write original values set by EPPCBug do not work!
346	* This change can be done safely because the caches have not yet
347	* been activated.
348	*
349	* The RAM array of UPMA is initialized by writing to each of
350	* its 64 32-bit RAM locations.
351	* Note: UPM register initialization should occur before
352	* initialization of the corresponding BRx and ORx registers.
353	*/
354	#if ( !defined(EPPCBUG_VECTORS) )
355	for( i = 0; i < 64; ++i ) {
356	m8xx.mdr = upmaTable[i];
357	m8xx.mcr = M8xx_MEMC_MCR_WRITE \| M8xx_MEMC_MCR_UPMA \| M8xx_MEMC_MCR_MAD(i);
358	}
359	#elif ( defined(mbx860_001) \|\| \
360	defined(mbx860_002) \|\| \
361	defined(mbx860_003) \|\| \
362	defined(mbx860_004) \|\| \
363	defined(mbx860_005) \|\| \
364	defined(mbx821_001) \|\| \
365	defined(mbx821_002) \|\| \
366	defined(mbx821_003) \|\| \
367	defined(mbx821_004) \|\| \
368	defined(mbx821_005) )
369	/* Replace the burst-read and burst-write values with better ones. */
370	/* burst-read values */
371	for( i = 8; i < 24; ++i ) {
372	m8xx.mdr = upmaTable[i];
373	m8xx.mcr = M8xx_MEMC_MCR_WRITE \| M8xx_MEMC_MCR_UPMA \| M8xx_MEMC_MCR_MAD(i);
374	}
375	/* burst-write values */
376	for( i = 32; i < 48; ++i ) {
377	m8xx.mdr = upmaTable[i];
378	m8xx.mcr = M8xx_MEMC_MCR_WRITE \| M8xx_MEMC_MCR_UPMA \| M8xx_MEMC_MCR_MAD(i);
379	}
380	#endif
381
382	#if ( !defined(EPPCBUG_VECTORS) )
383	/*
384	* Initialize the memory periodic timer.
385	* Memory Periodic Timer Prescaler Register (MPTPR: 16-bit register)
386	* m8xx.mptpr = 0x0200;
387	*/
388	m8xx.mptpr = M8xx_MPTPR_PTP(0x2);
389
390	/*
391	* Initialize the Machine A Mode Register (MAMR)
392	*
393	* ASSUMES THAT DIMMs ARE NOT INSTALLED!
394	*
395	* Without DIMMs:
396	* m8xx.mamr = 0x13821000 (40 MHz) or 0x18821000 (50 MHz).
397	*
398	* With DIMMs:
399	* m8xx.mamr = 0x06821000 (40 MHz) or 0x08821000 (50 MHz).
400	*/
401	#if ( defined(mbx821_001) \|\| defined(mbx821_001b) \|\| defined(mbx860_001b) )
402	m8xx.mamr = M8xx_MEMC_MMR_PTP(0x18) \| M8xx_MEMC_MMR_PTE \|
403	M8xx_MEMC_MMR_DSP(0x1) \| M8xx_MEMC_MMR_G0CL(0) \| M8xx_MEMC_MMR_UPWAIT;
404	#else
405	m8xx.mamr = M8xx_MEMC_MMR_PTP(0x13) \| M8xx_MEMC_MMR_PTE \|
406	M8xx_MEMC_MMR_DSP(0x1) \| M8xx_MEMC_MMR_G0CL(0) \| M8xx_MEMC_MMR_UPWAIT;
407	#endif
408	#endif /* ! defined(EPPCBUG_VECTORS) */
409
410	/*
411	* Initialize the Base and Option Registers (BR0-BR7 and OR0-OR7)
412	* Note: For all chip selects, ORx should be programmed before BRx,
413	* except when programming the boot chip select (CS0) after hardware
414	* reset, in which case, BR0 should be programmed before OR0.
415	*
416	* MPC860/MPX821 Memory Map Summary:
417	* S-ADDR E-ADDR CS PS PE WP MS BI V DESCRIPTION
418	* FE000000 FE7FFFFF 0 32 N N GPCM Y Y Soldered FLASH Memory
419	* 00000000 00zFFFFF 1 32 N N UPMA N Y Local DRAM Memory
420	* 00X00000 0XXXXXXX 2 0 N N UPMA N N DIMM Memory - Bank #0
421	* 00X00000 0XXXXXXX 3 0 N N UPMA N N DIMM Memory - Bank #1
422	* FA000000 FA1FFFFF 4 8 N N GPCM Y Y NVRAM & BCSR
423	* 80000000 DFFFFFFF 5 32 N N GPCM Y Y PCI/ISA I/O & Memory
424	* FA210000 FA21FFFF 6 32 N N GPCM Y Y QSpan Registers
425	* FC000000 FC7FFFFF 7 8 N N GPCM Y Y Socketed FLASH Memory
426	*
427	* z = 3 for 4MB installed on the motherboard, z = F for 16M
428	*
429	* NOTE: The devices selected by CS0 and CS7 can be selected with jumper J4.
430	* This table assumes that the 32-bit soldered flash device is the boot ROM.
431	*/
432
433	/*
434	* CS0 : Soldered (32-bit) Flash Memory at 0xFE000000
435	*
436	* CHANGE THIS CODE IF YOU CHANGE JUMPER J4 FROM ITS FACTORY DEFAULT SETTING!
437	* (or better yet, don't reprogram BR0 and OR0; just program BR7 and OR7 to
438	* access whatever flash device is not selected during hard reset.)
439	*
440	* MBXA/PG2 appears to lie in note 14 for table 2-4. The manual states that
441	* "EPPCBUG configures the reset flash device at the lower address, and the
442	* nonreset flash device at the higher address." If we take reset flash device
443	* to mean the boot flash memory, then the statement must mean that BR0 must
444	* point to the device at the lower address, i.e. 0xFC000000, while BR7 must
445	* point to the device at the highest address, i.e. 0xFE000000.
446	*
447	* THIS IS NOT THE CASE!
448	*
449	* The boot flash is always configured to start at 0xFE000000, and the other
450	* one to start at 0xFC000000. Changing jumper J4 only changes the width of
451	* the memory ports into these two region.
452	*
453	* BR0 = 0xFE000001
454	* Base addr [0-16] 0b11111110000000000 = 0xFE000000
455	* Address type [17-19] 0b000
456	* Port size [20-21] 0b00 = 32 bits
457	* Parity enable [22] 0b0 = disabled
458	* Write protect [23] 0b0 = r/w
459	* Machine select [24-25] 0b00 = GPCM
460	* Reserved [26-30] 0b00000
461	* Valid Bit [31] 0b1 = this bank is valid
462	* OR0 = 0xFF800930 @ 40 MHz, 0xFF800940 @ 50 MHz
463	* Address mask [0-16] 0b11111111100000000 = 0xFF800000
464	* Addr type mask [17-19] 0b000 = no address-type protection
465	* CS negation time [20] 0b1
466	* ACS [21-22] 0b00 = CS output at same time as address lines
467	* Burst inhibit [23] 0b1 = bank does not support burst accesses
468	* Cycle length [24-27] 0b0011/0b0100 = 3/4 clock cycle wait states
469	* SETA [28] 0b0 = TA generated internally
470	* Timing relaxed [29] 0b0 = not relaxed
471	* Extended hold time [30] 0b0 = not extended
472	* Reserved [31] 0b0
473	*
474	* m8xx.memc[0]._or = 0xFF800930 (40 MHz)
475	* m8xx.memc[0]._or = 0xFF800940 (50 MHz)
476	* m8xx.memc[0]._br = 0xFE000001
477	*/
478	#if ( defined(mbx821_001) \|\| defined(mbx821_001b) \|\| defined(mbx860_001b) )
479	m8xx.memc[0]._or = M8xx_MEMC_OR_8M \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_CSNT \|
480	M8xx_MEMC_OR_ACS_NORM \| M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(4);
481	#else
482	m8xx.memc[0]._or = M8xx_MEMC_OR_8M \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_CSNT \|
483	M8xx_MEMC_OR_ACS_NORM \| M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(3);
484	#endif
485	m8xx.memc[0]._br = M8xx_BR_BA(0xFE000000) \| M8xx_BR_AT(0) \| M8xx_BR_PS32 \|
486	M8xx_BR_MS_GPCM \| M8xx_MEMC_BR_V;
487
488	/*
489	* CS1 : Local DRAM Memory at 0x00000000
490	* m8xx.memc[1]._or = 0xFFC00400;
491	* m8xx.memc[1]._br = 0x00000081;
492	*/
493	#if ( defined(mbx860_001b) )
494	m8xx.memc[1]._or = M8xx_MEMC_OR_2M \| M8xx_MEMC_OR_ATM(0) \|
495	M8xx_MEMC_OR_ACS_QRTR \| M8xx_MEMC_OR_SCY(0);
496	#elif ( defined(mbx860_002b) \|\| \
497	defined(mbx860_003b) \|\| \
498	defined(mbx821_001b) \|\| \
499	defined(mbx821_002b) \|\| \
500	defined(mbx821_003b) \|\| \
501	defined(mbx860_001) \|\| \
502	defined(mbx860_002) \|\| \
503	defined(mbx860_003) \|\| \
504	defined(mbx821_001) \|\| \
505	defined(mbx821_002) \|\| \
506	defined(mbx821_003) )
507	m8xx.memc[1]._or = M8xx_MEMC_OR_4M \| M8xx_MEMC_OR_ATM(0) \|
508	M8xx_MEMC_OR_ACS_QRTR \| M8xx_MEMC_OR_SCY(0);
509	#elif ( defined(mbx860_004) \|\| \
510	defined(mbx860_005) \|\| \
511	defined(mbx860_004b) \|\| \
512	defined(mbx860_005b) \|\| \
513	defined(mbx860_006b) \|\| \
514	defined(mbx821_004) \|\| \
515	defined(mbx821_005) \|\| \
516	defined(mbx821_004b) \|\| \
517	defined(mbx821_005b) \|\| \
518	defined(mbx821_006b) )
519	m8xx.memc[1]._or = M8xx_MEMC_OR_16M \| M8xx_MEMC_OR_ATM(0) \|
520	M8xx_MEMC_OR_ACS_QRTR \| M8xx_MEMC_OR_SCY(0);
521	#else
522	#error "MBX board not defined"
523	#endif
524	m8xx.memc[1]._br = M8xx_BR_BA(0x00000000) \| M8xx_BR_AT(0) \| M8xx_BR_PS32 \|
525	M8xx_BR_MS_UPMA \| M8xx_MEMC_BR_V;
526
527	/*
528	* CS2 : DIMM Memory - Bank #0, not present
529	* m8xx.memc[2]._or = 0x00000400;
530	* m8xx.memc[2]._br = 0x00000080;
531	*/
532	m8xx.memc[2]._or = M8xx_MEMC_OR_ATM(0) \|
533	M8xx_MEMC_OR_ACS_QRTR \| M8xx_MEMC_OR_SCY(0);
534	m8xx.memc[2]._br = M8xx_BR_AT(0) \| M8xx_BR_PS32 \|
535	M8xx_BR_MS_UPMA; /* ! M8xx_MEMC_BR_V */
536
537	/*
538	* CS3 : DIMM Memory - Bank #1, not present
539	* m8xx.memc[3]._or = 0x00000400;
540	* m8xx.memc[3]._br = 0x00000080;
541	*/
542	m8xx.memc[3]._or = M8xx_MEMC_OR_ATM(0) \|
543	M8xx_MEMC_OR_ACS_QRTR \| M8xx_MEMC_OR_SCY(0);
544	m8xx.memc[3]._br = M8xx_BR_AT(0) \| M8xx_BR_PS32 \|
545	M8xx_BR_MS_UPMA; /* ! M8xx_MEMC_BR_V */
546
547	/*
548	* CS4 : Battery-Backed SRAM at 0xFA000000
549	* m8xx.memc[4]._or = 0xFFE00920@ 40 MHz, 0xFFE00930 @ 50 MHz
550	* m8xx.memc[4]._br = 0xFA000401;
551	*/
552	#if ( defined(mbx821_001) \|\| defined(mbx821_001b) \|\| defined(mbx860_001b) )
553	m8xx.memc[4]._or = M8xx_MEMC_OR_2M \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_CSNT \|
554	M8xx_MEMC_OR_ACS_NORM \| M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(3);
555	#else
556	m8xx.memc[4]._or = M8xx_MEMC_OR_2M \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_CSNT \|
557	M8xx_MEMC_OR_ACS_NORM \| M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(2);
558	#endif
559	m8xx.memc[4]._br = M8xx_BR_BA(0xFA000000) \| M8xx_BR_AT(0) \| M8xx_BR_PS8 \|
560	M8xx_BR_MS_GPCM \| M8xx_MEMC_BR_V;
561
562	/*
563	* CS5 : PCI I/O and Memory at 0x80000000
564	* m8xx.memc[5]._or = 0xA0000108;
565	* m8xx.memc[5]._br = 0x80000001;
566	*/
567	m8xx.memc[5]._or = 0xA0000000 \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_ACS_NORM \|
568	M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(0) \| M8xx_MEMC_OR_SETA;
569	m8xx.memc[5]._br = M8xx_BR_BA(0x80000000) \| M8xx_BR_AT(0) \| M8xx_BR_PS32 \|
570	M8xx_BR_MS_GPCM \| M8xx_MEMC_BR_V;
571
572	/*
573	* CS6 : QSPAN Registers at 0xFA210000
574	* m8xx.memc[6]._or = 0xFFFF0108;
575	* m8xx.memc[6]._br = 0xFA210001;
576	*/
577	m8xx.memc[6]._or = M8xx_MEMC_OR_64K \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_ACS_NORM \|
578	M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(0) \| M8xx_MEMC_OR_SETA;
579	m8xx.memc[6]._br = M8xx_BR_BA(0xFA210000) \| M8xx_BR_AT(0) \| M8xx_BR_PS32 \|
580	M8xx_BR_MS_GPCM \| M8xx_MEMC_BR_V;
581
582	/*
583	* CS7 : Socketed (8-bit) Flash at 0xFC000000
584	* m8xx.memc[7]._or = 0xFF800930 @ 40 MHz, 0xFF800940 @ 50 MHz
585	* m8xx.memc[7]._br = 0xFC000401;
586	*/
587	#if ( defined(mbx821_001) \|\| defined(mbx821_001b) \|\| defined(mbx860_001b) )
588	m8xx.memc[7]._or = M8xx_MEMC_OR_8M \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_CSNT \|
589	M8xx_MEMC_OR_ACS_NORM \| M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(4);
590	#else
591	m8xx.memc[7]._or = M8xx_MEMC_OR_8M \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_CSNT \|
592	M8xx_MEMC_OR_ACS_NORM \| M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(3);
593	#endif
594	m8xx.memc[7]._br = M8xx_BR_BA(0xFC000000) \| M8xx_BR_AT(0) \| M8xx_BR_PS8 \|
595	M8xx_BR_MS_GPCM \| M8xx_MEMC_BR_V;
596	#endif /* IMD hack */
597	/*
598	* PCMCIA initialization
599	*/
600	/*
601	* PCMCIA region 0: common memory
602	*/
603	m8xx.pbr0 = PCMCIA_MEM_ADDR;
604	m8xx.por0 = (M8xx_PCMCIA_POR_BSIZE_64MB
605	\| M8xx_PCMCIA_POR_PSHT(15) \| M8xx_PCMCIA_POR_PSST(15)
606	\| M8xx_PCMCIA_POR_PSL(32)
607	\| M8xx_PCMCIA_POR_PPS_16 \| M8xx_PCMCIA_POR_PRS_MEM
608	\|M8xx_PCMCIA_POR_PSLOT_A \| M8xx_PCMCIA_POR_VALID);
609	/*
610	* PCMCIA region 1: dma memory
611	*/
612	m8xx.pbr1 = PCMCIA_DMA_ADDR;
613	m8xx.por1 = (M8xx_PCMCIA_POR_BSIZE_64MB
614	\| M8xx_PCMCIA_POR_PSHT(15) \| M8xx_PCMCIA_POR_PSST(15)
615	\| M8xx_PCMCIA_POR_PSL(32)
616	\| M8xx_PCMCIA_POR_PPS_16 \| M8xx_PCMCIA_POR_PRS_DMA
617	\|M8xx_PCMCIA_POR_PSLOT_A \| M8xx_PCMCIA_POR_VALID);
618	/*
619	* PCMCIA region 2: attribute memory
620	*/
621	m8xx.pbr2 = PCMCIA_ATTRB_ADDR;
622	m8xx.por2 = (M8xx_PCMCIA_POR_BSIZE_64MB
623	\| M8xx_PCMCIA_POR_PSHT(15) \| M8xx_PCMCIA_POR_PSST(15)
624	\| M8xx_PCMCIA_POR_PSL(32)
625	\| M8xx_PCMCIA_POR_PPS_16 \| M8xx_PCMCIA_POR_PRS_ATT
626	\|M8xx_PCMCIA_POR_PSLOT_A \| M8xx_PCMCIA_POR_VALID);
627	/*
628	* PCMCIA region 3: I/O access
629	*/
630	m8xx.pbr3 = PCMCIA_IO_ADDR;
631	m8xx.por3 = (M8xx_PCMCIA_POR_BSIZE_64MB
632	\| M8xx_PCMCIA_POR_PSHT(15) \| M8xx_PCMCIA_POR_PSST(15)
633	\| M8xx_PCMCIA_POR_PSL(32)
634	\| M8xx_PCMCIA_POR_PPS_16 \| M8xx_PCMCIA_POR_PRS_IO
635	\|M8xx_PCMCIA_POR_PSLOT_A \| M8xx_PCMCIA_POR_VALID);
636
637	/*
638	* PCMCIA interface general control reg
639	*/
640	m8xx.pgcra = 0; /* no special options set */
641	/*
642	* PCMCIA interface enable reg
643	*/
644	m8xx.per =0; /* no interrupts enabled now */
645	}

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