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imbx8xx.c @ 310a2ec

4.104.114.84.95

Last change on this file since 310a2ec was 8ef3818, checked in by Joel Sherrill <joel.sherrill@…>, on 06/12/00 at 19:57:02

Patch from John Cotton <john.cotton@…>, Charles-Antoine Gauthier
<charles.gauthier@…>, and Darlene A. Stewart
<Darlene.Stewart@…> to add support for a number of very
significant things:

+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040

and PowerPC

+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use

same code base.

+ Rework of eth_comm BSP to utiltize above.

John reports this works on the 821 and 860

Property mode set to 100644

File size: 19.7 KB

Line
1	/*
2	* imbx8xx.c
3	*
4	* MBX860/MBX821 initialization routines.
5	*
6	* Copyright (c) 1999, National Research Council of Canada
7	*
8	* The license and distribution terms for this file may be
9	* found in the file LICENSE in this distribution or at
10	* http://www.OARcorp.com/rtems/license.html.
11	*/
12
13	#include <bsp.h>
14
15	/*
16	* EPPCBug rev 1.1 is stupid. It clears the interrupt mask register
17	* in the SIU when it takes control, but does not restore it before
18	* returning control to the program. We thus keep a copy of the
19	* register, and restore it from gdb using the hook facilities.
20	*
21	* We arrange for simask_copy to be initialized to zero so that
22	* it resides in the .data section. This avoids having gdb set
23	* the mask to crud before we get to initialize explicitly. Of
24	* course, the code will not be safely restartable, but then again,
25	* a lot of the library code isn't either, so there!
26	*/
27	unsigned32 simask_copy = 0;
28
29	/*
30	* The memory controller's UPMA Ram array values.
31	* The values in table 2-6 and 2-7 in the "MBX Series Embedded
32	* Controller Programmer's Reference Guide", part number MBXA/PG2,
33	* differ from the ones in the older MBX Programmer's Guide, part
34	* number MBXA/PG1. We are assuming that the values in MBXA/PG1
35	* are for the older MBX boards whose part number does not have
36	* the "B" suffix, but we have discovered that the values from
37	* MBXA/PG2 work better, even for the older boards.
38	*
39	* THESE VALUES HAVE ONLY BEEN VERIFIED FOR THE MBX821-001 and
40	* MBX860-002. USE WITH CARE!
41	*
42	* NOTE: The MBXA/PG2 manual lists the clock speed of the MBX821_001B
43	* as being 50 MHz, while the MBXA/IH2.1 manual lists it as 40 MHz.
44	* We think the MBX821_001B is an entry level board and thus is 50 MHz,
45	*/
46	static unsigned32 upmaTable[64] = {
47
48	#if ( defined(mbx860_001b) \|\| \
49	defined(mbx821_001b) \|\| \
50	defined(mbx821_001) )
51
52	/* 50 MHz MBX */
53	/*
54	* Note: For the mbx821_001, the following values (from the
55	* MBXA/PG2 manual) work better than, but are different
56	* from those published in the original MBXA/PG1 manual and
57	* initialized by EPPCBug 1.1. In particular, the original
58	* burst-write values do not work! Also, the following values
59	* facilitate higher performance.
60	*/
61	/* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */
62	0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04,
63	0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005,
64
65	/* DRAM 60ns - burst read. (offset 0x08 in UPM RAM) */
66	0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x00AF0C04,
67	0x07AF0C08, 0x0CAF0C04, 0x01AF0C04, 0x0FAF0C08,
68	0x0CAF0C04, 0x01AF0C04, 0x0FAF0C08, 0x0CAF0C04,
69	0x10AF0C04, 0xF0AFC000, 0xF3BF4805, 0xFFFFC005,
70
71	/* DRAM 60ns - single write. (offset 0x18 in UPM RAM) */
72	0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804,
73	0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
74
75	/* DRAM 60ns - burst write. (offset 0x20 in UPM RAM) */
76	0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
77	0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
78	0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005,
79	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
80
81	/* Refresh 60ns. (offset 0x30 in UPM RAM) */
82	0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
83	0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005,
84	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
85
86	/* Exception. (offset 0x3c in UPM RAM) */
87	0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007
88
89	#elif ( defined(mbx860_002b) \|\| \
90	defined(mbx860_003b) \|\| \
91	defined(mbx860_004b) \|\| \
92	defined(mbx860_005b) \|\| \
93	defined(mbx860_006b) \|\| \
94	defined(mbx821_002b) \|\| \
95	defined(mbx821_003b) \|\| \
96	defined(mbx821_004b) \|\| \
97	defined(mbx821_005b) \|\| \
98	defined(mbx821_006b) \|\| \
99	defined(mbx860_001) \|\| \
100	defined(mbx860_002) \|\| \
101	defined(mbx860_003) \|\| \
102	defined(mbx860_004) \|\| \
103	defined(mbx860_005) \|\| \
104	defined(mbx821_002) \|\| \
105	defined(mbx821_003) \|\| \
106	defined(mbx821_004) \|\| \
107	defined(mbx821_005) )
108
109	/* 40 MHz MBX */
110	/*
111	* Note: For the older MBX models (i.e. without the "b"
112	* suffix, e.g. mbx860_001), the following values (from the
113	* MBXA/PG2 manual) work better than, but are different
114	* from those published in the original MBXA/PG1 manual and
115	* initialized by EPPCBug 1.1. In particular, the following
116	* burst-read and burst-write values facilitate higher
117	* performance.
118	*/
119	/* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */
120	0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00,
121	0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
122
123	/* DRAM 60ns - burst read. (offset 0x08 in UPM RAM) */
124	0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08,
125	0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08,
126	0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005,
127	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
128
129	/* DRAM 60ns - single write. (offset 0x18 in UPM RAM) */
130	0xCFFF0004, 0x0FFF4004, 0x0CFF0C00, 0x33FF4804,
131	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
132
133	/* DRAM 60ns - burst write. (offset 0x20 in UPM RAM) */
134	0xCFFF0004, 0x0FFF4004, 0x0CFF0C00, 0x03FF0C0C,
135	0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
136	0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005,
137	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
138
139	/* Refresh 60ns. (offset 0x30 in UPM RAM) */
140	0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
141	0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
142	0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
143
144	/* Exception. (offset 0x3c in UPM RAM) */
145	0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007
146	#else
147	#error "MBX board model not specified."
148	#endif
149	};
150
151	/*
152	* Initialize MBX8xx
153	*/
154	void _InitMBX8xx (void)
155	{
156	register unsigned32 r1, i;
157	extern unsigned32 simask_copy;
158
159	/*
160	* Get the SIU interrupt mask.
161	*/
162	simask_copy = m8xx.simask;
163
164	/*
165	* Initialize the Debug Enable Register (DER) to an appropriate
166	* value for EPPCBug debugging.
167	* (This value should also work for BDM debugging.)
168	*/
169	r1 = 0x70C67C07; /* All except EXTIE, ALIE, DECIE */
170	_mtspr( M8xx_DER, r1 );
171
172	/*
173	* Initialize the Instruction Support Control Register (ICTRL) to a
174	* an appropriate value for normal operation. A different value,
175	* such as 0x0, may be more appropriate for debugging.
176	*/
177	r1 = 0x00000007;
178	_mtspr( M8xx_ICTRL, r1 );
179
180	/*
181	* Disable and invalidate the instruction and data caches.
182	*/
183	r1 = M8xx_CACHE_CMD_DISABLE;
184	_mtspr( M8xx_IC_CST, r1 );
185	_isync;
186	r1 = M8xx_CACHE_CMD_UNLOCKALL;
187	_mtspr( M8xx_IC_CST, r1 );
188	_isync;
189	r1 = M8xx_CACHE_CMD_INVALIDATE; /* invalidate all */
190	_mtspr( M8xx_IC_CST, r1 );
191	_isync;
192
193	r1 = M8xx_CACHE_CMD_DISABLE;
194	_mtspr( M8xx_DC_CST, r1 );
195	_isync;
196	r1 = M8xx_CACHE_CMD_UNLOCKALL;
197	_mtspr( M8xx_DC_CST, r1 );
198	_isync;
199	r1 = M8xx_CACHE_CMD_INVALIDATE; /* invalidate all */
200	_mtspr( M8xx_DC_CST, r1 );
201	_isync;
202
203	/*
204	* Initialize the Internal Memory Map Register (IMMR)
205	*
206	* Use the value in MBXA/PG2, which is also the value that EPPC-Bug
207	* programmed into our boards. The alternative is the value in
208	* MBXA/PG1: 0xFFA00000. This value might well depend on the revision
209	* of the firmware.
210	*
211	* THIS VALUE IS ALSO DECLARED IN THE linkcmds FILE and mmutlbtab.c!
212	*/
213	r1 = 0xFA200000;
214	_mtspr( M8xx_IMMR, r1 );
215
216	/*
217	* Initialize the SIU Module Configuration Register (SIUMCR)
218	* m8xx.siumcr = 0x00602900, the default MBX and firmware value.
219	*/
220	m8xx.siumcr = M8xx_SIUMCR_EARP0 \| M8xx_SIUMCR_DBGC3 \| M8xx_SIUMCR_DBPC0 \|
221	M8xx_SIUMCR_DPC \| M8xx_SIUMCR_MLRC2 \| M8xx_SIUMCR_SEME;
222
223	/*
224	* Initialize the System Protection Control Register (SYPCR).
225	* The SYPCR can only be written once after Reset.
226	* - Enable bus monitor
227	* - Disable software watchdog timer
228	* m8xx.sypcr = 0xFFFFFF88, the default MBX and firmware value.
229	*/
230	m8xx.sypcr = M8xx_SYPCR_SWTC(0xFFFF) \| M8xx_SYPCR_BMT(0xFF) \|
231	M8xx_SYPCR_BME \| M8xx_SYPCR_SWF;
232
233	/* Initialize the SIU Interrupt Edge Level Mask Register (SIEL) */
234	m8xx.siel = 0xAAAA0000; /* Default MBX and firmware value. */
235
236	/* Initialize the Transfer Error Status Register (TESR) */
237	m8xx.tesr = 0xFFFFFFFF; /* Default firmware value. */
238
239	/* Initialize the SDMA Configuration Register (SDCR) */
240	m8xx.sdcr = 0x00000001; /* Default firmware value. */
241
242	/*
243	* Initialize the Timebase Status and Control Register (TBSCR)
244	* m8xx.tbscr = 0x00C3, default MBX and firmware value.
245	*/
246	m8xx.tbscrk = M8xx_UNLOCK_KEY; /* unlock TBSCR */
247	m8xx.tbscr = M8xx_TBSCR_REFA \| M8xx_TBSCR_REFB \|
248	M8xx_TBSCR_TBF \| M8xx_TBSCR_TBE;
249
250	/* Initialize the Real-Time Clock Status and Control Register (RTCSC) */
251	m8xx.rtcsk = M8xx_UNLOCK_KEY; /* unlock RTCSC */
252	m8xx.rtcsc = 0x00C3; /* Default MBX and firmware value. */
253
254	/* Unlock other Real-Time Clock registers */
255	m8xx.rtck = M8xx_UNLOCK_KEY; /* unlock RTC */
256	m8xx.rtseck = M8xx_UNLOCK_KEY; /* unlock RTSEC */
257	m8xx.rtcalk = M8xx_UNLOCK_KEY; /* unlock RTCAL */
258
259	/* Initialize the Periodic Interrupt Status and Control Register (PISCR) */
260	m8xx.piscrk = M8xx_UNLOCK_KEY; /* unlock PISCR */
261	m8xx.piscr = 0x0083; /* Default MBX and firmware value. */
262
263	/* Initialize the System Clock and Reset Control Register (SCCR)
264	* Set the clock sources and division factors:
265	* Timebase Source is GCLK2 / 16
266	* Real-Time Clock Select is EXTCLK (4.192MHz)
267	* Real-Time Clock Divide is /4
268	*/
269	m8xx.sccrk = M8xx_UNLOCK_KEY; /* unlock SCCR */
270	m8xx.sccr = 0x02800000; /* for MBX860/MBX821 */
271
272	/* Initialize the PLL, Low-Power, and Reset Control Register (PLPRCR) */
273	/* - set the clock speed and set normal power mode */
274	m8xx.plprck = M8xx_UNLOCK_KEY; /* unlock PLPRCR */
275	#if ( defined(mbx821_001) \|\| defined(mbx821_001b) \|\| defined(mbx860_001b) )
276	m8xx.plprcr = 0x5F500000;
277	#else
278	m8xx.plprcr = 0x4C400000;
279	#endif
280	/* Unlock the timebase and decrementer registers. */
281	m8xx.tbk = M8xx_UNLOCK_KEY;
282
283	/*
284	* Initialize decrementer register to a large value to
285	* guarantee that a decrementer interrupt will not be
286	* generated before the kernel is fully initialized.
287	*/
288	r1 = 0x7FFFFFFF;
289	_mtspr( M8xx_DEC, r1 );
290
291	/* Initialize the timebase register (TB is 64 bits) */
292	r1 = 0x00000000;
293	_mtspr( M8xx_TBU_WR, r1 );
294	_mtspr( M8xx_TBL_WR, r1 );
295
296	/*
297	* Memory Controller Initialization
298	*/
299
300	/*
301	* User Programmable Machine A (UPMA) Initialization
302	*
303	* If this initialization code is running from DRAM, it is very
304	* dangerous to change the value of any UPMA Ram array word from
305	* what the firmware (EPPCBug) initialized it to. Thus we don't
306	* initialize UPMA if EPPCBUG_VECTORS is defined; we assume EPPCBug
307	* has done the appropriate initialization.
308	*
309	* An exception to our rule, is that, for the older MBX boards
310	* (those without the "B" suffix, e.g. MBX821-001 and MBX860-002),
311	* we do re-initialize the burst-read and burst-write values with
312	* values that are more efficient. Also, in the MBX821 case,
313	* the burst-write original values set by EPPCBug do not work!
314	* This change can be done safely because the caches have not yet
315	* been activated.
316	*
317	* The RAM array of UPMA is initialized by writing to each of
318	* its 64 32-bit RAM locations.
319	* Note: UPM register initialization should occur before
320	* initialization of the corresponding BRx and ORx registers.
321	*/
322	#if ( !defined(EPPCBUG_VECTORS) )
323	for( i = 0; i < 64; ++i ) {
324	m8xx.mdr = upmaTable[i];
325	m8xx.mcr = M8xx_MEMC_MCR_WRITE \| M8xx_MEMC_MCR_UPMA \| M8xx_MEMC_MCR_MAD(i);
326	}
327	#elif ( defined(mbx860_001) \|\| \
328	defined(mbx860_002) \|\| \
329	defined(mbx860_003) \|\| \
330	defined(mbx860_004) \|\| \
331	defined(mbx860_005) \|\| \
332	defined(mbx821_001) \|\| \
333	defined(mbx821_002) \|\| \
334	defined(mbx821_003) \|\| \
335	defined(mbx821_004) \|\| \
336	defined(mbx821_005) )
337	/* Replace the burst-read and burst-write values with better ones. */
338	/* burst-read values */
339	for( i = 8; i < 24; ++i ) {
340	m8xx.mdr = upmaTable[i];
341	m8xx.mcr = M8xx_MEMC_MCR_WRITE \| M8xx_MEMC_MCR_UPMA \| M8xx_MEMC_MCR_MAD(i);
342	}
343	/* burst-write values */
344	for( i = 32; i < 48; ++i ) {
345	m8xx.mdr = upmaTable[i];
346	m8xx.mcr = M8xx_MEMC_MCR_WRITE \| M8xx_MEMC_MCR_UPMA \| M8xx_MEMC_MCR_MAD(i);
347	}
348	#endif
349
350	#if ( !defined(EPPCBUG_VECTORS) )
351	/*
352	* Initialize the memory periodic timer.
353	* Memory Periodic Timer Prescaler Register (MPTPR: 16-bit register)
354	* m8xx.mptpr = 0x0200;
355	*/
356	m8xx.mptpr = M8xx_MPTPR_PTP(0x2);
357
358	/*
359	* Initialize the Machine A Mode Register (MAMR)
360	*
361	* ASSUMES THAT DIMMs ARE NOT INSTALLED!
362	*
363	* Without DIMMs:
364	* m8xx.mamr = 0x13821000 (40 MHz) or 0x18821000 (50 MHz).
365	*
366	* With DIMMs:
367	* m8xx.mamr = 0x06821000 (40 MHz) or 0x08821000 (50 MHz).
368	*/
369	#if ( defined(mbx821_001) \|\| defined(mbx821_001b) \|\| defined(mbx860_001b) )
370	m8xx.mamr = M8xx_MEMC_MMR_PTP(0x18) \| M8xx_MEMC_MMR_PTE \|
371	M8xx_MEMC_MMR_DSP(0x1) \| M8xx_MEMC_MMR_G0CL(0) \| M8xx_MEMC_MMR_UPWAIT;
372	#else
373	m8xx.mamr = M8xx_MEMC_MMR_PTP(0x13) \| M8xx_MEMC_MMR_PTE \|
374	M8xx_MEMC_MMR_DSP(0x1) \| M8xx_MEMC_MMR_G0CL(0) \| M8xx_MEMC_MMR_UPWAIT;
375	#endif
376	#endif /* ! defined(EPPCBUG_VECTORS) */
377
378	/*
379	* Initialize the Base and Option Registers (BR0-BR7 and OR0-OR7)
380	* Note: For all chip selects, ORx should be programmed before BRx,
381	* except when programming the boot chip select (CS0) after hardware
382	* reset, in which case, BR0 should be programmed before OR0.
383	*
384	* MPC860/MPX821 Memory Map Summary:
385	* S-ADDR E-ADDR CS PS PE WP MS BI V DESCRIPTION
386	* FE000000 FE7FFFFF 0 32 N N GPCM Y Y Soldered FLASH Memory
387	* 00000000 00zFFFFF 1 32 N N UPMA N Y Local DRAM Memory
388	* 00X00000 0XXXXXXX 2 0 N N UPMA N N DIMM Memory - Bank #0
389	* 00X00000 0XXXXXXX 3 0 N N UPMA N N DIMM Memory - Bank #1
390	* FA000000 FA1FFFFF 4 8 N N GPCM Y Y NVRAM & BCSR
391	* 80000000 DFFFFFFF 5 32 N N GPCM Y Y PCI/ISA I/O & Memory
392	* FA210000 FA21FFFF 6 32 N N GPCM Y Y QSpan Registers
393	* FC000000 FC7FFFFF 7 8 N N GPCM Y Y Socketed FLASH Memory
394	*
395	* z = 3 for 4MB installed on the motherboard, z = F for 16M
396	*
397	* NOTE: The devices selected by CS0 and CS7 can be selected with jumper J4.
398	* This table assumes that the 32-bit soldered flash device is the boot ROM.
399	*/
400
401	/*
402	* CS0 : Soldered (32-bit) Flash Memory at 0xFE000000
403	*
404	* CHANGE THIS CODE IF YOU CHANGE JUMPER J4 FROM ITS FACTORY DEFAULT SETTING!
405	* (or better yet, don't reprogram BR0 and OR0; just program BR7 and OR7 to
406	* access whatever flash device is not selected during hard reset.)
407	*
408	* MBXA/PG2 appears to lie in note 14 for table 2-4. The manual states that
409	* "EPPCBUG configures the reset flash device at the lower address, and the
410	* nonreset flash device at the higher address." If we take reset flash device
411	* to mean the boot flash memory, then the statement must mean that BR0 must
412	* point to the device at the lower address, i.e. 0xFC000000, while BR7 must
413	* point to the device at the highest address, i.e. 0xFE000000.
414	*
415	* THIS IS NOT THE CASE!
416	*
417	* The boot flash is always configured to start at 0xFE000000, and the other
418	* one to start at 0xFC000000. Changing jumper J4 only changes the width of
419	* the memory ports into these two region.
420	*
421	* BR0 = 0xFE000001
422	* Base addr [0-16] 0b11111110000000000 = 0xFE000000
423	* Address type [17-19] 0b000
424	* Port size [20-21] 0b00 = 32 bits
425	* Parity enable [22] 0b0 = disabled
426	* Write protect [23] 0b0 = r/w
427	* Machine select [24-25] 0b00 = GPCM
428	* Reserved [26-30] 0b00000
429	* Valid Bit [31] 0b1 = this bank is valid
430	* OR0 = 0xFF800930 @ 40 MHz, 0xFF800940 @ 50 MHz
431	* Address mask [0-16] 0b11111111100000000 = 0xFF800000
432	* Addr type mask [17-19] 0b000 = no address-type protection
433	* CS negation time [20] 0b1
434	* ACS [21-22] 0b00 = CS output at same time as address lines
435	* Burst inhibit [23] 0b1 = bank does not support burst accesses
436	* Cycle length [24-27] 0b0011/0b0100 = 3/4 clock cycle wait states
437	* SETA [28] 0b0 = TA generated internally
438	* Timing relaxed [29] 0b0 = not relaxed
439	* Extended hold time [30] 0b0 = not extended
440	* Reserved [31] 0b0
441	*
442	* m8xx.memc[0]._or = 0xFF800930 (40 MHz)
443	* m8xx.memc[0]._or = 0xFF800940 (50 MHz)
444	* m8xx.memc[0]._br = 0xFE000001
445	*/
446	#if ( defined(mbx821_001) \|\| defined(mbx821_001b) \|\| defined(mbx860_001b) )
447	m8xx.memc[0]._or = M8xx_MEMC_OR_8M \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_CSNT \|
448	M8xx_MEMC_OR_ACS_NORM \| M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(4);
449	#else
450	m8xx.memc[0]._or = M8xx_MEMC_OR_8M \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_CSNT \|
451	M8xx_MEMC_OR_ACS_NORM \| M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(3);
452	#endif
453	m8xx.memc[0]._br = M8xx_BR_BA(0xFE000000) \| M8xx_BR_AT(0) \| M8xx_BR_PS32 \|
454	M8xx_BR_MS_GPCM \| M8xx_MEMC_BR_V;
455
456	/*
457	* CS1 : Local DRAM Memory at 0x00000000
458	* m8xx.memc[1]._or = 0xFFC00400;
459	* m8xx.memc[1]._br = 0x00000081;
460	*/
461	m8xx.memc[1]._or = M8xx_MEMC_OR_4M \| M8xx_MEMC_OR_ATM(0) \|
462	M8xx_MEMC_OR_ACS_QRTR \| M8xx_MEMC_OR_SCY(0);
463	m8xx.memc[1]._br = M8xx_BR_BA(0x00000000) \| M8xx_BR_AT(0) \| M8xx_BR_PS32 \|
464	M8xx_BR_MS_UPMA \| M8xx_MEMC_BR_V;
465
466	/*
467	* CS2 : DIMM Memory - Bank #0, not present
468	* m8xx.memc[2]._or = 0x00000400;
469	* m8xx.memc[2]._br = 0x00000080;
470	*/
471	m8xx.memc[2]._or = M8xx_MEMC_OR_ATM(0) \|
472	M8xx_MEMC_OR_ACS_QRTR \| M8xx_MEMC_OR_SCY(0);
473	m8xx.memc[2]._br = M8xx_BR_AT(0) \| M8xx_BR_PS32 \|
474	M8xx_BR_MS_UPMA; /* ! M8xx_MEMC_BR_V */
475
476	/*
477	* CS3 : DIMM Memory - Bank #1, not present
478	* m8xx.memc[3]._or = 0x00000400;
479	* m8xx.memc[3]._br = 0x00000080;
480	*/
481	m8xx.memc[3]._or = M8xx_MEMC_OR_ATM(0) \|
482	M8xx_MEMC_OR_ACS_QRTR \| M8xx_MEMC_OR_SCY(0);
483	m8xx.memc[3]._br = M8xx_BR_AT(0) \| M8xx_BR_PS32 \|
484	M8xx_BR_MS_UPMA; /* ! M8xx_MEMC_BR_V */
485
486	/*
487	* CS4 : Battery-Backed SRAM at 0xFA000000
488	* m8xx.memc[4]._or = 0xFFE00920@ 40 MHz, 0xFFE00930 @ 50 MHz
489	* m8xx.memc[4]._br = 0xFA000401;
490	*/
491	#if ( defined(mbx821_001) \|\| defined(mbx821_001b) \|\| defined(mbx860_001b) )
492	m8xx.memc[4]._or = M8xx_MEMC_OR_2M \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_CSNT \|
493	M8xx_MEMC_OR_ACS_NORM \| M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(3);
494	#else
495	m8xx.memc[4]._or = M8xx_MEMC_OR_2M \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_CSNT \|
496	M8xx_MEMC_OR_ACS_NORM \| M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(2);
497	#endif
498	m8xx.memc[4]._br = M8xx_BR_BA(0xFA000000) \| M8xx_BR_AT(0) \| M8xx_BR_PS8 \|
499	M8xx_BR_MS_GPCM \| M8xx_MEMC_BR_V;
500
501	/*
502	* CS5 : PCI I/O and Memory at 0x80000000
503	* m8xx.memc[5]._or = 0xA0000108;
504	* m8xx.memc[5]._br = 0x80000001;
505	*/
506	m8xx.memc[5]._or = 0xA0000000 \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_ACS_NORM \|
507	M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(0) \| M8xx_MEMC_OR_SETA;
508	m8xx.memc[5]._br = M8xx_BR_BA(0x80000000) \| M8xx_BR_AT(0) \| M8xx_BR_PS32 \|
509	M8xx_BR_MS_GPCM \| M8xx_MEMC_BR_V;
510
511	/*
512	* CS6 : QSPAN Registers at 0xFA210000
513	* m8xx.memc[6]._or = 0xFFFF0108;
514	* m8xx.memc[6]._br = 0xFA210001;
515	*/
516	m8xx.memc[6]._or = M8xx_MEMC_OR_64K \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_ACS_NORM \|
517	M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(0) \| M8xx_MEMC_OR_SETA;
518	m8xx.memc[6]._br = M8xx_BR_BA(0xFA210000) \| M8xx_BR_AT(0) \| M8xx_BR_PS32 \|
519	M8xx_BR_MS_GPCM \| M8xx_MEMC_BR_V;
520
521	/*
522	* CS7 : Socketed (8-bit) Flash at 0xFC000000
523	* m8xx.memc[7]._or = 0xFF800930 @ 40 MHz, 0xFF800940 @ 50 MHz
524	* m8xx.memc[7]._br = 0xFC000401;
525	*/
526	#if ( defined(mbx821_001) \|\| defined(mbx821_001b) \|\| defined(mbx860_001b) )
527	m8xx.memc[7]._or = M8xx_MEMC_OR_8M \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_CSNT \|
528	M8xx_MEMC_OR_ACS_NORM \| M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(4);
529	#else
530	m8xx.memc[7]._or = M8xx_MEMC_OR_8M \| M8xx_MEMC_OR_ATM(0) \| M8xx_MEMC_OR_CSNT \|
531	M8xx_MEMC_OR_ACS_NORM \| M8xx_MEMC_OR_BI \| M8xx_MEMC_OR_SCY(3);
532	#endif
533	m8xx.memc[7]._br = M8xx_BR_BA(0xFC000000) \| M8xx_BR_AT(0) \| M8xx_BR_PS8 \|
534	M8xx_BR_MS_GPCM \| M8xx_MEMC_BR_V;
535	}

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source: rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c @ 310a2ec

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