source: rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/imbx8xx.c @ 1e7cbc5

4.104.114.84.9
Last change on this file since 1e7cbc5 was 1e7cbc5, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 4, 2003 at 6:52:26 PM

2003-09-04 Joel Sherrill <joel@…>

  • clock/p_clock.c, ide/pcmcia_ide.c, include/bsp.h, include/coverhd.h, irq/irq.c, irq/irq.h, irq/irq_asm.S, irq/irq_init.c, startup/bspstart.c, startup/bspstart.c.nocache, startup/imbx8xx.c, startup/mmutlbtab.c, startup/setvec.c, startup/start.S, vectors/vectors.h, vectors/vectors_init.c: URL for license changed.
  • Property mode set to 100644
File size: 23.1 KB
Line 
1/*
2 *  imbx8xx.c
3 *
4 *  MBX860/MBX821 initialization routines.
5 *
6 *  Copyright (c) 1999, National Research Council of Canada
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 */
12
13#include <bsp.h>
14#include <bsp/mbx.h>
15
16/*
17 *  EPPCBug rev 1.1 is stupid. It clears the interrupt mask register
18 *  in the SIU when it takes control, but does not restore it before
19 *  returning control to the program. We thus keep a copy of the
20 *  register, and restore it from gdb using the hook facilities.
21 * 
22 *  We arrange for simask_copy to be initialized to zero so that
23 *  it resides in the .data section. This avoids having gdb set
24 *  the mask to crud before we get to initialize explicitly. Of
25 *  course, the code will not be safely restartable, but then again,
26 *  a lot of the library code isn't either, so there!
27 */
28unsigned32 simask_copy = 0;
29
30/*
31 *  The memory controller's UPMA Ram array values.
32 *  The values in table 2-6 and 2-7 in the "MBX Series Embedded
33 *  Controller Programmer's Reference Guide", part number MBXA/PG2,
34 *  differ from the ones in the older MBX Programmer's Guide, part
35 *  number MBXA/PG1. We are assuming that the values in MBXA/PG1
36 *  are for the older MBX boards whose part number does not have
37 *  the "B" suffix, but we have discovered that the values from
38 *  MBXA/PG2 work better, even for the older boards.
39 * 
40 *  THESE VALUES HAVE ONLY BEEN VERIFIED FOR THE MBX821-001 and
41 *  MBX860-002. USE WITH CARE!
42 * 
43 *  NOTE: The MBXA/PG2 manual lists the clock speed of the MBX821_001B
44 *  as being 50 MHz, while the MBXA/IH2.1 manual lists it as 40 MHz.
45 *  We think the MBX821_001B is an entry level board and thus is 50 MHz,
46 */
47static unsigned32 upmaTable[64] = {
48
49#if ( defined(mbx860_001b) || \
50        defined(mbx821_001b) || \
51        defined(mbx821_001) )
52
53        /* 50 MHz MBX */
54        /*
55         * Note: For the mbx821_001, the following values (from the
56         * MBXA/PG2 manual) work better than, but are different
57         * from those published in the original MBXA/PG1 manual and
58         * initialized by EPPCBug 1.1. In particular, the original
59         * burst-write values do not work! Also, the following values
60         * facilitate higher performance.
61         */ 
62        /* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */
63        0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04,
64        0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005,
65
66        /*  DRAM 60ns - burst read. (offset 0x08 in UPM RAM) */
67        0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x00AF0C04,
68        0x07AF0C08, 0x0CAF0C04, 0x01AF0C04, 0x0FAF0C08,
69        0x0CAF0C04, 0x01AF0C04, 0x0FAF0C08, 0x0CAF0C04,
70        0x10AF0C04, 0xF0AFC000, 0xF3BF4805, 0xFFFFC005,
71
72        /*  DRAM 60ns - single write. (offset 0x18 in UPM RAM) */
73        0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804,
74        0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
75
76        /*  DRAM 60ns - burst write. (offset 0x20 in UPM RAM) */
77        0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C,
78        0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
79        0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005,
80        0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
81
82        /*  Refresh 60ns. (offset 0x30 in UPM RAM) */
83        0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
84        0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005,
85        0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
86 
87        /*  Exception. (offset 0x3c in UPM RAM) */
88        0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007
89
90#elif ( defined(mbx860_002b) || \
91        defined(mbx860_003b) || \
92        defined(mbx860_004b) || \
93        defined(mbx860_005b) || \
94        defined(mbx860_006b) || \
95        defined(mbx821_002b) || \
96        defined(mbx821_003b) || \
97        defined(mbx821_004b) || \
98        defined(mbx821_005b) || \
99        defined(mbx821_006b) || \
100        defined(mbx860_001) || \
101        defined(mbx860_002) || \
102        defined(mbx860_003) || \
103        defined(mbx860_004) || \
104        defined(mbx860_005) || \
105        defined(mbx821_002) || \
106        defined(mbx821_003) || \
107        defined(mbx821_004) || \
108        defined(mbx821_005) )
109
110        /* 40 MHz MBX */
111        /*
112         * Note: For the older MBX models (i.e. without the "b"
113         * suffix, e.g. mbx860_001), the following values (from the
114         * MBXA/PG2 manual) work better than, but are different
115         * from those published in the original MBXA/PG1 manual and
116         * initialized by EPPCBug 1.1. In particular, the following
117         * burst-read and burst-write values facilitate higher
118         * performance.
119         */ 
120        /* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */
121        0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00,
122        0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
123
124        /*  DRAM 60ns - burst read. (offset 0x08 in UPM RAM) */
125        0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08,
126        0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08,
127        0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005,
128        0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
129
130        /*  DRAM 60ns - single write. (offset 0x18 in UPM RAM) */
131        0xCFFF0004, 0x0FFF4004, 0x0CFF0C00, 0x33FF4804,
132        0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
133
134        /*  DRAM 60ns - burst write. (offset 0x20 in UPM RAM) */
135        0xCFFF0004, 0x0FFF4004, 0x0CFF0C00, 0x03FF0C0C,
136        0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C,
137        0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005,
138        0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
139
140        /*  Refresh 60ns. (offset 0x30 in UPM RAM) */
141        0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004,
142        0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
143        0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005,
144 
145        /*  Exception. (offset 0x3c in UPM RAM) */
146        0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007
147#else
148#error "MBX board model not specified."
149#endif
150};
151
152/*
153 *  Initialize MBX8xx
154 */
155void _InitMBX8xx (void)
156{
157  register unsigned32 r1, i;
158  extern unsigned32 simask_copy;
159
160  /*                   
161   *  Initialize the Debug Enable Register (DER) to an appropriate
162   *  value for EPPCBug debugging.
163   *  (This value should also work for BDM debugging.)
164   */
165  r1 = 0x70C67C07;      /* All except EXTIE, ALIE, DECIE */
166  _mtspr( M8xx_DER, r1 );
167 
168  /*
169   * Initialize the Instruction Support Control Register (ICTRL) to a
170   * an appropriate value for normal operation. A different value,
171   * such as 0x0, may be more appropriate for debugging.
172   */
173  r1 = 0x00000007;
174  _mtspr( M8xx_ICTRL, r1 );
175       
176  /*
177   * Disable and invalidate the instruction and data caches.
178   */
179  r1 = M8xx_CACHE_CMD_DISABLE;
180  _mtspr( M8xx_IC_CST, r1 );
181  _isync;
182  r1 = M8xx_CACHE_CMD_UNLOCKALL;
183  _mtspr( M8xx_IC_CST, r1 );
184  _isync;
185  r1 = M8xx_CACHE_CMD_INVALIDATE;       /* invalidate all */
186  _mtspr( M8xx_IC_CST, r1 );
187  _isync;
188 
189  r1 = M8xx_CACHE_CMD_DISABLE;
190  _mtspr( M8xx_DC_CST, r1 );
191  _isync;
192  r1 = M8xx_CACHE_CMD_UNLOCKALL;
193  _mtspr( M8xx_DC_CST, r1 );
194  _isync;
195  r1 = M8xx_CACHE_CMD_INVALIDATE;       /* invalidate all */
196  _mtspr( M8xx_DC_CST, r1 );
197  _isync;
198
199  /*
200   *  Initialize the Internal Memory Map Register (IMMR)
201   *
202   *  Use the value in MBXA/PG2, which is also the value that EPPC-Bug
203   *  programmed into our boards. The alternative is the value in
204   *  MBXA/PG1: 0xFFA00000. This value might well depend on the revision
205   *  of the firmware.
206   *
207   *  THIS VALUE IS ALSO DECLARED IN THE linkcmds FILE and mmutlbtab.c!
208   */
209  r1 = 0xFA200000;
210  _mtspr( M8xx_IMMR, r1 );
211
212  /*
213   *  Get the SIU interrupt mask.
214   *  imd: accessing m8xx.* should not occure before setting up the immr !
215   */
216   simask_copy = m8xx.simask;
217 
218  /*
219   * Initialize the SIU Module Configuration Register (SIUMCR)
220   * m8xx.siumcr = 0x00602900, the default MBX and firmware value.
221   */
222  m8xx.siumcr = M8xx_SIUMCR_EARP0 | M8xx_SIUMCR_DBGC3 | M8xx_SIUMCR_DBPC0 | 
223                M8xx_SIUMCR_DPC | M8xx_SIUMCR_MLRC2 | M8xx_SIUMCR_SEME;
224 
225  /*
226   * Initialize the System Protection Control Register (SYPCR).
227   * The SYPCR can only be written once after Reset.
228   *    - Enable bus monitor
229   *    - Disable software watchdog timer
230   * m8xx.sypcr = 0xFFFFFF88, the default MBX and firmware value.
231   */
232  m8xx.sypcr = M8xx_SYPCR_SWTC(0xFFFF) | M8xx_SYPCR_BMT(0xFF) | 
233                M8xx_SYPCR_BME | M8xx_SYPCR_SWF;
234
235  /* Initialize the SIU Interrupt Edge Level Mask Register (SIEL) */
236  m8xx.siel = 0xAAAA0000;               /* Default MBX and firmware value. */
237 
238  /* Initialize the Transfer Error Status Register (TESR) */
239  m8xx.tesr = 0xFFFFFFFF;               /* Default firmware value. */
240 
241  /* Initialize the SDMA Configuration Register (SDCR) */
242  m8xx.sdcr = 0x00000001;               /* Default firmware value. */
243 
244  /*
245   * Initialize the Timebase Status and Control Register (TBSCR)
246   * m8xx.tbscr = 0x00C3, default MBX and firmware value.
247   */
248  m8xx.tbscrk = M8xx_UNLOCK_KEY;        /* unlock TBSCR */
249  m8xx.tbscr = M8xx_TBSCR_REFA | M8xx_TBSCR_REFB | 
250                M8xx_TBSCR_TBF | M8xx_TBSCR_TBE;
251 
252  /* Initialize the Real-Time Clock Status and Control Register (RTCSC) */
253  m8xx.rtcsk = M8xx_UNLOCK_KEY;         /* unlock RTCSC */
254  m8xx.rtcsc = 0x00C3;                  /* Default MBX and firmware value. */
255 
256  /* Unlock other Real-Time Clock registers */
257  m8xx.rtck = M8xx_UNLOCK_KEY;          /* unlock RTC */
258  m8xx.rtseck = M8xx_UNLOCK_KEY;        /* unlock RTSEC */
259  m8xx.rtcalk = M8xx_UNLOCK_KEY;        /* unlock RTCAL */
260 
261  /* Initialize the Periodic Interrupt Status and Control Register (PISCR) */
262  m8xx.piscrk = M8xx_UNLOCK_KEY;        /* unlock PISCR */
263  m8xx.piscr = 0x0083;                  /* Default MBX and firmware value. */
264     
265  /* Initialize the System Clock and Reset Control Register (SCCR)
266   * Set the clock sources and division factors:
267   *   Timebase Source is GCLK2 / 16
268   *   Real-Time Clock Select is EXTCLK (4.192MHz)
269   *   Real-Time Clock Divide is /4
270   */
271  m8xx.sccrk = M8xx_UNLOCK_KEY;         /* unlock SCCR */
272  m8xx.sccr = 0x02800000;               /* for MBX860/MBX821 */
273
274  /* Initialize the PLL, Low-Power, and Reset Control Register (PLPRCR) */
275  /* - set the clock speed and set normal power mode */
276  m8xx.plprck = M8xx_UNLOCK_KEY;        /* unlock PLPRCR */
277#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) )
278  m8xx.plprcr = 0x5F500000;
279#elif ( defined(mbx860_005b) || \
280        defined(mbx860_002b) || \
281        defined(mbx860_003b) || \
282        defined(mbx860_004b) || \
283        defined(mbx860_006b) || \
284        defined(mbx821_002b) || \
285        defined(mbx821_003b) || \
286        defined(mbx821_004b) || \
287        defined(mbx821_005b) || \
288        defined(mbx821_006b) )
289  /* Set the multiplication factor to 0 and clear the timer interrupt status*/
290  m8xx.plprcr = 0x00005000;
291#elif ( defined(mbx860_001) || \
292        defined(mbx860_002) || \
293        defined(mbx860_003) || \
294        defined(mbx860_004) || \
295        defined(mbx860_005) || \
296        defined(mbx821_002) || \
297        defined(mbx821_003) || \
298        defined(mbx821_004) || \
299        defined(mbx821_005))
300  m8xx.plprcr = 0x4C400000;
301#else
302#error "MBX board not defined" 
303#endif
304  /* Unlock the timebase and decrementer registers. */
305  m8xx.tbk = M8xx_UNLOCK_KEY;
306  /*
307   * Initialize decrementer register to a large value to
308   * guarantee that a decrementer interrupt will not be
309   * generated before the kernel is fully initialized.
310   */
311  r1 = 0x7FFFFFFF;
312  _mtspr( M8xx_DEC, r1 );
313       
314  /* Initialize the timebase register (TB is 64 bits) */
315  r1 = 0x00000000;
316  _mtspr( M8xx_TBU_WR, r1 );
317  _mtspr( M8xx_TBL_WR, r1 );
318
319  /*
320   * Memory Controller Initialization
321   */
322
323  /*
324   * User Programmable Machine A (UPMA) Initialization
325   *
326   * If this initialization code is running from DRAM, it is very
327   * dangerous to change the value of any UPMA Ram array word from
328   * what the firmware (EPPCBug) initialized it to. Thus we don't
329   * initialize UPMA if EPPCBUG_VECTORS is defined; we assume EPPCBug
330   * has done the appropriate initialization.
331   *
332   * An exception to our rule, is that, for the older MBX boards
333   * (those without the "B" suffix, e.g. MBX821-001 and MBX860-002),
334   * we do re-initialize the burst-read and burst-write values with
335   * values that are more efficient. Also, in the MBX821 case,
336   * the burst-write original values set by EPPCBug do not work!
337   * This change can be done safely because the caches have not yet
338   * been activated.
339   *
340   * The RAM array of UPMA is initialized by writing to each of
341   * its 64 32-bit RAM locations.
342   * Note: UPM register initialization should occur before
343   * initialization of the corresponding BRx and ORx registers.
344   */
345#if ( !defined(EPPCBUG_VECTORS) )
346  for( i = 0; i < 64; ++i ) {
347    m8xx.mdr = upmaTable[i];
348    m8xx.mcr = M8xx_MEMC_MCR_WRITE | M8xx_MEMC_MCR_UPMA | M8xx_MEMC_MCR_MAD(i);
349  }
350#elif ( defined(mbx860_001) || \
351        defined(mbx860_002) || \
352        defined(mbx860_003) || \
353        defined(mbx860_004) || \
354        defined(mbx860_005) || \
355        defined(mbx821_001) || \
356        defined(mbx821_002) || \
357        defined(mbx821_003) || \
358        defined(mbx821_004) || \
359        defined(mbx821_005) )
360  /* Replace the burst-read and burst-write values with better ones. */
361  /* burst-read values */
362  for( i = 8; i < 24; ++i ) {
363    m8xx.mdr = upmaTable[i];
364    m8xx.mcr = M8xx_MEMC_MCR_WRITE | M8xx_MEMC_MCR_UPMA | M8xx_MEMC_MCR_MAD(i);
365  }
366  /* burst-write values */
367  for( i = 32; i < 48; ++i ) {
368    m8xx.mdr = upmaTable[i];
369    m8xx.mcr = M8xx_MEMC_MCR_WRITE | M8xx_MEMC_MCR_UPMA | M8xx_MEMC_MCR_MAD(i);
370  }
371#endif
372
373#if ( !defined(EPPCBUG_VECTORS) )
374  /*
375   *  Initialize the memory periodic timer.
376   *    Memory Periodic Timer Prescaler Register (MPTPR: 16-bit register)
377   *  m8xx.mptpr = 0x0200;
378   */
379  m8xx.mptpr = M8xx_MPTPR_PTP(0x2);
380 
381  /*
382   *  Initialize the Machine A Mode Register (MAMR)
383   *
384   *  ASSUMES THAT DIMMs ARE NOT INSTALLED!
385   * 
386   *  Without DIMMs:
387   *  m8xx.mamr = 0x13821000 (40 MHz) or 0x18821000 (50 MHz).
388   * 
389   *  With DIMMs:
390   *  m8xx.mamr = 0x06821000 (40 MHz) or 0x08821000 (50 MHz).
391   */
392#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) )
393  m8xx.mamr = M8xx_MEMC_MMR_PTP(0x18) | M8xx_MEMC_MMR_PTE | 
394        M8xx_MEMC_MMR_DSP(0x1) | M8xx_MEMC_MMR_G0CL(0) | M8xx_MEMC_MMR_UPWAIT;
395#else
396  m8xx.mamr = M8xx_MEMC_MMR_PTP(0x13) | M8xx_MEMC_MMR_PTE | 
397        M8xx_MEMC_MMR_DSP(0x1) | M8xx_MEMC_MMR_G0CL(0) | M8xx_MEMC_MMR_UPWAIT;
398#endif
399#endif /* ! defined(EPPCBUG_VECTORS) */
400
401  /*
402   *  Initialize the Base and Option Registers (BR0-BR7 and OR0-OR7)
403   *  Note: For all chip selects, ORx should be programmed before BRx,
404   *  except when programming the boot chip select (CS0) after hardware
405   *  reset, in which case, BR0 should be programmed before OR0.
406   *
407   *  MPC860/MPX821 Memory Map Summary:
408   *    S-ADDR    E-ADDR    CS  PS  PE  WP  MS    BI  V  DESCRIPTION
409   *    FE000000  FE7FFFFF  0   32  N   N   GPCM  Y   Y  Soldered FLASH Memory
410   *    00000000  00zFFFFF  1   32  N   N   UPMA  N   Y  Local DRAM Memory
411   *    00X00000  0XXXXXXX  2    0  N   N   UPMA  N   N  DIMM Memory - Bank #0
412   *    00X00000  0XXXXXXX  3    0  N   N   UPMA  N   N  DIMM Memory - Bank #1
413   *    FA000000  FA1FFFFF  4    8  N   N   GPCM  Y   Y  NVRAM & BCSR
414   *    80000000  DFFFFFFF  5   32  N   N   GPCM  Y   Y  PCI/ISA I/O & Memory
415   *    FA210000  FA21FFFF  6   32  N   N   GPCM  Y   Y  QSpan Registers
416   *    FC000000  FC7FFFFF  7    8  N   N   GPCM  Y   Y  Socketed FLASH Memory
417   *
418   *  z = 3 for 4MB installed on the motherboard, z = F for 16M
419   * 
420   *  NOTE: The devices selected by CS0 and CS7 can be selected with jumper J4.
421   *  This table assumes that the 32-bit soldered flash device is the boot ROM.
422   */
423
424  /*
425   *  CS0 : Soldered (32-bit) Flash Memory at 0xFE000000
426   * 
427   *  CHANGE THIS CODE IF YOU CHANGE JUMPER J4 FROM ITS FACTORY DEFAULT SETTING!
428   *  (or better yet, don't reprogram BR0 and OR0; just program BR7 and OR7 to
429   *  access whatever flash device is not selected during hard reset.)
430   *
431   *  MBXA/PG2 appears to lie in note 14 for table 2-4. The manual states that
432   *  "EPPCBUG configures the reset flash device at the lower address, and the
433   *  nonreset flash device at the higher address." If we take reset flash device
434   *  to mean the boot flash memory, then the statement must mean that BR0 must
435   *  point to the device at the lower address, i.e. 0xFC000000, while BR7 must
436   *  point to the device at the highest address, i.e. 0xFE000000.
437   * 
438   *  THIS IS NOT THE CASE!
439   * 
440   *  The boot flash is always configured to start at 0xFE000000, and the other
441   *  one to start at 0xFC000000. Changing jumper J4 only changes the width of
442   *  the memory ports into these two region.
443   * 
444   * BR0 = 0xFE000001
445   *    Base addr [0-16]        0b11111110000000000 = 0xFE000000
446   *    Address type [17-19]    0b000
447   *    Port size [20-21]       0b00 = 32 bits
448   *    Parity enable [22]      0b0 = disabled
449   *    Write protect [23]      0b0 = r/w
450   *    Machine select [24-25]  0b00 = GPCM
451   *    Reserved [26-30]        0b00000
452   *    Valid Bit [31]          0b1 = this bank is valid
453   * OR0 = 0xFF800930 @ 40 MHz, 0xFF800940 @ 50 MHz
454   *    Address mask [0-16]     0b11111111100000000 = 0xFF800000
455   *    Addr type mask [17-19]  0b000 = no address-type protection
456   *    CS negation time [20]   0b1
457   *    ACS [21-22]             0b00 = CS output at same time as address lines
458   *    Burst inhibit [23]      0b1 = bank does not support burst accesses
459   *    Cycle length [24-27]    0b0011/0b0100 = 3/4 clock cycle wait states
460   *    SETA [28]               0b0 = TA generated internally
461   *    Timing relaxed [29]     0b0 = not relaxed
462   *    Extended hold time [30] 0b0 = not extended
463   *    Reserved [31]           0b0
464   *
465   * m8xx.memc[0]._or = 0xFF800930 (40 MHz)
466   * m8xx.memc[0]._or = 0xFF800940 (50 MHz)
467   * m8xx.memc[0]._br = 0xFE000001
468   */
469#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) )
470  m8xx.memc[0]._or = M8xx_MEMC_OR_8M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT |
471                M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(4);
472#else
473  m8xx.memc[0]._or = M8xx_MEMC_OR_8M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT |
474                M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(3);
475#endif
476  m8xx.memc[0]._br = M8xx_BR_BA(0xFE000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 |
477                M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V;
478
479  /*
480   * CS1 : Local DRAM Memory at 0x00000000
481   * m8xx.memc[1]._or = 0xFFC00400;
482   * m8xx.memc[1]._br = 0x00000081;
483   */
484#if ( defined(mbx860_001b) )
485    m8xx.memc[1]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) | 
486    M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0);
487#elif ( defined(mbx860_002b) || \
488         defined(mbx860_003b) || \
489         defined(mbx821_001b) || \
490         defined(mbx821_002b) || \
491         defined(mbx821_003b) || \
492         defined(mbx860_001)  || \
493         defined(mbx860_002)  || \
494         defined(mbx860_003)  || \
495         defined(mbx821_001)  || \
496         defined(mbx821_002)  || \
497         defined(mbx821_003) )
498    m8xx.memc[1]._or = M8xx_MEMC_OR_4M | M8xx_MEMC_OR_ATM(0) | 
499    M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0);
500#elif ( defined(mbx860_004) || \
501        defined(mbx860_005) || \
502        defined(mbx860_004b) || \
503        defined(mbx860_005b) || \
504        defined(mbx860_006b) || \
505        defined(mbx821_004) || \
506        defined(mbx821_005) || \
507        defined(mbx821_004b) || \
508        defined(mbx821_005b) || \
509        defined(mbx821_006b) )
510    m8xx.memc[1]._or = M8xx_MEMC_OR_16M | M8xx_MEMC_OR_ATM(0) | 
511      M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0);
512#else
513#error "MBX board not defined"
514#endif
515  m8xx.memc[1]._br = M8xx_BR_BA(0x00000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 |
516                M8xx_BR_MS_UPMA | M8xx_MEMC_BR_V;
517
518  /*
519   * CS2 : DIMM Memory - Bank #0, not present
520   * m8xx.memc[2]._or = 0x00000400;
521   * m8xx.memc[2]._br = 0x00000080;
522   */
523  m8xx.memc[2]._or = M8xx_MEMC_OR_ATM(0) | 
524                M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0);
525  m8xx.memc[2]._br = M8xx_BR_AT(0) | M8xx_BR_PS32 |
526                M8xx_BR_MS_UPMA;        /* ! M8xx_MEMC_BR_V */
527
528  /*
529   * CS3 : DIMM Memory - Bank #1, not present
530   * m8xx.memc[3]._or = 0x00000400;
531   * m8xx.memc[3]._br = 0x00000080;
532   */
533  m8xx.memc[3]._or = M8xx_MEMC_OR_ATM(0) | 
534                M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0);
535  m8xx.memc[3]._br = M8xx_BR_AT(0) | M8xx_BR_PS32 |
536                M8xx_BR_MS_UPMA;        /* ! M8xx_MEMC_BR_V */
537
538  /*
539   * CS4 : Battery-Backed SRAM at 0xFA000000
540   * m8xx.memc[4]._or = 0xFFE00920@ 40 MHz, 0xFFE00930 @ 50 MHz
541   * m8xx.memc[4]._br = 0xFA000401;
542   */
543#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) )
544  m8xx.memc[4]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT |
545                M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(3);
546#else
547  m8xx.memc[4]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT |
548                M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(2);
549#endif
550  m8xx.memc[4]._br = M8xx_BR_BA(0xFA000000) | M8xx_BR_AT(0) | M8xx_BR_PS8 |
551                M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V;
552
553  /*
554   * CS5 : PCI I/O and Memory at 0x80000000
555   * m8xx.memc[5]._or = 0xA0000108;
556   * m8xx.memc[5]._br = 0x80000001;
557   */
558  m8xx.memc[5]._or = 0xA0000000 | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_NORM |
559                M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(0) | M8xx_MEMC_OR_SETA;
560  m8xx.memc[5]._br = M8xx_BR_BA(0x80000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 |
561                M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V;
562
563  /*
564   * CS6 : QSPAN Registers at 0xFA210000
565   * m8xx.memc[6]._or = 0xFFFF0108;
566   * m8xx.memc[6]._br = 0xFA210001;
567   */
568  m8xx.memc[6]._or = M8xx_MEMC_OR_64K | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_NORM |
569                M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(0) | M8xx_MEMC_OR_SETA;
570  m8xx.memc[6]._br = M8xx_BR_BA(0xFA210000) | M8xx_BR_AT(0) | M8xx_BR_PS32 |
571                M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V;
572
573  /*
574   * CS7 : Socketed (8-bit) Flash at 0xFC000000
575   * m8xx.memc[7]._or = 0xFF800930 @ 40 MHz, 0xFF800940 @ 50 MHz
576   * m8xx.memc[7]._br = 0xFC000401;
577   */
578#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) )
579  m8xx.memc[7]._or = M8xx_MEMC_OR_8M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT |
580                M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(4);
581#else
582   m8xx.memc[7]._or = M8xx_MEMC_OR_8M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT |
583                M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(3);
584#endif
585  m8xx.memc[7]._br = M8xx_BR_BA(0xFC000000) | M8xx_BR_AT(0) | M8xx_BR_PS8 |
586                M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V;
587  /*
588   * PCMCIA initialization
589   */
590  /*
591   * PCMCIA region 0: common memory
592   */
593  m8xx.pbr0 = PCMCIA_MEM_ADDR;
594  m8xx.por0 = (M8xx_PCMCIA_POR_BSIZE_64MB
595               | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) 
596               | M8xx_PCMCIA_POR_PSL(32) 
597               | M8xx_PCMCIA_POR_PPS_16   | M8xx_PCMCIA_POR_PRS_MEM
598               |M8xx_PCMCIA_POR_PSLOT_A   |  M8xx_PCMCIA_POR_VALID);
599  /*
600   * PCMCIA region 1: dma memory
601   */
602  m8xx.pbr1 = PCMCIA_DMA_ADDR;
603  m8xx.por1 = (M8xx_PCMCIA_POR_BSIZE_64MB
604               | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) 
605               | M8xx_PCMCIA_POR_PSL(32) 
606               | M8xx_PCMCIA_POR_PPS_16   | M8xx_PCMCIA_POR_PRS_DMA
607               |M8xx_PCMCIA_POR_PSLOT_A   |  M8xx_PCMCIA_POR_VALID);
608  /*
609   * PCMCIA region 2: attribute memory
610   */
611  m8xx.pbr2 = PCMCIA_ATTRB_ADDR;
612  m8xx.por2 = (M8xx_PCMCIA_POR_BSIZE_64MB
613               | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) 
614               | M8xx_PCMCIA_POR_PSL(32) 
615               | M8xx_PCMCIA_POR_PPS_16   | M8xx_PCMCIA_POR_PRS_ATT
616               |M8xx_PCMCIA_POR_PSLOT_A   |  M8xx_PCMCIA_POR_VALID);
617  /*
618   * PCMCIA region 3: I/O access
619   */
620  m8xx.pbr3 = PCMCIA_IO_ADDR;
621  m8xx.por3 = (M8xx_PCMCIA_POR_BSIZE_64MB
622               | M8xx_PCMCIA_POR_PSHT(15) | M8xx_PCMCIA_POR_PSST(15) 
623               | M8xx_PCMCIA_POR_PSL(32) 
624               | M8xx_PCMCIA_POR_PPS_16   | M8xx_PCMCIA_POR_PRS_IO
625               |M8xx_PCMCIA_POR_PSLOT_A   |  M8xx_PCMCIA_POR_VALID);
626
627  /*
628   * PCMCIA interface general control reg
629   */
630  m8xx.pgcra = 0; /* no special options set */
631  /*
632   * PCMCIA interface enable reg
633   */
634  m8xx.per   =0; /* no interrupts enabled now */
635}
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