[8ef3818] | 1 | /* |
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| 2 | * imbx8xx.c |
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| 3 | * |
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| 4 | * MBX860/MBX821 initialization routines. |
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| 5 | * |
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| 6 | * Copyright (c) 1999, National Research Council of Canada |
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| 7 | * |
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| 8 | * The license and distribution terms for this file may be |
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| 9 | * found in the file LICENSE in this distribution or at |
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| 10 | * http://www.OARcorp.com/rtems/license.html. |
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| 11 | */ |
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| 12 | |
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| 13 | #include <bsp.h> |
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| 14 | |
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| 15 | /* |
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| 16 | * EPPCBug rev 1.1 is stupid. It clears the interrupt mask register |
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| 17 | * in the SIU when it takes control, but does not restore it before |
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| 18 | * returning control to the program. We thus keep a copy of the |
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| 19 | * register, and restore it from gdb using the hook facilities. |
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| 20 | * |
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| 21 | * We arrange for simask_copy to be initialized to zero so that |
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| 22 | * it resides in the .data section. This avoids having gdb set |
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| 23 | * the mask to crud before we get to initialize explicitly. Of |
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| 24 | * course, the code will not be safely restartable, but then again, |
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| 25 | * a lot of the library code isn't either, so there! |
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| 26 | */ |
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| 27 | unsigned32 simask_copy = 0; |
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| 28 | |
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| 29 | /* |
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| 30 | * The memory controller's UPMA Ram array values. |
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| 31 | * The values in table 2-6 and 2-7 in the "MBX Series Embedded |
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| 32 | * Controller Programmer's Reference Guide", part number MBXA/PG2, |
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| 33 | * differ from the ones in the older MBX Programmer's Guide, part |
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| 34 | * number MBXA/PG1. We are assuming that the values in MBXA/PG1 |
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| 35 | * are for the older MBX boards whose part number does not have |
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| 36 | * the "B" suffix, but we have discovered that the values from |
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| 37 | * MBXA/PG2 work better, even for the older boards. |
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| 38 | * |
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| 39 | * THESE VALUES HAVE ONLY BEEN VERIFIED FOR THE MBX821-001 and |
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| 40 | * MBX860-002. USE WITH CARE! |
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| 41 | * |
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| 42 | * NOTE: The MBXA/PG2 manual lists the clock speed of the MBX821_001B |
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| 43 | * as being 50 MHz, while the MBXA/IH2.1 manual lists it as 40 MHz. |
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| 44 | * We think the MBX821_001B is an entry level board and thus is 50 MHz, |
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| 45 | */ |
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| 46 | static unsigned32 upmaTable[64] = { |
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| 47 | |
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| 48 | #if ( defined(mbx860_001b) || \ |
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| 49 | defined(mbx821_001b) || \ |
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| 50 | defined(mbx821_001) ) |
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| 51 | |
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| 52 | /* 50 MHz MBX */ |
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| 53 | /* |
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| 54 | * Note: For the mbx821_001, the following values (from the |
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| 55 | * MBXA/PG2 manual) work better than, but are different |
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| 56 | * from those published in the original MBXA/PG1 manual and |
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| 57 | * initialized by EPPCBug 1.1. In particular, the original |
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| 58 | * burst-write values do not work! Also, the following values |
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| 59 | * facilitate higher performance. |
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| 60 | */ |
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| 61 | /* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */ |
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| 62 | 0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x10AF0C04, |
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| 63 | 0xF0AF0C00, 0xF3BF4805, 0xFFFFC005, 0xFFFFC005, |
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| 64 | |
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| 65 | /* DRAM 60ns - burst read. (offset 0x08 in UPM RAM) */ |
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| 66 | 0xCFAFC004, 0x0FAFC404, 0x0CAF8C04, 0x00AF0C04, |
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| 67 | 0x07AF0C08, 0x0CAF0C04, 0x01AF0C04, 0x0FAF0C08, |
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| 68 | 0x0CAF0C04, 0x01AF0C04, 0x0FAF0C08, 0x0CAF0C04, |
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| 69 | 0x10AF0C04, 0xF0AFC000, 0xF3BF4805, 0xFFFFC005, |
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| 70 | |
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| 71 | /* DRAM 60ns - single write. (offset 0x18 in UPM RAM) */ |
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| 72 | 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x13FF4804, |
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| 73 | 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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| 74 | |
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| 75 | /* DRAM 60ns - burst write. (offset 0x20 in UPM RAM) */ |
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| 76 | 0xCFFF0004, 0x0FFF0404, 0x0CFF0C00, 0x03FF0C0C, |
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| 77 | 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, |
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| 78 | 0x0CFF0C00, 0x13FF4804, 0xFFFFC004, 0xFFFFC005, |
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| 79 | 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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| 80 | |
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| 81 | /* Refresh 60ns. (offset 0x30 in UPM RAM) */ |
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| 82 | 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, |
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| 83 | 0x1FFFC004, 0xFFFFC004, 0xFFFFC005, 0xFFFFC005, |
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| 84 | 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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| 85 | |
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| 86 | /* Exception. (offset 0x3c in UPM RAM) */ |
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| 87 | 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007 |
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| 88 | |
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| 89 | #elif ( defined(mbx860_002b) || \ |
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| 90 | defined(mbx860_003b) || \ |
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| 91 | defined(mbx860_004b) || \ |
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| 92 | defined(mbx860_005b) || \ |
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| 93 | defined(mbx860_006b) || \ |
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| 94 | defined(mbx821_002b) || \ |
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| 95 | defined(mbx821_003b) || \ |
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| 96 | defined(mbx821_004b) || \ |
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| 97 | defined(mbx821_005b) || \ |
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| 98 | defined(mbx821_006b) || \ |
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| 99 | defined(mbx860_001) || \ |
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| 100 | defined(mbx860_002) || \ |
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| 101 | defined(mbx860_003) || \ |
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| 102 | defined(mbx860_004) || \ |
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| 103 | defined(mbx860_005) || \ |
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| 104 | defined(mbx821_002) || \ |
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| 105 | defined(mbx821_003) || \ |
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| 106 | defined(mbx821_004) || \ |
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| 107 | defined(mbx821_005) ) |
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| 108 | |
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| 109 | /* 40 MHz MBX */ |
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| 110 | /* |
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| 111 | * Note: For the older MBX models (i.e. without the "b" |
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| 112 | * suffix, e.g. mbx860_001), the following values (from the |
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| 113 | * MBXA/PG2 manual) work better than, but are different |
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| 114 | * from those published in the original MBXA/PG1 manual and |
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| 115 | * initialized by EPPCBug 1.1. In particular, the following |
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| 116 | * burst-read and burst-write values facilitate higher |
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| 117 | * performance. |
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| 118 | */ |
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| 119 | /* DRAM 60ns - single read. (offset 0x00 in UPM RAM) */ |
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| 120 | 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x30AF0C00, |
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| 121 | 0xF1BF4805, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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| 122 | |
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| 123 | /* DRAM 60ns - burst read. (offset 0x08 in UPM RAM) */ |
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| 124 | 0xCFAFC004, 0x0FAFC404, 0x0CAF0C04, 0x03AF0C08, |
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| 125 | 0x0CAF0C04, 0x03AF0C08, 0x0CAF0C04, 0x03AF0C08, |
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| 126 | 0x0CAF0C04, 0x30AF0C00, 0xF3BF4805, 0xFFFFC005, |
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| 127 | 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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| 128 | |
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| 129 | /* DRAM 60ns - single write. (offset 0x18 in UPM RAM) */ |
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| 130 | 0xCFFF0004, 0x0FFF4004, 0x0CFF0C00, 0x33FF4804, |
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| 131 | 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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| 132 | |
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| 133 | /* DRAM 60ns - burst write. (offset 0x20 in UPM RAM) */ |
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| 134 | 0xCFFF0004, 0x0FFF4004, 0x0CFF0C00, 0x03FF0C0C, |
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| 135 | 0x0CFF0C00, 0x03FF0C0C, 0x0CFF0C00, 0x03FF0C0C, |
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| 136 | 0x0CFF0C00, 0x33FF4804, 0xFFFFC005, 0xFFFFC005, |
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| 137 | 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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| 138 | |
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| 139 | /* Refresh 60ns. (offset 0x30 in UPM RAM) */ |
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| 140 | 0xFCFFC004, 0xC0FFC004, 0x01FFC004, 0x0FFFC004, |
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| 141 | 0x3FFFC004, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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| 142 | 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, 0xFFFFC005, |
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| 143 | |
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| 144 | /* Exception. (offset 0x3c in UPM RAM) */ |
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| 145 | 0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007 |
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| 146 | #else |
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| 147 | #error "MBX board model not specified." |
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| 148 | #endif |
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| 149 | }; |
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| 150 | |
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| 151 | /* |
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| 152 | * Initialize MBX8xx |
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| 153 | */ |
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| 154 | void _InitMBX8xx (void) |
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| 155 | { |
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| 156 | register unsigned32 r1, i; |
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| 157 | extern unsigned32 simask_copy; |
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| 158 | |
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| 159 | /* |
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| 160 | * Get the SIU interrupt mask. |
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| 161 | */ |
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| 162 | simask_copy = m8xx.simask; |
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| 163 | |
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| 164 | /* |
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| 165 | * Initialize the Debug Enable Register (DER) to an appropriate |
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| 166 | * value for EPPCBug debugging. |
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| 167 | * (This value should also work for BDM debugging.) |
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| 168 | */ |
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| 169 | r1 = 0x70C67C07; /* All except EXTIE, ALIE, DECIE */ |
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| 170 | _mtspr( M8xx_DER, r1 ); |
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| 171 | |
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| 172 | /* |
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| 173 | * Initialize the Instruction Support Control Register (ICTRL) to a |
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| 174 | * an appropriate value for normal operation. A different value, |
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| 175 | * such as 0x0, may be more appropriate for debugging. |
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| 176 | */ |
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| 177 | r1 = 0x00000007; |
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| 178 | _mtspr( M8xx_ICTRL, r1 ); |
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| 179 | |
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| 180 | /* |
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| 181 | * Disable and invalidate the instruction and data caches. |
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| 182 | */ |
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| 183 | r1 = M8xx_CACHE_CMD_DISABLE; |
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| 184 | _mtspr( M8xx_IC_CST, r1 ); |
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| 185 | _isync; |
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| 186 | r1 = M8xx_CACHE_CMD_UNLOCKALL; |
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| 187 | _mtspr( M8xx_IC_CST, r1 ); |
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| 188 | _isync; |
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| 189 | r1 = M8xx_CACHE_CMD_INVALIDATE; /* invalidate all */ |
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| 190 | _mtspr( M8xx_IC_CST, r1 ); |
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| 191 | _isync; |
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| 192 | |
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| 193 | r1 = M8xx_CACHE_CMD_DISABLE; |
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| 194 | _mtspr( M8xx_DC_CST, r1 ); |
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| 195 | _isync; |
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| 196 | r1 = M8xx_CACHE_CMD_UNLOCKALL; |
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| 197 | _mtspr( M8xx_DC_CST, r1 ); |
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| 198 | _isync; |
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| 199 | r1 = M8xx_CACHE_CMD_INVALIDATE; /* invalidate all */ |
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| 200 | _mtspr( M8xx_DC_CST, r1 ); |
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| 201 | _isync; |
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| 202 | |
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| 203 | /* |
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| 204 | * Initialize the Internal Memory Map Register (IMMR) |
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| 205 | * |
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| 206 | * Use the value in MBXA/PG2, which is also the value that EPPC-Bug |
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| 207 | * programmed into our boards. The alternative is the value in |
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| 208 | * MBXA/PG1: 0xFFA00000. This value might well depend on the revision |
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| 209 | * of the firmware. |
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| 210 | * |
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| 211 | * THIS VALUE IS ALSO DECLARED IN THE linkcmds FILE and mmutlbtab.c! |
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| 212 | */ |
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| 213 | r1 = 0xFA200000; |
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| 214 | _mtspr( M8xx_IMMR, r1 ); |
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| 215 | |
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| 216 | /* |
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| 217 | * Initialize the SIU Module Configuration Register (SIUMCR) |
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| 218 | * m8xx.siumcr = 0x00602900, the default MBX and firmware value. |
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| 219 | */ |
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| 220 | m8xx.siumcr = M8xx_SIUMCR_EARP0 | M8xx_SIUMCR_DBGC3 | M8xx_SIUMCR_DBPC0 | |
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| 221 | M8xx_SIUMCR_DPC | M8xx_SIUMCR_MLRC2 | M8xx_SIUMCR_SEME; |
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| 222 | |
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| 223 | /* |
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| 224 | * Initialize the System Protection Control Register (SYPCR). |
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| 225 | * The SYPCR can only be written once after Reset. |
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| 226 | * - Enable bus monitor |
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| 227 | * - Disable software watchdog timer |
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| 228 | * m8xx.sypcr = 0xFFFFFF88, the default MBX and firmware value. |
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| 229 | */ |
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| 230 | m8xx.sypcr = M8xx_SYPCR_SWTC(0xFFFF) | M8xx_SYPCR_BMT(0xFF) | |
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| 231 | M8xx_SYPCR_BME | M8xx_SYPCR_SWF; |
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| 232 | |
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| 233 | /* Initialize the SIU Interrupt Edge Level Mask Register (SIEL) */ |
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| 234 | m8xx.siel = 0xAAAA0000; /* Default MBX and firmware value. */ |
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| 235 | |
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| 236 | /* Initialize the Transfer Error Status Register (TESR) */ |
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| 237 | m8xx.tesr = 0xFFFFFFFF; /* Default firmware value. */ |
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| 238 | |
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| 239 | /* Initialize the SDMA Configuration Register (SDCR) */ |
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| 240 | m8xx.sdcr = 0x00000001; /* Default firmware value. */ |
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| 241 | |
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| 242 | /* |
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| 243 | * Initialize the Timebase Status and Control Register (TBSCR) |
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| 244 | * m8xx.tbscr = 0x00C3, default MBX and firmware value. |
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| 245 | */ |
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| 246 | m8xx.tbscrk = M8xx_UNLOCK_KEY; /* unlock TBSCR */ |
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| 247 | m8xx.tbscr = M8xx_TBSCR_REFA | M8xx_TBSCR_REFB | |
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| 248 | M8xx_TBSCR_TBF | M8xx_TBSCR_TBE; |
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| 249 | |
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| 250 | /* Initialize the Real-Time Clock Status and Control Register (RTCSC) */ |
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| 251 | m8xx.rtcsk = M8xx_UNLOCK_KEY; /* unlock RTCSC */ |
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| 252 | m8xx.rtcsc = 0x00C3; /* Default MBX and firmware value. */ |
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| 253 | |
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| 254 | /* Unlock other Real-Time Clock registers */ |
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| 255 | m8xx.rtck = M8xx_UNLOCK_KEY; /* unlock RTC */ |
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| 256 | m8xx.rtseck = M8xx_UNLOCK_KEY; /* unlock RTSEC */ |
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| 257 | m8xx.rtcalk = M8xx_UNLOCK_KEY; /* unlock RTCAL */ |
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| 258 | |
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| 259 | /* Initialize the Periodic Interrupt Status and Control Register (PISCR) */ |
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| 260 | m8xx.piscrk = M8xx_UNLOCK_KEY; /* unlock PISCR */ |
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| 261 | m8xx.piscr = 0x0083; /* Default MBX and firmware value. */ |
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| 262 | |
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| 263 | /* Initialize the System Clock and Reset Control Register (SCCR) |
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| 264 | * Set the clock sources and division factors: |
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| 265 | * Timebase Source is GCLK2 / 16 |
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| 266 | * Real-Time Clock Select is EXTCLK (4.192MHz) |
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| 267 | * Real-Time Clock Divide is /4 |
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| 268 | */ |
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| 269 | m8xx.sccrk = M8xx_UNLOCK_KEY; /* unlock SCCR */ |
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| 270 | m8xx.sccr = 0x02800000; /* for MBX860/MBX821 */ |
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| 271 | |
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| 272 | /* Initialize the PLL, Low-Power, and Reset Control Register (PLPRCR) */ |
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| 273 | /* - set the clock speed and set normal power mode */ |
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| 274 | m8xx.plprck = M8xx_UNLOCK_KEY; /* unlock PLPRCR */ |
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| 275 | #if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) |
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| 276 | m8xx.plprcr = 0x5F500000; |
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[168ba07] | 277 | #elif ( defined(mbx860_005b) ) |
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| 278 | /* Set the multiplication factor to 0 and clear the timer interrupt status*/ |
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| 279 | m8xx.plprcr = 0x00005000; |
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| 280 | #elif ( defined(mbx860_001) || \ |
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| 281 | defined(mbx860_002) || \ |
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| 282 | defined(mbx860_003) || \ |
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| 283 | defined(mbx860_004) || \ |
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| 284 | defined(mbx860_005) || \ |
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| 285 | defined(mbx860_002b) || \ |
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| 286 | defined(mbx860_003b) || \ |
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| 287 | defined(mbx860_004b) || \ |
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| 288 | defined(mbx860_006b) || \ |
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| 289 | defined(mbx821_002) || \ |
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| 290 | defined(mbx821_003) || \ |
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| 291 | defined(mbx821_004) || \ |
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| 292 | defined(mbx821_005) || \ |
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| 293 | defined(mbx821_002b) || \ |
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| 294 | defined(mbx821_003b) || \ |
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| 295 | defined(mbx821_004b) || \ |
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[9df5323] | 296 | defined(mbx821_005b) || \ |
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[168ba07] | 297 | defined(mbx821_006b) ) |
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[8ef3818] | 298 | m8xx.plprcr = 0x4C400000; |
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[168ba07] | 299 | #else |
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| 300 | #error "MBX board not defined" |
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[8ef3818] | 301 | #endif |
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| 302 | /* Unlock the timebase and decrementer registers. */ |
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| 303 | m8xx.tbk = M8xx_UNLOCK_KEY; |
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| 304 | /* |
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| 305 | * Initialize decrementer register to a large value to |
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| 306 | * guarantee that a decrementer interrupt will not be |
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| 307 | * generated before the kernel is fully initialized. |
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| 308 | */ |
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| 309 | r1 = 0x7FFFFFFF; |
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| 310 | _mtspr( M8xx_DEC, r1 ); |
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| 311 | |
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| 312 | /* Initialize the timebase register (TB is 64 bits) */ |
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| 313 | r1 = 0x00000000; |
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| 314 | _mtspr( M8xx_TBU_WR, r1 ); |
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| 315 | _mtspr( M8xx_TBL_WR, r1 ); |
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| 316 | |
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| 317 | /* |
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| 318 | * Memory Controller Initialization |
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| 319 | */ |
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| 320 | |
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| 321 | /* |
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| 322 | * User Programmable Machine A (UPMA) Initialization |
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| 323 | * |
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| 324 | * If this initialization code is running from DRAM, it is very |
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| 325 | * dangerous to change the value of any UPMA Ram array word from |
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| 326 | * what the firmware (EPPCBug) initialized it to. Thus we don't |
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| 327 | * initialize UPMA if EPPCBUG_VECTORS is defined; we assume EPPCBug |
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| 328 | * has done the appropriate initialization. |
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| 329 | * |
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| 330 | * An exception to our rule, is that, for the older MBX boards |
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| 331 | * (those without the "B" suffix, e.g. MBX821-001 and MBX860-002), |
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| 332 | * we do re-initialize the burst-read and burst-write values with |
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| 333 | * values that are more efficient. Also, in the MBX821 case, |
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| 334 | * the burst-write original values set by EPPCBug do not work! |
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| 335 | * This change can be done safely because the caches have not yet |
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| 336 | * been activated. |
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| 337 | * |
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| 338 | * The RAM array of UPMA is initialized by writing to each of |
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| 339 | * its 64 32-bit RAM locations. |
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| 340 | * Note: UPM register initialization should occur before |
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| 341 | * initialization of the corresponding BRx and ORx registers. |
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| 342 | */ |
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| 343 | #if ( !defined(EPPCBUG_VECTORS) ) |
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| 344 | for( i = 0; i < 64; ++i ) { |
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| 345 | m8xx.mdr = upmaTable[i]; |
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| 346 | m8xx.mcr = M8xx_MEMC_MCR_WRITE | M8xx_MEMC_MCR_UPMA | M8xx_MEMC_MCR_MAD(i); |
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| 347 | } |
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| 348 | #elif ( defined(mbx860_001) || \ |
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| 349 | defined(mbx860_002) || \ |
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| 350 | defined(mbx860_003) || \ |
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| 351 | defined(mbx860_004) || \ |
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| 352 | defined(mbx860_005) || \ |
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| 353 | defined(mbx821_001) || \ |
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| 354 | defined(mbx821_002) || \ |
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| 355 | defined(mbx821_003) || \ |
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| 356 | defined(mbx821_004) || \ |
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| 357 | defined(mbx821_005) ) |
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| 358 | /* Replace the burst-read and burst-write values with better ones. */ |
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| 359 | /* burst-read values */ |
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| 360 | for( i = 8; i < 24; ++i ) { |
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| 361 | m8xx.mdr = upmaTable[i]; |
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| 362 | m8xx.mcr = M8xx_MEMC_MCR_WRITE | M8xx_MEMC_MCR_UPMA | M8xx_MEMC_MCR_MAD(i); |
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| 363 | } |
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| 364 | /* burst-write values */ |
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| 365 | for( i = 32; i < 48; ++i ) { |
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| 366 | m8xx.mdr = upmaTable[i]; |
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| 367 | m8xx.mcr = M8xx_MEMC_MCR_WRITE | M8xx_MEMC_MCR_UPMA | M8xx_MEMC_MCR_MAD(i); |
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| 368 | } |
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| 369 | #endif |
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| 370 | |
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| 371 | #if ( !defined(EPPCBUG_VECTORS) ) |
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| 372 | /* |
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| 373 | * Initialize the memory periodic timer. |
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| 374 | * Memory Periodic Timer Prescaler Register (MPTPR: 16-bit register) |
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| 375 | * m8xx.mptpr = 0x0200; |
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| 376 | */ |
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| 377 | m8xx.mptpr = M8xx_MPTPR_PTP(0x2); |
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| 378 | |
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| 379 | /* |
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| 380 | * Initialize the Machine A Mode Register (MAMR) |
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| 381 | * |
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| 382 | * ASSUMES THAT DIMMs ARE NOT INSTALLED! |
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| 383 | * |
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| 384 | * Without DIMMs: |
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| 385 | * m8xx.mamr = 0x13821000 (40 MHz) or 0x18821000 (50 MHz). |
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| 386 | * |
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| 387 | * With DIMMs: |
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| 388 | * m8xx.mamr = 0x06821000 (40 MHz) or 0x08821000 (50 MHz). |
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| 389 | */ |
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| 390 | #if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) |
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| 391 | m8xx.mamr = M8xx_MEMC_MMR_PTP(0x18) | M8xx_MEMC_MMR_PTE | |
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| 392 | M8xx_MEMC_MMR_DSP(0x1) | M8xx_MEMC_MMR_G0CL(0) | M8xx_MEMC_MMR_UPWAIT; |
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| 393 | #else |
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| 394 | m8xx.mamr = M8xx_MEMC_MMR_PTP(0x13) | M8xx_MEMC_MMR_PTE | |
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| 395 | M8xx_MEMC_MMR_DSP(0x1) | M8xx_MEMC_MMR_G0CL(0) | M8xx_MEMC_MMR_UPWAIT; |
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| 396 | #endif |
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| 397 | #endif /* ! defined(EPPCBUG_VECTORS) */ |
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| 398 | |
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| 399 | /* |
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| 400 | * Initialize the Base and Option Registers (BR0-BR7 and OR0-OR7) |
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| 401 | * Note: For all chip selects, ORx should be programmed before BRx, |
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| 402 | * except when programming the boot chip select (CS0) after hardware |
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| 403 | * reset, in which case, BR0 should be programmed before OR0. |
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| 404 | * |
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| 405 | * MPC860/MPX821 Memory Map Summary: |
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| 406 | * S-ADDR E-ADDR CS PS PE WP MS BI V DESCRIPTION |
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| 407 | * FE000000 FE7FFFFF 0 32 N N GPCM Y Y Soldered FLASH Memory |
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| 408 | * 00000000 00zFFFFF 1 32 N N UPMA N Y Local DRAM Memory |
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| 409 | * 00X00000 0XXXXXXX 2 0 N N UPMA N N DIMM Memory - Bank #0 |
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| 410 | * 00X00000 0XXXXXXX 3 0 N N UPMA N N DIMM Memory - Bank #1 |
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| 411 | * FA000000 FA1FFFFF 4 8 N N GPCM Y Y NVRAM & BCSR |
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| 412 | * 80000000 DFFFFFFF 5 32 N N GPCM Y Y PCI/ISA I/O & Memory |
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| 413 | * FA210000 FA21FFFF 6 32 N N GPCM Y Y QSpan Registers |
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| 414 | * FC000000 FC7FFFFF 7 8 N N GPCM Y Y Socketed FLASH Memory |
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| 415 | * |
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| 416 | * z = 3 for 4MB installed on the motherboard, z = F for 16M |
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| 417 | * |
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| 418 | * NOTE: The devices selected by CS0 and CS7 can be selected with jumper J4. |
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| 419 | * This table assumes that the 32-bit soldered flash device is the boot ROM. |
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| 420 | */ |
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| 421 | |
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| 422 | /* |
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| 423 | * CS0 : Soldered (32-bit) Flash Memory at 0xFE000000 |
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| 424 | * |
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| 425 | * CHANGE THIS CODE IF YOU CHANGE JUMPER J4 FROM ITS FACTORY DEFAULT SETTING! |
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| 426 | * (or better yet, don't reprogram BR0 and OR0; just program BR7 and OR7 to |
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| 427 | * access whatever flash device is not selected during hard reset.) |
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| 428 | * |
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| 429 | * MBXA/PG2 appears to lie in note 14 for table 2-4. The manual states that |
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| 430 | * "EPPCBUG configures the reset flash device at the lower address, and the |
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| 431 | * nonreset flash device at the higher address." If we take reset flash device |
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| 432 | * to mean the boot flash memory, then the statement must mean that BR0 must |
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| 433 | * point to the device at the lower address, i.e. 0xFC000000, while BR7 must |
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| 434 | * point to the device at the highest address, i.e. 0xFE000000. |
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| 435 | * |
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| 436 | * THIS IS NOT THE CASE! |
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| 437 | * |
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| 438 | * The boot flash is always configured to start at 0xFE000000, and the other |
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| 439 | * one to start at 0xFC000000. Changing jumper J4 only changes the width of |
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| 440 | * the memory ports into these two region. |
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| 441 | * |
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| 442 | * BR0 = 0xFE000001 |
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| 443 | * Base addr [0-16] 0b11111110000000000 = 0xFE000000 |
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| 444 | * Address type [17-19] 0b000 |
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| 445 | * Port size [20-21] 0b00 = 32 bits |
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| 446 | * Parity enable [22] 0b0 = disabled |
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| 447 | * Write protect [23] 0b0 = r/w |
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| 448 | * Machine select [24-25] 0b00 = GPCM |
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| 449 | * Reserved [26-30] 0b00000 |
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| 450 | * Valid Bit [31] 0b1 = this bank is valid |
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| 451 | * OR0 = 0xFF800930 @ 40 MHz, 0xFF800940 @ 50 MHz |
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| 452 | * Address mask [0-16] 0b11111111100000000 = 0xFF800000 |
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| 453 | * Addr type mask [17-19] 0b000 = no address-type protection |
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| 454 | * CS negation time [20] 0b1 |
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| 455 | * ACS [21-22] 0b00 = CS output at same time as address lines |
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| 456 | * Burst inhibit [23] 0b1 = bank does not support burst accesses |
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| 457 | * Cycle length [24-27] 0b0011/0b0100 = 3/4 clock cycle wait states |
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| 458 | * SETA [28] 0b0 = TA generated internally |
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| 459 | * Timing relaxed [29] 0b0 = not relaxed |
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| 460 | * Extended hold time [30] 0b0 = not extended |
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| 461 | * Reserved [31] 0b0 |
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| 462 | * |
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| 463 | * m8xx.memc[0]._or = 0xFF800930 (40 MHz) |
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| 464 | * m8xx.memc[0]._or = 0xFF800940 (50 MHz) |
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| 465 | * m8xx.memc[0]._br = 0xFE000001 |
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| 466 | */ |
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| 467 | #if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) |
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| 468 | m8xx.memc[0]._or = M8xx_MEMC_OR_8M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT | |
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| 469 | M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(4); |
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| 470 | #else |
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| 471 | m8xx.memc[0]._or = M8xx_MEMC_OR_8M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT | |
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| 472 | M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(3); |
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| 473 | #endif |
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| 474 | m8xx.memc[0]._br = M8xx_BR_BA(0xFE000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | |
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| 475 | M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; |
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| 476 | |
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| 477 | /* |
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| 478 | * CS1 : Local DRAM Memory at 0x00000000 |
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| 479 | * m8xx.memc[1]._or = 0xFFC00400; |
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| 480 | * m8xx.memc[1]._br = 0x00000081; |
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| 481 | */ |
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[168ba07] | 482 | #if ( defined(mbx860_001b) ) |
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| 483 | m8xx.memc[1]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) | |
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| 484 | M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); |
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| 485 | #elif ( defined(mbx860_002b) || \ |
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| 486 | defined(mbx860_003b) || \ |
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| 487 | defined(mbx821_001b) || \ |
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| 488 | defined(mbx821_002b) || \ |
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| 489 | defined(mbx821_003b) || \ |
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| 490 | defined(mbx860_001) || \ |
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| 491 | defined(mbx860_002) || \ |
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| 492 | defined(mbx860_003) || \ |
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| 493 | defined(mbx821_001) || \ |
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| 494 | defined(mbx821_002) || \ |
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| 495 | defined(mbx821_003) ) |
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| 496 | m8xx.memc[1]._or = M8xx_MEMC_OR_4M | M8xx_MEMC_OR_ATM(0) | |
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| 497 | M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); |
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| 498 | #elif ( defined(mbx860_004) || \ |
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| 499 | defined(mbx860_005) || \ |
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| 500 | defined(mbx860_004b) || \ |
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| 501 | defined(mbx860_005b) || \ |
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| 502 | defined(mbx860_006b) || \ |
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| 503 | defined(mbx821_004) || \ |
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| 504 | defined(mbx821_005) || \ |
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| 505 | defined(mbx821_004b) || \ |
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| 506 | defined(mbx821_005b) || \ |
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| 507 | defined(mbx821_006b) ) |
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| 508 | m8xx.memc[1]._or = M8xx_MEMC_OR_16M | M8xx_MEMC_OR_ATM(0) | |
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| 509 | M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); |
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| 510 | #else |
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| 511 | #error "MBX board not defined" |
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| 512 | #endif |
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[8ef3818] | 513 | m8xx.memc[1]._br = M8xx_BR_BA(0x00000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | |
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| 514 | M8xx_BR_MS_UPMA | M8xx_MEMC_BR_V; |
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| 515 | |
---|
| 516 | /* |
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| 517 | * CS2 : DIMM Memory - Bank #0, not present |
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| 518 | * m8xx.memc[2]._or = 0x00000400; |
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| 519 | * m8xx.memc[2]._br = 0x00000080; |
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| 520 | */ |
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| 521 | m8xx.memc[2]._or = M8xx_MEMC_OR_ATM(0) | |
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| 522 | M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); |
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| 523 | m8xx.memc[2]._br = M8xx_BR_AT(0) | M8xx_BR_PS32 | |
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| 524 | M8xx_BR_MS_UPMA; /* ! M8xx_MEMC_BR_V */ |
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| 525 | |
---|
| 526 | /* |
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| 527 | * CS3 : DIMM Memory - Bank #1, not present |
---|
| 528 | * m8xx.memc[3]._or = 0x00000400; |
---|
| 529 | * m8xx.memc[3]._br = 0x00000080; |
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| 530 | */ |
---|
| 531 | m8xx.memc[3]._or = M8xx_MEMC_OR_ATM(0) | |
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| 532 | M8xx_MEMC_OR_ACS_QRTR | M8xx_MEMC_OR_SCY(0); |
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| 533 | m8xx.memc[3]._br = M8xx_BR_AT(0) | M8xx_BR_PS32 | |
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| 534 | M8xx_BR_MS_UPMA; /* ! M8xx_MEMC_BR_V */ |
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| 535 | |
---|
| 536 | /* |
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| 537 | * CS4 : Battery-Backed SRAM at 0xFA000000 |
---|
| 538 | * m8xx.memc[4]._or = 0xFFE00920@ 40 MHz, 0xFFE00930 @ 50 MHz |
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| 539 | * m8xx.memc[4]._br = 0xFA000401; |
---|
| 540 | */ |
---|
| 541 | #if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) |
---|
| 542 | m8xx.memc[4]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT | |
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| 543 | M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(3); |
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| 544 | #else |
---|
| 545 | m8xx.memc[4]._or = M8xx_MEMC_OR_2M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT | |
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| 546 | M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(2); |
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| 547 | #endif |
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| 548 | m8xx.memc[4]._br = M8xx_BR_BA(0xFA000000) | M8xx_BR_AT(0) | M8xx_BR_PS8 | |
---|
| 549 | M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; |
---|
| 550 | |
---|
| 551 | /* |
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| 552 | * CS5 : PCI I/O and Memory at 0x80000000 |
---|
| 553 | * m8xx.memc[5]._or = 0xA0000108; |
---|
| 554 | * m8xx.memc[5]._br = 0x80000001; |
---|
| 555 | */ |
---|
| 556 | m8xx.memc[5]._or = 0xA0000000 | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_NORM | |
---|
| 557 | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(0) | M8xx_MEMC_OR_SETA; |
---|
| 558 | m8xx.memc[5]._br = M8xx_BR_BA(0x80000000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | |
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| 559 | M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; |
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| 560 | |
---|
| 561 | /* |
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| 562 | * CS6 : QSPAN Registers at 0xFA210000 |
---|
| 563 | * m8xx.memc[6]._or = 0xFFFF0108; |
---|
| 564 | * m8xx.memc[6]._br = 0xFA210001; |
---|
| 565 | */ |
---|
| 566 | m8xx.memc[6]._or = M8xx_MEMC_OR_64K | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_ACS_NORM | |
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| 567 | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(0) | M8xx_MEMC_OR_SETA; |
---|
| 568 | m8xx.memc[6]._br = M8xx_BR_BA(0xFA210000) | M8xx_BR_AT(0) | M8xx_BR_PS32 | |
---|
| 569 | M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; |
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| 570 | |
---|
| 571 | /* |
---|
| 572 | * CS7 : Socketed (8-bit) Flash at 0xFC000000 |
---|
| 573 | * m8xx.memc[7]._or = 0xFF800930 @ 40 MHz, 0xFF800940 @ 50 MHz |
---|
| 574 | * m8xx.memc[7]._br = 0xFC000401; |
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| 575 | */ |
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| 576 | #if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) |
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| 577 | m8xx.memc[7]._or = M8xx_MEMC_OR_8M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT | |
---|
| 578 | M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(4); |
---|
| 579 | #else |
---|
| 580 | m8xx.memc[7]._or = M8xx_MEMC_OR_8M | M8xx_MEMC_OR_ATM(0) | M8xx_MEMC_OR_CSNT | |
---|
| 581 | M8xx_MEMC_OR_ACS_NORM | M8xx_MEMC_OR_BI | M8xx_MEMC_OR_SCY(3); |
---|
| 582 | #endif |
---|
| 583 | m8xx.memc[7]._br = M8xx_BR_BA(0xFC000000) | M8xx_BR_AT(0) | M8xx_BR_PS8 | |
---|
| 584 | M8xx_BR_MS_GPCM | M8xx_MEMC_BR_V; |
---|
| 585 | } |
---|