1 | /* bspstart.c |
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2 | * |
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3 | * This set of routines starts the application. It includes application, |
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4 | * board, and monitor specific initialization and configuration. |
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5 | * The generic CPU dependent initialization has been performed |
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6 | * before this routine is invoked. |
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7 | * |
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8 | * COPYRIGHT (c) 1989-2007. |
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9 | * On-Line Applications Research Corporation (OAR). |
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10 | * |
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11 | * The license and distribution terms for this file may be |
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12 | * found in the file LICENSE in this distribution or at |
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13 | * http://www.rtems.com/license/LICENSE. |
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14 | * |
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15 | * Modifications for MBX860: |
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16 | * Copyright (c) 1999, National Research Council of Canada |
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17 | */ |
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18 | |
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19 | #include <bsp.h> |
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20 | #include <bsp/irq.h> |
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21 | #include <rtems/bspIo.h> |
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22 | #include <rtems/counter.h> |
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23 | #include <libcpu/cpuIdent.h> |
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24 | #include <libcpu/spr.h> |
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25 | #include <rtems/powerpc/powerpc.h> |
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26 | |
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27 | SPR_RW(SPRG1) |
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28 | |
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29 | int bsp_interrupt_initialize(void); |
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30 | |
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31 | /* |
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32 | * Driver configuration parameters |
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33 | */ |
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34 | uint32_t bsp_clicks_per_usec; |
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35 | uint32_t bsp_clock_speed; |
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36 | uint32_t bsp_serial_per_sec; /* Serial clocks per second */ |
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37 | bool bsp_serial_external_clock; |
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38 | bool bsp_serial_xon_xoff; |
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39 | bool bsp_serial_cts_rts; |
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40 | uint32_t bsp_serial_rate; |
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41 | uint32_t bsp_timer_average_overhead; /* Average overhead of timer in ticks */ |
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42 | uint32_t bsp_timer_least_valid; /* Least valid number from timer */ |
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43 | bool bsp_timer_internal_clock; /* TRUE, when timer runs with CPU clk */ |
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44 | |
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45 | extern char IntrStack_start []; |
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46 | extern char intrStack []; |
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47 | |
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48 | void BSP_panic(char *s) |
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49 | { |
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50 | printk("%s PANIC %s\n",_RTEMS_version, s); |
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51 | __asm__ __volatile ("sc"); |
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52 | } |
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53 | |
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54 | void _BSP_Fatal_error(unsigned int v) |
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55 | { |
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56 | printk("%s PANIC ERROR %x\n",_RTEMS_version, v); |
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57 | __asm__ __volatile ("sc"); |
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58 | } |
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59 | |
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60 | /* |
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61 | * bsp_start() |
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62 | * |
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63 | * Board-specific initialization code. Called from the generic boot_card() |
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64 | * function defined in rtems/c/src/lib/libbsp/shared/main.c. That function |
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65 | * does some of the board independent initialization. It is called from the |
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66 | * MBX8xx entry point _start() defined in |
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67 | * rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S |
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68 | * |
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69 | * _start() has set up a stack, has zeroed the .bss section, has turned off |
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70 | * interrupts, and placed the processor in the supervisor mode. boot_card() |
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71 | * has left the processor in that state when bsp_start() was called. |
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72 | * |
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73 | * RUNS WITH ADDRESS TRANSLATION AND CACHING TURNED OFF! |
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74 | * ASSUMES THAT THE VIRTUAL ADDRESSES WILL BE IDENTICAL TO THE PHYSICAL |
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75 | * ADDRESSES. Software-controlled address translation would be required |
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76 | * otherwise. |
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77 | * |
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78 | * Input parameters: NONE |
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79 | * |
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80 | * Output parameters: NONE |
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81 | * |
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82 | * Return values: NONE |
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83 | */ |
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84 | void bsp_start(void) |
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85 | { |
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86 | ppc_cpu_id_t myCpu; |
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87 | ppc_cpu_revision_t myCpuRevision; |
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88 | |
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89 | /* |
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90 | * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function |
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91 | * store the result in global variables so that it can be used latter... |
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92 | */ |
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93 | myCpu = get_ppc_cpu_type(); |
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94 | myCpuRevision = get_ppc_cpu_revision(); |
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95 | |
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96 | mmu_init(); |
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97 | |
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98 | /* |
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99 | * Enable instruction and data caches. Do not force writethrough mode. |
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100 | */ |
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101 | #if NVRAM_CONFIGURE == 1 |
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102 | if ( nvram->cache_mode & 0x02 ) |
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103 | rtems_cache_enable_instruction(); |
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104 | if ( nvram->cache_mode & 0x01 ) |
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105 | rtems_cache_enable_data(); |
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106 | #else |
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107 | #if BSP_INSTRUCTION_CACHE_ENABLED |
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108 | rtems_cache_enable_instruction(); |
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109 | #endif |
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110 | #if BSP_DATA_CACHE_ENABLED |
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111 | rtems_cache_enable_data(); |
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112 | #endif |
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113 | #endif |
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114 | |
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115 | /* Initialize exception handler */ |
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116 | ppc_exc_initialize( |
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117 | PPC_INTERRUPT_DISABLE_MASK_DEFAULT, |
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118 | (uintptr_t) IntrStack_start, |
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119 | (uintptr_t) intrStack - (uintptr_t) IntrStack_start |
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120 | ); |
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121 | |
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122 | /* Initalize interrupt support */ |
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123 | bsp_interrupt_initialize(); |
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124 | |
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125 | /* |
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126 | * initialize the device driver parameters |
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127 | */ |
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128 | |
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129 | #if ( defined(mbx860_001b) || \ |
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130 | defined(mbx860_002b) || \ |
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131 | defined(mbx860_003b) || \ |
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132 | defined(mbx860_003b) || \ |
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133 | defined(mbx860_004b) || \ |
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134 | defined(mbx860_005b) || \ |
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135 | defined(mbx860_006b) || \ |
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136 | defined(mbx821_001b) || \ |
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137 | defined(mbx821_002b) || \ |
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138 | defined(mbx821_003b) || \ |
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139 | defined(mbx821_004b) || \ |
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140 | defined(mbx821_005b) || \ |
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141 | defined(mbx821_006b)) |
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142 | bsp_clicks_per_usec = 0; /* for 32768Hz extclk */ |
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143 | #else |
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144 | bsp_clicks_per_usec = 1; /* for 4MHz extclk */ |
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145 | #endif |
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146 | rtems_counter_initialize_converter(bsp_clicks_per_usec * 1000000); |
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147 | |
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148 | bsp_serial_per_sec = 10000000; |
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149 | bsp_serial_external_clock = true; |
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150 | bsp_serial_xon_xoff = false; |
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151 | bsp_serial_cts_rts = true; |
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152 | bsp_serial_rate = 9600; |
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153 | #if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) |
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154 | bsp_clock_speed = 50000000; |
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155 | bsp_timer_average_overhead = 3; |
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156 | bsp_timer_least_valid = 3; |
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157 | #else |
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158 | bsp_clock_speed = 40000000; |
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159 | bsp_timer_average_overhead = 3; |
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160 | bsp_timer_least_valid = 3; |
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161 | #endif |
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162 | |
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163 | m8xx.scc2.sccm=0; |
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164 | m8xx.scc2p.rbase=0; |
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165 | m8xx.scc2p.tbase=0; |
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166 | m8xx_cp_execute_cmd( M8xx_CR_OP_STOP_TX | M8xx_CR_CHAN_SCC2 ); |
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167 | |
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168 | #ifdef SHOW_MORE_INIT_SETTINGS |
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169 | printk("Exit from bspstart\n"); |
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170 | #endif |
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171 | |
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172 | } |
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