1 | /* irq.h |
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2 | * |
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3 | * This include file describe the data structure and the functions implemented |
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4 | * by rtems to write interrupt handlers. |
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5 | * |
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6 | * CopyRight (C) 1999 valette@crf.canon.fr |
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7 | * |
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8 | * This code is heavilly inspired by the public specification of STREAM V2 |
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9 | * that can be found at : |
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10 | * |
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11 | * <http://www.chorus.com/Documentation/index.html> by following |
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12 | * the STREAM API Specification Document link. |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.com/license/LICENSE. |
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17 | * |
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18 | * $Id$ |
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19 | */ |
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20 | |
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21 | #ifndef LIBBSP_POWERPC_MBX8XX_IRQ_IRQ_H |
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22 | #define LIBBSP_POWERPC_MBX8XX_IRQ_IRQ_H |
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23 | |
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24 | #include <rtems/irq.h> |
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25 | |
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26 | #ifndef ASM |
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27 | |
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28 | #ifdef __cplusplus |
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29 | extern "C" { |
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30 | #endif |
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31 | |
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32 | extern volatile unsigned int ppc_cached_irq_mask; |
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33 | |
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34 | /* |
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35 | * Symblolic IRQ names and related definitions. |
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36 | */ |
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37 | |
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38 | /* |
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39 | * SIU IRQ handler related definitions |
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40 | */ |
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41 | #define BSP_SIU_IRQ_NUMBER 16 /* 16 reserved but in the future... */ |
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42 | #define BSP_SIU_IRQ_LOWEST_OFFSET 0 |
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43 | #define BSP_SIU_IRQ_MAX_OFFSET (BSP_SIU_IRQ_LOWEST_OFFSET + BSP_SIU_IRQ_NUMBER - 1) |
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44 | /* |
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45 | * CPM IRQ handlers related definitions |
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46 | * CAUTION : BSP_CPM_IRQ_LOWEST_OFFSET should be equal to OPENPIC_VEC_SOURCE |
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47 | */ |
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48 | #define BSP_CPM_IRQ_NUMBER 32 |
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49 | #define BSP_CPM_IRQ_LOWEST_OFFSET (BSP_SIU_IRQ_NUMBER + BSP_SIU_IRQ_LOWEST_OFFSET) |
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50 | #define BSP_CPM_IRQ_MAX_OFFSET (BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER - 1) |
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51 | /* |
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52 | * PowerPc exceptions handled as interrupt where a rtems managed interrupt |
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53 | * handler might be connected |
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54 | */ |
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55 | #define BSP_PROCESSOR_IRQ_NUMBER 1 |
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56 | #define BSP_PROCESSOR_IRQ_LOWEST_OFFSET (BSP_CPM_IRQ_MAX_OFFSET + 1) |
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57 | #define BSP_PROCESSOR_IRQ_MAX_OFFSET (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) |
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58 | /* |
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59 | * Summary |
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60 | */ |
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61 | #define BSP_IRQ_NUMBER (BSP_PROCESSOR_IRQ_MAX_OFFSET + 1) |
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62 | #define BSP_LOWEST_OFFSET (BSP_SIU_IRQ_LOWEST_OFFSET) |
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63 | #define BSP_MAX_OFFSET (BSP_PROCESSOR_IRQ_MAX_OFFSET) |
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64 | /* |
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65 | * Some SIU IRQ symbolic name definition. Please note that |
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66 | * INT IRQ are defined but a single one will be used to |
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67 | * redirect all CPM interrupt. |
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68 | */ |
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69 | #define BSP_SIU_EXT_IRQ_0 0 |
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70 | #define BSP_SIU_INT_IRQ_0 1 |
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71 | |
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72 | #define BSP_SIU_EXT_IRQ_1 2 |
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73 | #define BSP_SIU_INT_IRQ_1 3 |
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74 | |
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75 | #define BSP_SIU_EXT_IRQ_2 4 |
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76 | #define BSP_SIU_INT_IRQ_2 5 |
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77 | |
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78 | #define BSP_SIU_EXT_IRQ_3 6 |
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79 | #define BSP_SIU_INT_IRQ_3 7 |
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80 | |
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81 | #define BSP_SIU_EXT_IRQ_4 8 |
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82 | #define BSP_SIU_INT_IRQ_4 9 |
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83 | |
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84 | #define BSP_SIU_EXT_IRQ_5 10 |
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85 | #define BSP_SIU_INT_IRQ_5 11 |
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86 | |
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87 | #define BSP_SIU_EXT_IRQ_6 12 |
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88 | #define BSP_SIU_INT_IRQ_6 13 |
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89 | |
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90 | #define BSP_SIU_EXT_IRQ_7 14 |
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91 | #define BSP_SIU_INT_IRQ_7 15 |
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92 | /* |
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93 | * Symbolic name for CPM interrupt on SIU Internal level 2 |
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94 | */ |
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95 | #define BSP_CPM_INTERRUPT BSP_SIU_INT_IRQ_2 |
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96 | #define BSP_PERIODIC_TIMER BSP_SIU_INT_IRQ_6 |
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97 | #define BSP_FAST_ETHERNET_CTRL BSP_SIU_INT_IRQ_3 |
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98 | /* |
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99 | * Some CPM IRQ symbolic name definition |
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100 | */ |
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101 | #define BSP_CPM_IRQ_ERROR BSP_CPM_IRQ_LOWEST_OFFSET |
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102 | #define BSP_CPM_IRQ_PARALLEL_IO_PC4 (BSP_CPM_IRQ_LOWEST_OFFSET + 1) |
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103 | #define BSP_CPM_IRQ_PARALLEL_IO_PC5 (BSP_CPM_IRQ_LOWEST_OFFSET + 2) |
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104 | #define BSP_CPM_IRQ_SMC2_OR_PIP (BSP_CPM_IRQ_LOWEST_OFFSET + 3) |
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105 | #define BSP_CPM_IRQ_SMC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 4) |
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106 | #define BSP_CPM_IRQ_SPI (BSP_CPM_IRQ_LOWEST_OFFSET + 5) |
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107 | #define BSP_CPM_IRQ_PARALLEL_IO_PC6 (BSP_CPM_IRQ_LOWEST_OFFSET + 6) |
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108 | #define BSP_CPM_IRQ_TIMER_4 (BSP_CPM_IRQ_LOWEST_OFFSET + 7) |
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109 | |
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110 | #define BSP_CPM_IRQ_PARALLEL_IO_PC7 (BSP_CPM_IRQ_LOWEST_OFFSET + 9) |
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111 | #define BSP_CPM_IRQ_PARALLEL_IO_PC8 (BSP_CPM_IRQ_LOWEST_OFFSET + 10) |
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112 | #define BSP_CPM_IRQ_PARALLEL_IO_PC9 (BSP_CPM_IRQ_LOWEST_OFFSET + 11) |
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113 | #define BSP_CPM_IRQ_TIMER_3 (BSP_CPM_IRQ_LOWEST_OFFSET + 12) |
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114 | |
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115 | #define BSP_CPM_IRQ_PARALLEL_IO_PC10 (BSP_CPM_IRQ_LOWEST_OFFSET + 14) |
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116 | #define BSP_CPM_IRQ_PARALLEL_IO_PC11 (BSP_CPM_IRQ_LOWEST_OFFSET + 15) |
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117 | #define BSP_CPM_I2C (BSP_CPM_IRQ_LOWEST_OFFSET + 16) |
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118 | #define BSP_CPM_RISC_TIMER_TABLE (BSP_CPM_IRQ_LOWEST_OFFSET + 17) |
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119 | #define BSP_CPM_IRQ_TIMER_2 (BSP_CPM_IRQ_LOWEST_OFFSET + 18) |
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120 | |
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121 | #define BSP_CPM_IDMA2 (BSP_CPM_IRQ_LOWEST_OFFSET + 20) |
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122 | #define BSP_CPM_IDMA1 (BSP_CPM_IRQ_LOWEST_OFFSET + 21) |
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123 | #define BSP_CPM_SDMA_CHANNEL_BUS_ERR (BSP_CPM_IRQ_LOWEST_OFFSET + 22) |
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124 | #define BSP_CPM_IRQ_PARALLEL_IO_PC12 (BSP_CPM_IRQ_LOWEST_OFFSET + 23) |
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125 | #define BSP_CPM_IRQ_PARALLEL_IO_PC13 (BSP_CPM_IRQ_LOWEST_OFFSET + 24) |
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126 | #define BSP_CPM_IRQ_TIMER_1 (BSP_CPM_IRQ_LOWEST_OFFSET + 25) |
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127 | #define BSP_CPM_IRQ_PARALLEL_IO_PC14 (BSP_CPM_IRQ_LOWEST_OFFSET + 26) |
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128 | #define BSP_CPM_IRQ_SCC4 (BSP_CPM_IRQ_LOWEST_OFFSET + 27) |
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129 | #define BSP_CPM_IRQ_SCC3 (BSP_CPM_IRQ_LOWEST_OFFSET + 28) |
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130 | #define BSP_CPM_IRQ_SCC2 (BSP_CPM_IRQ_LOWEST_OFFSET + 29) |
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131 | #define BSP_CPM_IRQ_SCC1 (BSP_CPM_IRQ_LOWEST_OFFSET + 30) |
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132 | #define BSP_CPM_IRQ_PARALLEL_IO_PC15 (BSP_CPM_IRQ_LOWEST_OFFSET + 31) |
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133 | /* |
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134 | * Some Processor exception handled as rtems IRQ symbolic name definition |
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135 | */ |
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136 | #define BSP_DECREMENTER BSP_PROCESSOR_IRQ_LOWEST_OFFSET |
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137 | |
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138 | |
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139 | #define CPM_INTERRUPT |
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140 | |
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141 | /*-------------------------------------------------------------------------+ |
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142 | | Function Prototypes. |
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143 | +--------------------------------------------------------------------------*/ |
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144 | /* |
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145 | * ------------------------ PPC SIU Mngt Routines ------- |
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146 | */ |
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147 | |
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148 | /* |
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149 | * function to disable a particular irq at 8259 level. After calling |
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150 | * this function, even if the device asserts the interrupt line it will |
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151 | * not be propagated further to the processor |
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152 | */ |
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153 | int BSP_irq_disable_at_siu (const rtems_irq_number irqLine); |
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154 | /* |
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155 | * function to enable a particular irq at 8259 level. After calling |
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156 | * this function, if the device asserts the interrupt line it will |
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157 | * be propagated further to the processor |
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158 | */ |
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159 | int BSP_irq_enable_at_siu (const rtems_irq_number irqLine); |
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160 | /* |
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161 | * function to acknoledge a particular irq at 8259 level. After calling |
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162 | * this function, if a device asserts an enabled interrupt line it will |
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163 | * be propagated further to the processor. Mainly usefull for people |
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164 | * writting raw handlers as this is automagically done for rtems managed |
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165 | * handlers. |
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166 | */ |
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167 | int BSP_irq_ack_at_siu (const rtems_irq_number irqLine); |
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168 | /* |
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169 | * function to check if a particular irq is enabled at 8259 level. After calling |
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170 | */ |
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171 | int BSP_irq_enabled_at_siu (const rtems_irq_number irqLine); |
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172 | |
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173 | extern void BSP_rtems_irq_mng_init(unsigned cpuId); |
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174 | |
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175 | #ifdef __cplusplus |
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176 | } |
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177 | #endif |
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178 | |
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179 | #endif |
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180 | |
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181 | #endif |
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