1 | /* |
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2 | * |
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3 | * This file contains the implementation of the function described in irq.h |
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4 | * |
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5 | * Copyright (c) 2009 embedded brains GmbH. |
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6 | * |
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7 | * Copyright (C) 1998, 1999 valette@crf.canon.fr |
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8 | * |
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9 | * The license and distribution terms for this file may be |
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10 | * found in the file LICENSE in this distribution or at |
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11 | * http://www.rtems.com/license/LICENSE. |
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12 | * |
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13 | * $Id$ |
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14 | */ |
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15 | |
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16 | #include <rtems/system.h> |
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17 | #include <bsp.h> |
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18 | #include <bsp/irq.h> |
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19 | #include <bsp/irq-generic.h> |
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20 | #include <bsp/vectors.h> |
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21 | #include <bsp/8xx_immap.h> |
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22 | #include <bsp/mbx.h> |
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23 | #include <bsp/commproc.h> |
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24 | |
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25 | volatile unsigned int ppc_cached_irq_mask; |
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26 | |
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27 | /* |
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28 | * Check if symbolic IRQ name is an SIU IRQ |
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29 | */ |
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30 | static inline int is_siu_irq(const rtems_irq_number irqLine) |
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31 | { |
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32 | return (((int) irqLine <= BSP_SIU_IRQ_MAX_OFFSET) & |
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33 | ((int) irqLine >= BSP_SIU_IRQ_LOWEST_OFFSET) |
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34 | ); |
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35 | } |
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36 | |
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37 | /* |
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38 | * Check if symbolic IRQ name is an CPM IRQ |
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39 | */ |
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40 | static inline int is_cpm_irq(const rtems_irq_number irqLine) |
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41 | { |
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42 | return (((int) irqLine <= BSP_CPM_IRQ_MAX_OFFSET) & |
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43 | ((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET) |
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44 | ); |
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45 | } |
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46 | |
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47 | /* |
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48 | * masks used to mask off the interrupts. For exmaple, for ILVL2, the |
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49 | * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 |
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50 | * and ILVL7. |
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51 | * |
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52 | */ |
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53 | const static unsigned int SIU_IvectMask[BSP_SIU_IRQ_NUMBER] = |
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54 | { |
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55 | /* IRQ0 ILVL0 IRQ1 ILVL1 */ |
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56 | 0x00000000, 0x80000000, 0xC0000000, 0xE0000000, |
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57 | |
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58 | /* IRQ2 ILVL2 IRQ3 ILVL3 */ |
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59 | 0xF0000000, 0xF8000000, 0xFC000000, 0xFE000000, |
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60 | |
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61 | /* IRQ4 ILVL4 IRQ5 ILVL5 */ |
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62 | 0xFF000000, 0xFF800000, 0xFFC00000, 0xFFE00000, |
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63 | |
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64 | /* IRQ6 ILVL6 IRQ7 ILVL7 */ |
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65 | 0xFFF00000, 0xFFF80000, 0xFFFC0000, 0xFFFE0000 |
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66 | }; |
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67 | |
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68 | int BSP_irq_enable_at_cpm(const rtems_irq_number irqLine) |
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69 | { |
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70 | int cpm_irq_index; |
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71 | |
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72 | if (!is_cpm_irq(irqLine)) |
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73 | return 1; |
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74 | |
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75 | cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); |
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76 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr |= (1 << cpm_irq_index); |
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77 | |
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78 | return 0; |
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79 | } |
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80 | |
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81 | int BSP_irq_disable_at_cpm(const rtems_irq_number irqLine) |
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82 | { |
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83 | int cpm_irq_index; |
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84 | |
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85 | if (!is_cpm_irq(irqLine)) |
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86 | return 1; |
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87 | |
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88 | cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); |
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89 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << cpm_irq_index); |
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90 | |
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91 | return 0; |
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92 | } |
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93 | |
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94 | int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine) |
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95 | { |
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96 | int cpm_irq_index; |
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97 | |
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98 | if (!is_cpm_irq(irqLine)) |
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99 | return 0; |
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100 | |
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101 | cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); |
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102 | return (((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr & (1 << cpm_irq_index)); |
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103 | } |
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104 | |
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105 | int BSP_irq_enable_at_siu(const rtems_irq_number irqLine) |
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106 | { |
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107 | int siu_irq_index; |
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108 | |
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109 | if (!is_siu_irq(irqLine)) |
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110 | return 1; |
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111 | |
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112 | siu_irq_index = ((int) (irqLine) - BSP_SIU_IRQ_LOWEST_OFFSET); |
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113 | ppc_cached_irq_mask |= (1 << (31-siu_irq_index)); |
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114 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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115 | |
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116 | return 0; |
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117 | } |
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118 | |
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119 | int BSP_irq_disable_at_siu(const rtems_irq_number irqLine) |
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120 | { |
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121 | int siu_irq_index; |
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122 | |
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123 | if (!is_siu_irq(irqLine)) |
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124 | return 1; |
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125 | |
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126 | siu_irq_index = ((int) (irqLine) - BSP_SIU_IRQ_LOWEST_OFFSET); |
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127 | ppc_cached_irq_mask &= ~(1 << (31-siu_irq_index)); |
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128 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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129 | |
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130 | return 0; |
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131 | } |
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132 | |
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133 | int BSP_irq_enabled_at_siu (const rtems_irq_number irqLine) |
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134 | { |
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135 | int siu_irq_index; |
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136 | |
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137 | if (!is_siu_irq(irqLine)) |
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138 | return 0; |
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139 | |
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140 | siu_irq_index = ((int) (irqLine) - BSP_SIU_IRQ_LOWEST_OFFSET); |
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141 | return ppc_cached_irq_mask & (1 << (31-siu_irq_index)); |
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142 | } |
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143 | |
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144 | #ifdef DISPATCH_HANDLER_STAT |
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145 | volatile unsigned int maxLoop = 0; |
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146 | #endif |
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147 | |
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148 | /* |
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149 | * High level IRQ handler called from shared_raw_irq_code_entry |
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150 | */ |
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151 | int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum) |
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152 | { |
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153 | register unsigned int irq; |
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154 | register unsigned cpmIntr; /* boolean */ |
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155 | register unsigned oldMask; /* old siu pic masks */ |
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156 | register unsigned msr; |
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157 | register unsigned new_msr; |
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158 | #ifdef DISPATCH_HANDLER_STAT |
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159 | unsigned loopCounter; |
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160 | #endif |
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161 | /* |
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162 | * Handle decrementer interrupt |
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163 | */ |
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164 | if (excNum == ASM_DEC_VECTOR) { |
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165 | _CPU_MSR_GET(msr); |
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166 | new_msr = msr | MSR_EE; |
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167 | _CPU_MSR_SET(new_msr); |
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168 | |
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169 | bsp_interrupt_handler_dispatch(BSP_DECREMENTER); |
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170 | |
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171 | _CPU_MSR_SET(msr); |
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172 | return 0; |
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173 | } |
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174 | /* |
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175 | * Handle external interrupt generated by SIU on PPC core |
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176 | */ |
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177 | #ifdef DISPATCH_HANDLER_STAT |
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178 | loopCounter = 0; |
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179 | #endif |
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180 | while (1) { |
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181 | if ((ppc_cached_irq_mask & ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend) == 0) { |
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182 | #ifdef DISPATCH_HANDLER_STAT |
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183 | if (loopCounter > maxLoop) maxLoop = loopCounter; |
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184 | #endif |
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185 | break; |
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186 | } |
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187 | irq = (((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec >> 26); |
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188 | cpmIntr = (irq == BSP_CPM_INTERRUPT); |
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189 | /* |
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190 | * Disable the interrupt of the same and lower priority. |
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191 | */ |
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192 | oldMask = ppc_cached_irq_mask; |
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193 | ppc_cached_irq_mask = oldMask & SIU_IvectMask[irq]; |
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194 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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195 | /* |
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196 | * Acknowledge current interrupt. This has no effect on internal level interrupt. |
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197 | */ |
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198 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend = (1 << (31 - irq)); |
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199 | |
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200 | if (cpmIntr) { |
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201 | /* |
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202 | * We will reenable the SIU CPM interrupt to allow nesting of CPM interrupt. |
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203 | * We must before acknowledege the current irq at CPM level to avoid trigerring |
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204 | * the interrupt again. |
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205 | */ |
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206 | /* |
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207 | * Acknowledge and get the vector. |
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208 | */ |
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209 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr = 1; |
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210 | irq = (((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr >> 11); |
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211 | /* |
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212 | * transform IRQ to normalized irq table index. |
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213 | */ |
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214 | irq += BSP_CPM_IRQ_LOWEST_OFFSET; |
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215 | /* |
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216 | * Unmask CPM interrupt at SIU level |
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217 | */ |
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218 | ppc_cached_irq_mask |= (1 << (31 - BSP_CPM_INTERRUPT)); |
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219 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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220 | } |
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221 | /* |
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222 | * make sure, that the masking operations in |
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223 | * ICTL and MSR are executed in order |
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224 | */ |
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225 | __asm__ volatile("sync":::"memory"); |
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226 | |
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227 | _CPU_MSR_GET(msr); |
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228 | new_msr = msr | MSR_EE; |
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229 | _CPU_MSR_SET(new_msr); |
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230 | |
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231 | bsp_interrupt_handler_dispatch(irq); |
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232 | |
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233 | _CPU_MSR_SET(msr); |
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234 | |
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235 | /* |
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236 | * make sure, that the masking operations in |
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237 | * ICTL and MSR are executed in order |
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238 | */ |
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239 | __asm__ volatile("sync":::"memory"); |
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240 | |
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241 | if (cpmIntr) { |
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242 | irq -= BSP_CPM_IRQ_LOWEST_OFFSET; |
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243 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr = (1 << irq); |
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244 | } |
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245 | ppc_cached_irq_mask = oldMask; |
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246 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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247 | #ifdef DISPATCH_HANDLER_STAT |
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248 | ++ loopCounter; |
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249 | #endif |
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250 | } |
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251 | return 0; |
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252 | } |
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253 | |
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254 | void BSP_SIU_irq_init(void) |
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255 | { |
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256 | /* |
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257 | * In theory we should initialize two registers at least : |
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258 | * SIMASK, SIEL. SIMASK is reset at 0 value meaning no interrupt. But |
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259 | * we should take care that a monitor may have restoreed to another value. |
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260 | * If someone find a reasonnable value for SIEL, AND THE NEED TO CHANGE IT |
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261 | * please feel free to add it here. |
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262 | */ |
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263 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = 0; |
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264 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend = 0xffff0000; |
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265 | ppc_cached_irq_mask = 0; |
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266 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel = ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel; |
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267 | } |
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268 | |
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269 | /* |
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270 | * Initialize CPM interrupt management |
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271 | */ |
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272 | void |
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273 | BSP_CPM_irq_init(void) |
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274 | { |
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275 | /* |
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276 | * Initialize the CPM interrupt controller. |
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277 | */ |
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278 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr = |
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279 | #ifdef mpc860 |
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280 | (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) | |
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281 | #else |
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282 | (CICR_SCB_SCC2 | CICR_SCA_SCC1) | |
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283 | #endif |
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284 | ((BSP_CPM_INTERRUPT/2) << 13) | CICR_HP_MASK; |
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285 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr = 0; |
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286 | |
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287 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN; |
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288 | } |
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289 | |
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290 | rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqnum) |
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291 | { |
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292 | if (is_cpm_irq(irqnum)) { |
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293 | /* |
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294 | * Enable interrupt at PIC level |
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295 | */ |
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296 | BSP_irq_enable_at_cpm (irqnum); |
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297 | } |
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298 | |
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299 | if (is_siu_irq(irqnum)) { |
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300 | /* |
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301 | * Enable interrupt at SIU level |
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302 | */ |
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303 | BSP_irq_enable_at_siu (irqnum); |
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304 | } |
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305 | |
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306 | return RTEMS_SUCCESSFUL; |
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307 | } |
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308 | |
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309 | rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqnum) |
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310 | { |
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311 | if (is_cpm_irq(irqnum)) { |
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312 | /* |
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313 | * disable interrupt at PIC level |
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314 | */ |
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315 | BSP_irq_disable_at_cpm (irqnum); |
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316 | } |
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317 | if (is_siu_irq(irqnum)) { |
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318 | /* |
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319 | * disable interrupt at OPENPIC level |
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320 | */ |
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321 | BSP_irq_disable_at_siu (irqnum); |
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322 | } |
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323 | |
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324 | return RTEMS_SUCCESSFUL; |
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325 | } |
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326 | |
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327 | rtems_status_code bsp_interrupt_facility_initialize() |
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328 | { |
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329 | /* Install exception handler */ |
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330 | if (ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler)) { |
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331 | return RTEMS_IO_ERROR; |
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332 | } |
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333 | if (ppc_exc_set_handler( ASM_DEC_VECTOR, C_dispatch_irq_handler)) { |
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334 | return RTEMS_IO_ERROR; |
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335 | } |
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336 | |
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337 | /* Initialize the interrupt controller */ |
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338 | BSP_SIU_irq_init(); |
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339 | BSP_CPM_irq_init(); |
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340 | |
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341 | /* |
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342 | * Must enable CPM interrupt on SIU. CPM on SIU Interrupt level has already been |
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343 | * set up in BSP_CPM_irq_init. |
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344 | */ |
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345 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN; |
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346 | BSP_irq_enable_at_siu (BSP_CPM_INTERRUPT); |
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347 | |
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348 | return RTEMS_SUCCESSFUL; |
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349 | } |
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350 | |
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351 | void bsp_interrupt_handler_default( rtems_vector_number vector) |
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352 | { |
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353 | printk( "Spurious interrupt: 0x%08x\n", vector); |
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354 | } |
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