[35bb69b] | 1 | /* |
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| 2 | * |
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| 3 | * This file contains the implementation of the function described in irq.h |
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| 4 | * |
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| 5 | * Copyright (C) 1998, 1999 valette@crf.canon.fr |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in found in the file LICENSE in this distribution or at |
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[1e7cbc5] | 9 | * http://www.rtems.com/license/LICENSE. |
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[35bb69b] | 10 | * |
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| 11 | * $Id$ |
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| 12 | */ |
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[6128a4a] | 13 | |
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[8038731] | 14 | #include <rtems/system.h> |
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[35bb69b] | 15 | #include <bsp.h> |
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| 16 | #include <bsp/irq.h> |
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| 17 | #include <rtems/score/thread.h> |
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| 18 | #include <rtems/score/apiext.h> |
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| 19 | #include <libcpu/raw_exception.h> |
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| 20 | #include <bsp/vectors.h> |
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| 21 | #include <bsp/8xx_immap.h> |
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| 22 | #include <bsp/mbx.h> |
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| 23 | #include <bsp/commproc.h> |
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| 24 | |
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| 25 | /* |
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| 26 | * default handler connected on each irq after bsp initialization |
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| 27 | */ |
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| 28 | static rtems_irq_connect_data default_rtems_entry; |
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| 29 | |
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| 30 | /* |
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| 31 | * location used to store initial tables used for interrupt |
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| 32 | * management. |
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| 33 | */ |
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| 34 | static rtems_irq_global_settings* internal_config; |
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| 35 | static rtems_irq_connect_data* rtems_hdl_tbl; |
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| 36 | |
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| 37 | /* |
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| 38 | * Check if symbolic IRQ name is an SIU IRQ |
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| 39 | */ |
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[adc53ec9] | 40 | static inline int is_siu_irq(const rtems_irq_number irqLine) |
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[35bb69b] | 41 | { |
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| 42 | return (((int) irqLine <= BSP_SIU_IRQ_MAX_OFFSET) & |
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| 43 | ((int) irqLine >= BSP_SIU_IRQ_LOWEST_OFFSET) |
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| 44 | ); |
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| 45 | } |
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| 46 | |
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| 47 | /* |
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| 48 | * Check if symbolic IRQ name is an CPM IRQ |
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| 49 | */ |
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[adc53ec9] | 50 | static inline int is_cpm_irq(const rtems_irq_number irqLine) |
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[35bb69b] | 51 | { |
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| 52 | return (((int) irqLine <= BSP_CPM_IRQ_MAX_OFFSET) & |
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| 53 | ((int) irqLine >= BSP_CPM_IRQ_LOWEST_OFFSET) |
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| 54 | ); |
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| 55 | } |
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| 56 | |
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| 57 | /* |
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| 58 | * Check if symbolic IRQ name is a Processor IRQ |
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| 59 | */ |
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[adc53ec9] | 60 | static inline int is_processor_irq(const rtems_irq_number irqLine) |
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[35bb69b] | 61 | { |
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| 62 | return (((int) irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) & |
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| 63 | ((int) irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET) |
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| 64 | ); |
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| 65 | } |
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| 66 | |
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| 67 | /* |
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[6128a4a] | 68 | * masks used to mask off the interrupts. For exmaple, for ILVL2, the |
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| 69 | * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 |
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| 70 | * and ILVL7. |
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[35bb69b] | 71 | * |
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| 72 | */ |
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| 73 | const static unsigned int SIU_IvectMask[BSP_SIU_IRQ_NUMBER] = |
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| 74 | { |
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| 75 | /* IRQ0 ILVL0 IRQ1 ILVL1 */ |
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| 76 | 0x00000000, 0x80000000, 0xC0000000, 0xE0000000, |
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| 77 | |
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| 78 | /* IRQ2 ILVL2 IRQ3 ILVL3 */ |
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| 79 | 0xF0000000, 0xF8000000, 0xFC000000, 0xFE000000, |
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| 80 | |
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| 81 | /* IRQ4 ILVL4 IRQ5 ILVL5 */ |
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| 82 | 0xFF000000, 0xFF800000, 0xFFC00000, 0xFFE00000, |
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| 83 | |
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| 84 | /* IRQ6 ILVL6 IRQ7 ILVL7 */ |
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| 85 | 0xFFF00000, 0xFFF80000, 0xFFFC0000, 0xFFFE0000 |
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| 86 | }; |
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| 87 | |
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| 88 | /* |
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| 89 | * ------------------------ RTEMS Irq helper functions ---------------- |
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| 90 | */ |
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| 91 | |
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| 92 | /* |
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| 93 | * Caution : this function assumes the variable "internal_config" |
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| 94 | * is already set and that the tables it contains are still valid |
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| 95 | * and accessible. |
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| 96 | */ |
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[cc981e1] | 97 | static void compute_SIU_IvectMask_from_prio (void) |
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[35bb69b] | 98 | { |
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| 99 | /* |
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| 100 | * In theory this is feasible. No time to code it yet. See i386/shared/irq.c |
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| 101 | * for an example based on 8259 controller mask. The actual masks defined |
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| 102 | * correspond to the priorities defined for the SIU in irq_init.c. |
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| 103 | */ |
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| 104 | } |
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| 105 | |
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| 106 | /* |
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| 107 | * This function check that the value given for the irq line |
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| 108 | * is valid. |
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| 109 | */ |
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| 110 | |
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| 111 | static int isValidInterrupt(int irq) |
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| 112 | { |
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| 113 | if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET) || (irq == BSP_CPM_INTERRUPT) ) |
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| 114 | return 0; |
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| 115 | return 1; |
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| 116 | } |
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| 117 | |
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[adc53ec9] | 118 | int BSP_irq_enable_at_cpm(const rtems_irq_number irqLine) |
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[35bb69b] | 119 | { |
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| 120 | int cpm_irq_index; |
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| 121 | |
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| 122 | if (!is_cpm_irq(irqLine)) |
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| 123 | return 1; |
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| 124 | |
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| 125 | cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); |
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| 126 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr |= (1 << cpm_irq_index); |
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| 127 | |
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| 128 | return 0; |
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| 129 | } |
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| 130 | |
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[adc53ec9] | 131 | int BSP_irq_disable_at_cpm(const rtems_irq_number irqLine) |
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[35bb69b] | 132 | { |
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| 133 | int cpm_irq_index; |
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[6128a4a] | 134 | |
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[35bb69b] | 135 | if (!is_cpm_irq(irqLine)) |
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| 136 | return 1; |
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[6128a4a] | 137 | |
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[35bb69b] | 138 | cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); |
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| 139 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr &= ~(1 << cpm_irq_index); |
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| 140 | |
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| 141 | return 0; |
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| 142 | } |
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| 143 | |
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[adc53ec9] | 144 | int BSP_irq_enabled_at_cpm(const rtems_irq_number irqLine) |
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[35bb69b] | 145 | { |
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| 146 | int cpm_irq_index; |
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[6128a4a] | 147 | |
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[35bb69b] | 148 | if (!is_cpm_irq(irqLine)) |
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| 149 | return 0; |
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[6128a4a] | 150 | |
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[35bb69b] | 151 | cpm_irq_index = ((int) (irqLine) - BSP_CPM_IRQ_LOWEST_OFFSET); |
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| 152 | return (((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr & (1 << cpm_irq_index)); |
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| 153 | } |
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| 154 | |
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[adc53ec9] | 155 | int BSP_irq_enable_at_siu(const rtems_irq_number irqLine) |
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[35bb69b] | 156 | { |
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| 157 | int siu_irq_index; |
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[6128a4a] | 158 | |
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[35bb69b] | 159 | if (!is_siu_irq(irqLine)) |
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| 160 | return 1; |
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| 161 | |
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| 162 | siu_irq_index = ((int) (irqLine) - BSP_SIU_IRQ_LOWEST_OFFSET); |
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| 163 | ppc_cached_irq_mask |= (1 << (31-siu_irq_index)); |
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| 164 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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| 165 | |
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| 166 | return 0; |
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| 167 | } |
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| 168 | |
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[adc53ec9] | 169 | int BSP_irq_disable_at_siu(const rtems_irq_number irqLine) |
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[35bb69b] | 170 | { |
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| 171 | int siu_irq_index; |
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| 172 | |
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| 173 | if (!is_siu_irq(irqLine)) |
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| 174 | return 1; |
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[6128a4a] | 175 | |
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[35bb69b] | 176 | siu_irq_index = ((int) (irqLine) - BSP_SIU_IRQ_LOWEST_OFFSET); |
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| 177 | ppc_cached_irq_mask &= ~(1 << (31-siu_irq_index)); |
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| 178 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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| 179 | |
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| 180 | return 0; |
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| 181 | } |
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| 182 | |
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[adc53ec9] | 183 | int BSP_irq_enabled_at_siu (const rtems_irq_number irqLine) |
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[35bb69b] | 184 | { |
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| 185 | int siu_irq_index; |
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| 186 | |
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| 187 | if (!is_siu_irq(irqLine)) |
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| 188 | return 0; |
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| 189 | |
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| 190 | siu_irq_index = ((int) (irqLine) - BSP_SIU_IRQ_LOWEST_OFFSET); |
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| 191 | return ppc_cached_irq_mask & (1 << (31-siu_irq_index)); |
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| 192 | } |
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| 193 | |
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| 194 | /* |
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| 195 | * ------------------------ RTEMS Single Irq Handler Mngt Routines ---------------- |
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| 196 | */ |
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| 197 | |
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| 198 | int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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| 199 | { |
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[ec1d0b9d] | 200 | rtems_interrupt_level level; |
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[6128a4a] | 201 | |
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[35bb69b] | 202 | if (!isValidInterrupt(irq->name)) { |
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| 203 | return 0; |
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| 204 | } |
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| 205 | /* |
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| 206 | * Check if default handler is actually connected. If not issue an error. |
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| 207 | * You must first get the current handler via i386_get_current_idt_entry |
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| 208 | * and then disconnect it using i386_delete_idt_entry. |
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| 209 | * RATIONALE : to always have the same transition by forcing the user |
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| 210 | * to get the previous handler before accepting to disconnect. |
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| 211 | */ |
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| 212 | if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { |
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| 213 | return 0; |
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| 214 | } |
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| 215 | |
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[ec1d0b9d] | 216 | rtems_interrupt_disable(level); |
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[35bb69b] | 217 | |
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| 218 | /* |
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| 219 | * store the data provided by user |
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| 220 | */ |
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| 221 | rtems_hdl_tbl[irq->name] = *irq; |
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[6128a4a] | 222 | |
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[35bb69b] | 223 | if (is_cpm_irq(irq->name)) { |
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| 224 | /* |
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| 225 | * Enable interrupt at PIC level |
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| 226 | */ |
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| 227 | BSP_irq_enable_at_cpm (irq->name); |
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| 228 | } |
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[6128a4a] | 229 | |
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[35bb69b] | 230 | if (is_siu_irq(irq->name)) { |
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| 231 | /* |
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| 232 | * Enable interrupt at SIU level |
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| 233 | */ |
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| 234 | BSP_irq_enable_at_siu (irq->name); |
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| 235 | } |
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| 236 | |
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| 237 | if (is_processor_irq(irq->name)) { |
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| 238 | /* |
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| 239 | * Should Enable exception at processor level but not needed. Will restore |
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| 240 | * EE flags at the end of the routine anyway. |
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| 241 | */ |
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| 242 | } |
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| 243 | /* |
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| 244 | * Enable interrupt on device |
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| 245 | */ |
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[a4722f82] | 246 | if (irq->on) |
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| 247 | irq->on(irq); |
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[6128a4a] | 248 | |
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[ec1d0b9d] | 249 | rtems_interrupt_enable(level); |
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[35bb69b] | 250 | |
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| 251 | return 1; |
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| 252 | } |
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| 253 | |
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| 254 | int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) |
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| 255 | { |
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| 256 | if (!isValidInterrupt(irq->name)) { |
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| 257 | return 0; |
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| 258 | } |
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| 259 | *irq = rtems_hdl_tbl[irq->name]; |
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| 260 | return 1; |
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| 261 | } |
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| 262 | |
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| 263 | int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) |
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| 264 | { |
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[ec1d0b9d] | 265 | rtems_interrupt_level level; |
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[6128a4a] | 266 | |
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[35bb69b] | 267 | if (!isValidInterrupt(irq->name)) { |
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| 268 | return 0; |
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| 269 | } |
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| 270 | /* |
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| 271 | * Check if default handler is actually connected. If not issue an error. |
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| 272 | * You must first get the current handler via i386_get_current_idt_entry |
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| 273 | * and then disconnect it using i386_delete_idt_entry. |
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| 274 | * RATIONALE : to always have the same transition by forcing the user |
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| 275 | * to get the previous handler before accepting to disconnect. |
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| 276 | */ |
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| 277 | if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { |
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| 278 | return 0; |
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| 279 | } |
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[ec1d0b9d] | 280 | rtems_interrupt_disable(level); |
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[35bb69b] | 281 | |
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| 282 | if (is_cpm_irq(irq->name)) { |
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| 283 | /* |
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| 284 | * disable interrupt at PIC level |
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| 285 | */ |
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| 286 | BSP_irq_disable_at_cpm (irq->name); |
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| 287 | } |
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| 288 | if (is_siu_irq(irq->name)) { |
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| 289 | /* |
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| 290 | * disable interrupt at OPENPIC level |
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| 291 | */ |
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| 292 | BSP_irq_disable_at_siu (irq->name); |
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| 293 | } |
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| 294 | if (is_processor_irq(irq->name)) { |
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| 295 | /* |
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| 296 | * disable exception at processor level |
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| 297 | */ |
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[6128a4a] | 298 | } |
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[35bb69b] | 299 | |
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| 300 | /* |
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| 301 | * Disable interrupt on device |
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| 302 | */ |
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[a4722f82] | 303 | if (irq->off) |
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| 304 | irq->off(irq); |
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[35bb69b] | 305 | |
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| 306 | /* |
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| 307 | * restore the default irq value |
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| 308 | */ |
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| 309 | rtems_hdl_tbl[irq->name] = default_rtems_entry; |
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| 310 | |
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[ec1d0b9d] | 311 | rtems_interrupt_enable(level); |
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[35bb69b] | 312 | |
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| 313 | return 1; |
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| 314 | } |
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| 315 | |
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| 316 | /* |
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| 317 | * ------------------------ RTEMS Global Irq Handler Mngt Routines ---------------- |
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| 318 | */ |
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| 319 | |
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| 320 | int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config) |
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| 321 | { |
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[ec1d0b9d] | 322 | int i; |
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| 323 | rtems_interrupt_level level; |
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| 324 | |
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| 325 | /* |
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| 326 | * Store various code accelerators |
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| 327 | */ |
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[35bb69b] | 328 | internal_config = config; |
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| 329 | default_rtems_entry = config->defaultEntry; |
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| 330 | rtems_hdl_tbl = config->irqHdlTbl; |
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| 331 | |
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[ec1d0b9d] | 332 | rtems_interrupt_disable(level); |
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[35bb69b] | 333 | /* |
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| 334 | * start with CPM IRQ |
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| 335 | */ |
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| 336 | for (i=BSP_CPM_IRQ_LOWEST_OFFSET; i < BSP_CPM_IRQ_LOWEST_OFFSET + BSP_CPM_IRQ_NUMBER ; i++) { |
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| 337 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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| 338 | BSP_irq_enable_at_cpm (i); |
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[a4722f82] | 339 | if (rtems_hdl_tbl[i].on) |
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| 340 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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[35bb69b] | 341 | } |
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| 342 | else { |
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[a4722f82] | 343 | if (rtems_hdl_tbl[i].off) |
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| 344 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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[35bb69b] | 345 | BSP_irq_disable_at_cpm (i); |
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| 346 | } |
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| 347 | } |
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| 348 | |
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| 349 | /* |
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| 350 | * continue with PCI IRQ |
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| 351 | */ |
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| 352 | /* |
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| 353 | * set up internal tables used by rtems interrupt prologue |
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| 354 | */ |
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| 355 | compute_SIU_IvectMask_from_prio (); |
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| 356 | |
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| 357 | for (i=BSP_SIU_IRQ_LOWEST_OFFSET; i < BSP_SIU_IRQ_LOWEST_OFFSET + BSP_SIU_IRQ_NUMBER ; i++) { |
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| 358 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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| 359 | BSP_irq_enable_at_siu (i); |
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[a4722f82] | 360 | if (rtems_hdl_tbl[i].on) |
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| 361 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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[35bb69b] | 362 | } |
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| 363 | else { |
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[a4722f82] | 364 | if (rtems_hdl_tbl[i].off) |
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| 365 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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[35bb69b] | 366 | BSP_irq_disable_at_siu (i); |
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| 367 | } |
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| 368 | } |
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| 369 | /* |
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| 370 | * Must enable CPM interrupt on SIU. CPM on SIU Interrupt level has already been |
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| 371 | * set up in BSP_CPM_irq_init. |
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| 372 | */ |
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| 373 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr |= CICR_IEN; |
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| 374 | BSP_irq_enable_at_siu (BSP_CPM_INTERRUPT); |
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| 375 | /* |
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| 376 | * finish with Processor exceptions handled like IRQ |
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| 377 | */ |
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| 378 | for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER; i++) { |
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| 379 | if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) { |
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[a4722f82] | 380 | if (rtems_hdl_tbl[i].on) |
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| 381 | rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]); |
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[35bb69b] | 382 | } |
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| 383 | else { |
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[a4722f82] | 384 | if (rtems_hdl_tbl[i].off) |
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| 385 | rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]); |
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[35bb69b] | 386 | } |
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| 387 | } |
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[ec1d0b9d] | 388 | rtems_interrupt_enable(level); |
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[35bb69b] | 389 | return 1; |
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| 390 | } |
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| 391 | |
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| 392 | int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config) |
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| 393 | { |
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| 394 | *config = internal_config; |
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| 395 | return 0; |
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| 396 | } |
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| 397 | |
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| 398 | #ifdef DISPATCH_HANDLER_STAT |
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| 399 | volatile unsigned int maxLoop = 0; |
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| 400 | #endif |
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| 401 | |
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| 402 | /* |
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| 403 | * High level IRQ handler called from shared_raw_irq_code_entry |
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| 404 | */ |
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[a9e62c2] | 405 | int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) |
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[35bb69b] | 406 | { |
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| 407 | register unsigned int irq; |
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| 408 | register unsigned cpmIntr; /* boolean */ |
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| 409 | register unsigned oldMask; /* old siu pic masks */ |
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| 410 | register unsigned msr; |
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| 411 | register unsigned new_msr; |
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[8038731] | 412 | #ifdef DISPATCH_HANDLER_STAT |
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[35bb69b] | 413 | unsigned loopCounter; |
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[8038731] | 414 | #endif |
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[35bb69b] | 415 | /* |
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| 416 | * Handle decrementer interrupt |
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| 417 | */ |
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| 418 | if (excNum == ASM_DEC_VECTOR) { |
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| 419 | _CPU_MSR_GET(msr); |
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| 420 | new_msr = msr | MSR_EE; |
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| 421 | _CPU_MSR_SET(new_msr); |
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[6128a4a] | 422 | |
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[8a463b4] | 423 | rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle); |
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[35bb69b] | 424 | |
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| 425 | _CPU_MSR_SET(msr); |
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[a9e62c2] | 426 | return 0; |
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[35bb69b] | 427 | } |
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| 428 | /* |
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| 429 | * Handle external interrupt generated by SIU on PPC core |
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| 430 | */ |
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| 431 | #ifdef DISPATCH_HANDLER_STAT |
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| 432 | loopCounter = 0; |
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[6128a4a] | 433 | #endif |
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[35bb69b] | 434 | while (1) { |
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| 435 | if ((ppc_cached_irq_mask & ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend) == 0) { |
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| 436 | #ifdef DISPATCH_HANDLER_STAT |
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| 437 | if (loopCounter > maxLoop) maxLoop = loopCounter; |
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[6128a4a] | 438 | #endif |
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[35bb69b] | 439 | break; |
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| 440 | } |
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| 441 | irq = (((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec >> 26); |
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| 442 | cpmIntr = (irq == BSP_CPM_INTERRUPT); |
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| 443 | /* |
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| 444 | * Disable the interrupt of the same and lower priority. |
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| 445 | */ |
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| 446 | oldMask = ppc_cached_irq_mask; |
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| 447 | ppc_cached_irq_mask = oldMask & SIU_IvectMask[irq]; |
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| 448 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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| 449 | /* |
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| 450 | * Acknowledge current interrupt. This has no effect on internal level interrupt. |
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| 451 | */ |
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| 452 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend = (1 << (31 - irq)); |
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[6128a4a] | 453 | |
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[35bb69b] | 454 | if (cpmIntr) { |
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| 455 | /* |
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| 456 | * We will reenable the SIU CPM interrupt to allow nesting of CPM interrupt. |
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| 457 | * We must before acknowledege the current irq at CPM level to avoid trigerring |
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[6128a4a] | 458 | * the interrupt again. |
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[35bb69b] | 459 | */ |
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| 460 | /* |
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| 461 | * Acknowledge and get the vector. |
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| 462 | */ |
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| 463 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr = 1; |
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| 464 | irq = (((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_civr >> 11); |
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| 465 | /* |
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| 466 | * transform IRQ to normalized irq table index. |
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| 467 | */ |
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| 468 | irq += BSP_CPM_IRQ_LOWEST_OFFSET; |
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| 469 | /* |
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| 470 | * Unmask CPM interrupt at SIU level |
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| 471 | */ |
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| 472 | ppc_cached_irq_mask |= (1 << (31 - BSP_CPM_INTERRUPT)); |
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| 473 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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| 474 | } |
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[42bf1b9] | 475 | /* |
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| 476 | * make sure, that the masking operations in |
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| 477 | * ICTL and MSR are executed in order |
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| 478 | */ |
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| 479 | asm volatile("sync":::"memory"); |
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| 480 | |
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[35bb69b] | 481 | _CPU_MSR_GET(msr); |
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| 482 | new_msr = msr | MSR_EE; |
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| 483 | _CPU_MSR_SET(new_msr); |
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[6128a4a] | 484 | |
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[ef546c3] | 485 | rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle); |
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[35bb69b] | 486 | |
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| 487 | _CPU_MSR_SET(msr); |
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| 488 | |
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[42bf1b9] | 489 | /* |
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| 490 | * make sure, that the masking operations in |
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| 491 | * ICTL and MSR are executed in order |
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| 492 | */ |
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| 493 | asm volatile("sync":::"memory"); |
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| 494 | |
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[35bb69b] | 495 | if (cpmIntr) { |
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| 496 | irq -= BSP_CPM_IRQ_LOWEST_OFFSET; |
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| 497 | ((volatile immap_t *)IMAP_ADDR)->im_cpic.cpic_cisr = (1 << irq); |
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| 498 | } |
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[be1c6bcd] | 499 | ppc_cached_irq_mask = oldMask; |
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[35bb69b] | 500 | ((volatile immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask = ppc_cached_irq_mask; |
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| 501 | #ifdef DISPATCH_HANDLER_STAT |
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| 502 | ++ loopCounter; |
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[6128a4a] | 503 | #endif |
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[35bb69b] | 504 | } |
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[a9e62c2] | 505 | return 0; |
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[35bb69b] | 506 | } |
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| 507 | |
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| 508 | void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx) |
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| 509 | { |
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| 510 | /* |
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| 511 | * Process pending signals that have not already been |
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| 512 | * processed by _Thread_Displatch. This happens quite |
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| 513 | * unfrequently : the ISR must have posted an action |
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| 514 | * to the current running thread. |
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| 515 | */ |
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| 516 | if ( _Thread_Do_post_task_switch_extension || |
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| 517 | _Thread_Executing->do_post_task_switch_extension ) { |
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[39d08d55] | 518 | _Thread_Executing->do_post_task_switch_extension = false; |
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[35bb69b] | 519 | _API_extensions_Run_postswitch(); |
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| 520 | } |
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| 521 | /* |
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| 522 | * I plan to process other thread related events here. |
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| 523 | * This will include DEBUG session requested from keyboard... |
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| 524 | */ |
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| 525 | } |
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