1 | |
---|
2 | /* |
---|
3 | * A collection of structures, addresses, and values associated with |
---|
4 | * the Motorola MBX boards. This was originally created for the |
---|
5 | * MBX860, and probably needs revisions for other boards (like the 821). |
---|
6 | * When this file gets out of control, we can split it up into more |
---|
7 | * meaningful pieces. |
---|
8 | * |
---|
9 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) |
---|
10 | */ |
---|
11 | #ifndef __MACH_MBX_DEFS |
---|
12 | #define __MACH_MBX_DEFS |
---|
13 | |
---|
14 | /* A Board Information structure that is given to a program when |
---|
15 | * EPPC-Bug starts it up. |
---|
16 | */ |
---|
17 | typedef struct bd_info { |
---|
18 | unsigned int bi_tag; /* Should be 0x42444944 "BDID" */ |
---|
19 | unsigned int bi_size; /* Size of this structure */ |
---|
20 | unsigned int bi_revision; /* revision of this structure */ |
---|
21 | unsigned int bi_bdate; /* EPPCbug date, i.e. 0x11061997 */ |
---|
22 | unsigned int bi_memstart; /* Memory start address */ |
---|
23 | unsigned int bi_memsize; /* Memory (end) size in bytes */ |
---|
24 | unsigned int bi_intfreq; /* Internal Freq, in Hz */ |
---|
25 | unsigned int bi_busfreq; /* Bus Freq, in Hz */ |
---|
26 | unsigned int bi_clun; /* Boot device controller */ |
---|
27 | unsigned int bi_dlun; /* Boot device logical dev */ |
---|
28 | } bd_t; |
---|
29 | |
---|
30 | /* Memory map for the MBX as configured by EPPC-Bug. We could reprogram |
---|
31 | * The SIU and PCI bridge, and try to use larger MMU pages, but the |
---|
32 | * performance gain is not measureable and it certainly complicates the |
---|
33 | * generic MMU model. |
---|
34 | * |
---|
35 | * In a effort to minimize memory usage for embedded applications, any |
---|
36 | * PCI driver or ISA driver must request or map the region required by |
---|
37 | * the device. For convenience (and since we can map up to 4 Mbytes with |
---|
38 | * a single page table page), the MMU initialization will map the |
---|
39 | * NVRAM, Status/Control registers, CPM Dual Port RAM, and the PCI |
---|
40 | * Bridge CSRs 1:1 into the kernel address space. |
---|
41 | */ |
---|
42 | #define PCI_ISA_IO_ADDR ((unsigned int)0x80000000) |
---|
43 | #define PCI_ISA_IO_SIZE ((unsigned int)(512 * 1024 * 1024)) |
---|
44 | #define PCI_ISA_MEM_ADDR ((unsigned int)0xc0000000) |
---|
45 | #define PCI_ISA_MEM_SIZE ((unsigned int)(512 * 1024 * 1024)) |
---|
46 | #define PCMCIA_MEM_ADDR ((unsigned int)0xe0000000) |
---|
47 | #define PCMCIA_MEM_SIZE ((unsigned int)(64 * 1024 * 1024)) |
---|
48 | #define PCMCIA_DMA_ADDR ((unsigned int)0xe4000000) |
---|
49 | #define PCMCIA_DMA_SIZE ((unsigned int)(64 * 1024 * 1024)) |
---|
50 | #define PCMCIA_ATTRB_ADDR ((unsigned int)0xe8000000) |
---|
51 | #define PCMCIA_ATTRB_SIZE ((unsigned int)(64 * 1024 * 1024)) |
---|
52 | #define PCMCIA_IO_ADDR ((unsigned int)0xec000000) |
---|
53 | #define PCMCIA_IO_SIZE ((unsigned int)(64 * 1024 * 1024)) |
---|
54 | #define NVRAM_ADDR ((unsigned int)0xfa000000) |
---|
55 | #define NVRAM_SIZE ((unsigned int)(1 * 1024 * 1024)) |
---|
56 | #define MBX_CSR_ADDR ((unsigned int)0xfa100000) |
---|
57 | #define MBX_CSR_SIZE ((unsigned int)(1 * 1024 * 1024)) |
---|
58 | #define IMAP_ADDR ((unsigned int)0xfa200000) |
---|
59 | #define IMAP_SIZE ((unsigned int)(64 * 1024)) |
---|
60 | #define PCI_CSR_ADDR ((unsigned int)0xfa210000) |
---|
61 | #define PCI_CSR_SIZE ((unsigned int)(64 * 1024)) |
---|
62 | |
---|
63 | #define MBX_CSR2 (MBX_CSR_ADDR+1) |
---|
64 | #endif |
---|