1 | |
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2 | /* |
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3 | * MPC8xx Communication Processor Module. |
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4 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) |
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5 | * |
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6 | * This file contains structures and information for the communication |
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7 | * processor channels. Some CPM control and status is available |
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8 | * throught the MPC8xx internal memory map. See immap.h for details. |
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9 | * This file only contains what I need for the moment, not the total |
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10 | * CPM capabilities. I (or someone else) will add definitions as they |
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11 | * are needed. -- Dan |
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12 | * |
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13 | * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 |
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14 | * bytes of the DP RAM and relocates the I2C parameter area to the |
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15 | * IDMA1 space. The remaining DP RAM is available for buffer descriptors |
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16 | * or other use. |
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17 | */ |
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18 | #ifndef __CPM_8XX__ |
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19 | #define __CPM_8XX__ |
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20 | |
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21 | #include <bsp/8xx_immap.h> |
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22 | |
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23 | /* CPM Command register. |
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24 | */ |
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25 | #define CPM_CR_RST ((unsigned short)0x8000) |
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26 | #define CPM_CR_OPCODE ((unsigned short)0x0f00) |
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27 | #define CPM_CR_CHAN ((unsigned short)0x00f0) |
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28 | #define CPM_CR_FLG ((unsigned short)0x0001) |
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29 | |
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30 | /* Some commands (there are more...later) |
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31 | */ |
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32 | #define CPM_CR_INIT_TRX ((unsigned short)0x0000) |
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33 | #define CPM_CR_INIT_RX ((unsigned short)0x0001) |
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34 | #define CPM_CR_INIT_TX ((unsigned short)0x0002) |
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35 | #define CPM_CR_STOP_TX ((unsigned short)0x0004) |
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36 | #define CPM_CR_RESTART_TX ((unsigned short)0x0006) |
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37 | #define CPM_CR_SET_GADDR ((unsigned short)0x0008) |
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38 | |
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39 | /* Channel numbers. |
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40 | */ |
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41 | #define CPM_CR_CH_SCC1 ((unsigned short)0x0000) |
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42 | #define CPM_CR_CH_I2C ((unsigned short)0x0001) /* I2C and IDMA1 */ |
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43 | #define CPM_CR_CH_SCC2 ((unsigned short)0x0004) |
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44 | #define CPM_CR_CH_SPI ((unsigned short)0x0005) /* SPI / IDMA2 / Timers */ |
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45 | #define CPM_CR_CH_SCC3 ((unsigned short)0x0008) |
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46 | #define CPM_CR_CH_SMC1 ((unsigned short)0x0009) /* SMC1 / DSP1 */ |
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47 | #define CPM_CR_CH_SCC4 ((unsigned short)0x000c) |
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48 | #define CPM_CR_CH_SMC2 ((unsigned short)0x000d) /* SMC2 / DSP2 */ |
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49 | |
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50 | #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) |
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51 | |
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52 | /* The dual ported RAM is multi-functional. Some areas can be (and are |
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53 | * being) used for microcode. There is an area that can only be used |
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54 | * as data ram for buffer descriptors, which is all we use right now. |
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55 | * Currently the first 512 and last 256 bytes are used for microcode. |
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56 | */ |
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57 | #define CPM_DATAONLY_BASE ((unsigned int)0x0800) |
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58 | #define CPM_DATAONLY_SIZE ((unsigned int)0x0700) |
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59 | #define CPM_DP_NOSPACE ((unsigned int)0x7fffffff) |
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60 | |
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61 | /* Export the base address of the communication processor registers |
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62 | * and dual port ram. |
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63 | */ |
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64 | unsigned int m8xx_cpm_dpalloc(unsigned int size); |
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65 | unsigned int m8xx_cpm_hostalloc(unsigned int size); |
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66 | void m8xx_cpm_setbrg(unsigned int brg, unsigned int rate); |
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67 | |
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68 | /* Buffer descriptors used by many of the CPM protocols. |
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69 | */ |
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70 | typedef struct cpm_buf_desc { |
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71 | unsigned short cbd_sc; /* Status and Control */ |
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72 | unsigned short cbd_datlen; /* Data length in buffer */ |
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73 | unsigned int cbd_bufaddr; /* Buffer address in host memory */ |
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74 | } cbd_t; |
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75 | |
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76 | #define BD_SC_EMPTY ((unsigned short)0x8000) /* Recieve is empty */ |
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77 | #define BD_SC_READY ((unsigned short)0x8000) /* Transmit is ready */ |
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78 | #define BD_SC_WRAP ((unsigned short)0x2000) /* Last buffer descriptor */ |
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79 | #define BD_SC_INTRPT ((unsigned short)0x1000) /* Interrupt on change */ |
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80 | #define BD_SC_CM ((unsigned short)0x0200) /* Continous mode */ |
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81 | #define BD_SC_ID ((unsigned short)0x0100) /* Rec'd too many idles */ |
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82 | #define BD_SC_P ((unsigned short)0x0100) /* xmt preamble */ |
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83 | #define BD_SC_BR ((unsigned short)0x0020) /* Break received */ |
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84 | #define BD_SC_FR ((unsigned short)0x0010) /* Framing error */ |
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85 | #define BD_SC_PR ((unsigned short)0x0008) /* Parity error */ |
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86 | #define BD_SC_OV ((unsigned short)0x0002) /* Overrun */ |
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87 | #define BD_SC_CD ((unsigned short)0x0001) /* ?? */ |
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88 | |
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89 | /* Parameter RAM offsets. |
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90 | */ |
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91 | #define PROFF_SCC1 ((unsigned int)0x0000) |
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92 | #define PROFF_SCC2 ((unsigned int)0x0100) |
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93 | #define PROFF_SCC3 ((unsigned int)0x0200) |
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94 | #define PROFF_SMC1 ((unsigned int)0x0280) |
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95 | #define PROFF_SCC4 ((unsigned int)0x0300) |
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96 | #define PROFF_SMC2 ((unsigned int)0x0380) |
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97 | |
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98 | /* Define enough so I can at least use the serial port as a UART. |
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99 | */ |
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100 | typedef struct smc_uart { |
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101 | unsigned short smc_rbase; /* Rx Buffer descriptor base address */ |
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102 | unsigned short smc_tbase; /* Tx Buffer descriptor base address */ |
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103 | unsigned char smc_rfcr; /* Rx function code */ |
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104 | unsigned char smc_tfcr; /* Tx function code */ |
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105 | unsigned short smc_mrblr; /* Max receive buffer length */ |
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106 | unsigned int smc_rstate; /* Internal */ |
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107 | unsigned int smc_idp; /* Internal */ |
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108 | unsigned short smc_rbptr; /* Internal */ |
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109 | unsigned short smc_ibc; /* Internal */ |
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110 | unsigned int smc_rxtmp; /* Internal */ |
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111 | unsigned int smc_tstate; /* Internal */ |
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112 | unsigned int smc_tdp; /* Internal */ |
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113 | unsigned short smc_tbptr; /* Internal */ |
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114 | unsigned short smc_tbc; /* Internal */ |
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115 | unsigned int smc_txtmp; /* Internal */ |
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116 | unsigned short smc_maxidl; /* Maximum idle characters */ |
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117 | unsigned short smc_tmpidl; /* Temporary idle counter */ |
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118 | unsigned short smc_brklen; /* Last received break length */ |
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119 | unsigned short smc_brkec; /* rcv'd break condition counter */ |
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120 | unsigned short smc_brkcr; /* xmt break count register */ |
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121 | unsigned short smc_rmask; /* Temporary bit mask */ |
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122 | } smc_uart_t; |
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123 | |
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124 | /* Function code bits. |
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125 | */ |
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126 | #define SMC_EB ((unsigned char)0x10) /* Set big endian byte order */ |
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127 | |
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128 | /* SMC uart mode register. |
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129 | */ |
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130 | #define SMCMR_REN ((unsigned short)0x0001) |
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131 | #define SMCMR_TEN ((unsigned short)0x0002) |
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132 | #define SMCMR_DM ((unsigned short)0x000c) |
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133 | #define SMCMR_SM_GCI ((unsigned short)0x0000) |
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134 | #define SMCMR_SM_UART ((unsigned short)0x0020) |
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135 | #define SMCMR_SM_TRANS ((unsigned short)0x0030) |
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136 | #define SMCMR_SM_MASK ((unsigned short)0x0030) |
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137 | #define SMCMR_PM_EVEN ((unsigned short)0x0100) /* Even parity, else odd */ |
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138 | #define SMCMR_PEN ((unsigned short)0x0200) /* Parity enable */ |
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139 | #define SMCMR_SL ((unsigned short)0x0400) /* Two stops, else one */ |
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140 | #define SMCR_CLEN_MASK ((unsigned short)0x7800) /* Character length */ |
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141 | #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) |
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142 | |
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143 | /* SMC Event and Mask register. |
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144 | */ |
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145 | #define SMCM_TXE ((unsigned char)0x10) |
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146 | #define SMCM_BSY ((unsigned char)0x04) |
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147 | #define SMCM_TX ((unsigned char)0x02) |
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148 | #define SMCM_RX ((unsigned char)0x01) |
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149 | |
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150 | /* Baud rate generators. |
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151 | */ |
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152 | #define CPM_BRG_RST ((unsigned int)0x00020000) |
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153 | #define CPM_BRG_EN ((unsigned int)0x00010000) |
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154 | #define CPM_BRG_EXTC_INT ((unsigned int)0x00000000) |
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155 | #define CPM_BRG_EXTC_CLK2 ((unsigned int)0x00004000) |
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156 | #define CPM_BRG_EXTC_CLK6 ((unsigned int)0x00008000) |
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157 | #define CPM_BRG_ATB ((unsigned int)0x00002000) |
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158 | #define CPM_BRG_CD_MASK ((unsigned int)0x00001ffe) |
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159 | #define CPM_BRG_DIV16 ((unsigned int)0x00000001) |
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160 | |
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161 | /* SCCs. |
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162 | */ |
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163 | #define SCC_GSMRH_IRP ((unsigned int)0x00040000) |
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164 | #define SCC_GSMRH_GDE ((unsigned int)0x00010000) |
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165 | #define SCC_GSMRH_TCRC_CCITT ((unsigned int)0x00008000) |
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166 | #define SCC_GSMRH_TCRC_BISYNC ((unsigned int)0x00004000) |
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167 | #define SCC_GSMRH_TCRC_HDLC ((unsigned int)0x00000000) |
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168 | #define SCC_GSMRH_REVD ((unsigned int)0x00002000) |
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169 | #define SCC_GSMRH_TRX ((unsigned int)0x00001000) |
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170 | #define SCC_GSMRH_TTX ((unsigned int)0x00000800) |
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171 | #define SCC_GSMRH_CDP ((unsigned int)0x00000400) |
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172 | #define SCC_GSMRH_CTSP ((unsigned int)0x00000200) |
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173 | #define SCC_GSMRH_CDS ((unsigned int)0x00000100) |
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174 | #define SCC_GSMRH_CTSS ((unsigned int)0x00000080) |
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175 | #define SCC_GSMRH_TFL ((unsigned int)0x00000040) |
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176 | #define SCC_GSMRH_RFW ((unsigned int)0x00000020) |
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177 | #define SCC_GSMRH_TXSY ((unsigned int)0x00000010) |
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178 | #define SCC_GSMRH_SYNL16 ((unsigned int)0x0000000c) |
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179 | #define SCC_GSMRH_SYNL8 ((unsigned int)0x00000008) |
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180 | #define SCC_GSMRH_SYNL4 ((unsigned int)0x00000004) |
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181 | #define SCC_GSMRH_RTSM ((unsigned int)0x00000002) |
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182 | #define SCC_GSMRH_RSYN ((unsigned int)0x00000001) |
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183 | |
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184 | #define SCC_GSMRL_SIR ((unsigned int)0x80000000) /* SCC2 only */ |
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185 | #define SCC_GSMRL_EDGE_NONE ((unsigned int)0x60000000) |
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186 | #define SCC_GSMRL_EDGE_NEG ((unsigned int)0x40000000) |
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187 | #define SCC_GSMRL_EDGE_POS ((unsigned int)0x20000000) |
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188 | #define SCC_GSMRL_EDGE_BOTH ((unsigned int)0x00000000) |
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189 | #define SCC_GSMRL_TCI ((unsigned int)0x10000000) |
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190 | #define SCC_GSMRL_TSNC_3 ((unsigned int)0x0c000000) |
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191 | #define SCC_GSMRL_TSNC_4 ((unsigned int)0x08000000) |
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192 | #define SCC_GSMRL_TSNC_14 ((unsigned int)0x04000000) |
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193 | #define SCC_GSMRL_TSNC_INF ((unsigned int)0x00000000) |
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194 | #define SCC_GSMRL_RINV ((unsigned int)0x02000000) |
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195 | #define SCC_GSMRL_TINV ((unsigned int)0x01000000) |
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196 | #define SCC_GSMRL_TPL_128 ((unsigned int)0x00c00000) |
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197 | #define SCC_GSMRL_TPL_64 ((unsigned int)0x00a00000) |
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198 | #define SCC_GSMRL_TPL_48 ((unsigned int)0x00800000) |
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199 | #define SCC_GSMRL_TPL_32 ((unsigned int)0x00600000) |
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200 | #define SCC_GSMRL_TPL_16 ((unsigned int)0x00400000) |
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201 | #define SCC_GSMRL_TPL_8 ((unsigned int)0x00200000) |
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202 | #define SCC_GSMRL_TPL_NONE ((unsigned int)0x00000000) |
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203 | #define SCC_GSMRL_TPP_ALL1 ((unsigned int)0x00180000) |
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204 | #define SCC_GSMRL_TPP_01 ((unsigned int)0x00100000) |
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205 | #define SCC_GSMRL_TPP_10 ((unsigned int)0x00080000) |
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206 | #define SCC_GSMRL_TPP_ZEROS ((unsigned int)0x00000000) |
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207 | #define SCC_GSMRL_TEND ((unsigned int)0x00040000) |
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208 | #define SCC_GSMRL_TDCR_32 ((unsigned int)0x00030000) |
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209 | #define SCC_GSMRL_TDCR_16 ((unsigned int)0x00020000) |
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210 | #define SCC_GSMRL_TDCR_8 ((unsigned int)0x00010000) |
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211 | #define SCC_GSMRL_TDCR_1 ((unsigned int)0x00000000) |
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212 | #define SCC_GSMRL_RDCR_32 ((unsigned int)0x0000c000) |
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213 | #define SCC_GSMRL_RDCR_16 ((unsigned int)0x00008000) |
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214 | #define SCC_GSMRL_RDCR_8 ((unsigned int)0x00004000) |
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215 | #define SCC_GSMRL_RDCR_1 ((unsigned int)0x00000000) |
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216 | #define SCC_GSMRL_RENC_DFMAN ((unsigned int)0x00003000) |
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217 | #define SCC_GSMRL_RENC_MANCH ((unsigned int)0x00002000) |
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218 | #define SCC_GSMRL_RENC_FM0 ((unsigned int)0x00001000) |
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219 | #define SCC_GSMRL_RENC_NRZI ((unsigned int)0x00000800) |
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220 | #define SCC_GSMRL_RENC_NRZ ((unsigned int)0x00000000) |
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221 | #define SCC_GSMRL_TENC_DFMAN ((unsigned int)0x00000600) |
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222 | #define SCC_GSMRL_TENC_MANCH ((unsigned int)0x00000400) |
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223 | #define SCC_GSMRL_TENC_FM0 ((unsigned int)0x00000200) |
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224 | #define SCC_GSMRL_TENC_NRZI ((unsigned int)0x00000100) |
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225 | #define SCC_GSMRL_TENC_NRZ ((unsigned int)0x00000000) |
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226 | #define SCC_GSMRL_DIAG_LE ((unsigned int)0x000000c0) /* Loop and echo */ |
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227 | #define SCC_GSMRL_DIAG_ECHO ((unsigned int)0x00000080) |
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228 | #define SCC_GSMRL_DIAG_LOOP ((unsigned int)0x00000040) |
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229 | #define SCC_GSMRL_DIAG_NORM ((unsigned int)0x00000000) |
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230 | #define SCC_GSMRL_ENR ((unsigned int)0x00000020) |
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231 | #define SCC_GSMRL_ENT ((unsigned int)0x00000010) |
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232 | #define SCC_GSMRL_MODE_ENET ((unsigned int)0x0000000c) |
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233 | #define SCC_GSMRL_MODE_DDCMP ((unsigned int)0x00000009) |
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234 | #define SCC_GSMRL_MODE_BISYNC ((unsigned int)0x00000008) |
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235 | #define SCC_GSMRL_MODE_V14 ((unsigned int)0x00000007) |
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236 | #define SCC_GSMRL_MODE_AHDLC ((unsigned int)0x00000006) |
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237 | #define SCC_GSMRL_MODE_PROFIBUS ((unsigned int)0x00000005) |
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238 | #define SCC_GSMRL_MODE_UART ((unsigned int)0x00000004) |
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239 | #define SCC_GSMRL_MODE_SS7 ((unsigned int)0x00000003) |
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240 | #define SCC_GSMRL_MODE_ATALK ((unsigned int)0x00000002) |
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241 | #define SCC_GSMRL_MODE_HDLC ((unsigned int)0x00000000) |
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242 | |
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243 | #define SCC_TODR_TOD ((unsigned short)0x8000) |
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244 | |
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245 | /* SCC Event and Mask register. |
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246 | */ |
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247 | #define SCCM_TXE ((unsigned char)0x10) |
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248 | #define SCCM_BSY ((unsigned char)0x04) |
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249 | #define SCCM_TX ((unsigned char)0x02) |
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250 | #define SCCM_RX ((unsigned char)0x01) |
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251 | |
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252 | typedef struct scc_param { |
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253 | unsigned short scc_rbase; /* Rx Buffer descriptor base address */ |
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254 | unsigned short scc_tbase; /* Tx Buffer descriptor base address */ |
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255 | unsigned char scc_rfcr; /* Rx function code */ |
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256 | unsigned char scc_tfcr; /* Tx function code */ |
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257 | unsigned short scc_mrblr; /* Max receive buffer length */ |
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258 | unsigned int scc_rstate; /* Internal */ |
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259 | unsigned int scc_idp; /* Internal */ |
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260 | unsigned short scc_rbptr; /* Internal */ |
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261 | unsigned short scc_ibc; /* Internal */ |
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262 | unsigned int scc_rxtmp; /* Internal */ |
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263 | unsigned int scc_tstate; /* Internal */ |
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264 | unsigned int scc_tdp; /* Internal */ |
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265 | unsigned short scc_tbptr; /* Internal */ |
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266 | unsigned short scc_tbc; /* Internal */ |
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267 | unsigned int scc_txtmp; /* Internal */ |
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268 | unsigned int scc_rcrc; /* Internal */ |
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269 | unsigned int scc_tcrc; /* Internal */ |
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270 | } sccp_t; |
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271 | |
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272 | /* Function code bits. |
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273 | */ |
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274 | #define SCC_EB ((unsigned char)0x10) /* Set big endian byte order */ |
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275 | |
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276 | /* CPM Ethernet through SCC1. |
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277 | */ |
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278 | typedef struct scc_enet { |
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279 | sccp_t sen_genscc; |
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280 | unsigned int sen_cpres; /* Preset CRC */ |
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281 | unsigned int sen_cmask; /* Constant mask for CRC */ |
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282 | unsigned int sen_crcec; /* CRC Error counter */ |
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283 | unsigned int sen_alec; /* alignment error counter */ |
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284 | unsigned int sen_disfc; /* discard frame counter */ |
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285 | unsigned short sen_pads; /* Tx short frame pad character */ |
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286 | unsigned short sen_retlim; /* Retry limit threshold */ |
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287 | unsigned short sen_retcnt; /* Retry limit counter */ |
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288 | unsigned short sen_maxflr; /* maximum frame length register */ |
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289 | unsigned short sen_minflr; /* minimum frame length register */ |
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290 | unsigned short sen_maxd1; /* maximum DMA1 length */ |
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291 | unsigned short sen_maxd2; /* maximum DMA2 length */ |
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292 | unsigned short sen_maxd; /* Rx max DMA */ |
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293 | unsigned short sen_dmacnt; /* Rx DMA counter */ |
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294 | unsigned short sen_maxb; /* Max BD byte count */ |
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295 | unsigned short sen_gaddr1; /* Group address filter */ |
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296 | unsigned short sen_gaddr2; |
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297 | unsigned short sen_gaddr3; |
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298 | unsigned short sen_gaddr4; |
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299 | unsigned int sen_tbuf0data0; /* Save area 0 - current frame */ |
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300 | unsigned int sen_tbuf0data1; /* Save area 1 - current frame */ |
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301 | unsigned int sen_tbuf0rba; /* Internal */ |
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302 | unsigned int sen_tbuf0crc; /* Internal */ |
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303 | unsigned short sen_tbuf0bcnt; /* Internal */ |
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304 | unsigned short sen_paddrh; /* physical address (MSB) */ |
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305 | unsigned short sen_paddrm; |
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306 | unsigned short sen_paddrl; /* physical address (LSB) */ |
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307 | unsigned short sen_pper; /* persistence */ |
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308 | unsigned short sen_rfbdptr; /* Rx first BD pointer */ |
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309 | unsigned short sen_tfbdptr; /* Tx first BD pointer */ |
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310 | unsigned short sen_tlbdptr; /* Tx last BD pointer */ |
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311 | unsigned int sen_tbuf1data0; /* Save area 0 - current frame */ |
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312 | unsigned int sen_tbuf1data1; /* Save area 1 - current frame */ |
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313 | unsigned int sen_tbuf1rba; /* Internal */ |
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314 | unsigned int sen_tbuf1crc; /* Internal */ |
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315 | unsigned short sen_tbuf1bcnt; /* Internal */ |
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316 | unsigned short sen_txlen; /* Tx Frame length counter */ |
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317 | unsigned short sen_iaddr1; /* Individual address filter */ |
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318 | unsigned short sen_iaddr2; |
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319 | unsigned short sen_iaddr3; |
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320 | unsigned short sen_iaddr4; |
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321 | unsigned short sen_boffcnt; /* Backoff counter */ |
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322 | |
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323 | /* NOTE: Some versions of the manual have the following items |
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324 | * incorrectly documented. Below is the proper order. |
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325 | */ |
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326 | unsigned short sen_taddrh; /* temp address (MSB) */ |
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327 | unsigned short sen_taddrm; |
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328 | unsigned short sen_taddrl; /* temp address (LSB) */ |
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329 | } scc_enet_t; |
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330 | |
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331 | /* Bits in parallel I/O port registers that have to be set/cleared |
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332 | * to configure the pins for SCC1 use. The TCLK and RCLK seem unique |
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333 | * to the MBX860 board. Any two of the four available clocks could be |
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334 | * used, and the MPC860 cookbook manual has an example using different |
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335 | * clock pins. |
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336 | */ |
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337 | #define PA_ENET_RXD ((unsigned short)0x0001) |
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338 | #define PA_ENET_TXD ((unsigned short)0x0002) |
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339 | #define PA_ENET_TCLK ((unsigned short)0x0200) |
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340 | #define PA_ENET_RCLK ((unsigned short)0x0800) |
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341 | #define PC_ENET_TENA ((unsigned short)0x0001) |
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342 | #define PC_ENET_CLSN ((unsigned short)0x0010) |
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343 | #define PC_ENET_RENA ((unsigned short)0x0020) |
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344 | |
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345 | /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to |
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346 | * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. |
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347 | */ |
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348 | #define SICR_ENET_MASK ((unsigned int)0x000000ff) |
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349 | #define SICR_ENET_CLKRT ((unsigned int)0x0000003d) |
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350 | |
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351 | /* SCC Event register as used by Ethernet. |
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352 | */ |
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353 | #define SCCE_ENET_GRA ((unsigned short)0x0080) /* Graceful stop complete */ |
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354 | #define SCCE_ENET_TXE ((unsigned short)0x0010) /* Transmit Error */ |
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355 | #define SCCE_ENET_RXF ((unsigned short)0x0008) /* Full frame received */ |
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356 | #define SCCE_ENET_BSY ((unsigned short)0x0004) /* All incoming buffers full */ |
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357 | #define SCCE_ENET_TXB ((unsigned short)0x0002) /* A buffer was transmitted */ |
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358 | #define SCCE_ENET_RXB ((unsigned short)0x0001) /* A buffer was received */ |
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359 | |
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360 | /* SCC Mode Register (PMSR) as used by Ethernet. |
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361 | */ |
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362 | #define SCC_PMSR_HBC ((unsigned short)0x8000) /* Enable heartbeat */ |
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363 | #define SCC_PMSR_FC ((unsigned short)0x4000) /* Force collision */ |
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364 | #define SCC_PMSR_RSH ((unsigned short)0x2000) /* Receive short frames */ |
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365 | #define SCC_PMSR_IAM ((unsigned short)0x1000) /* Check individual hash */ |
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366 | #define SCC_PMSR_ENCRC ((unsigned short)0x0800) /* Ethernet CRC mode */ |
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367 | #define SCC_PMSR_PRO ((unsigned short)0x0200) /* Promiscuous mode */ |
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368 | #define SCC_PMSR_BRO ((unsigned short)0x0100) /* Catch broadcast pkts */ |
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369 | #define SCC_PMSR_SBT ((unsigned short)0x0080) /* Special backoff timer */ |
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370 | #define SCC_PMSR_LPB ((unsigned short)0x0040) /* Set Loopback mode */ |
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371 | #define SCC_PMSR_SIP ((unsigned short)0x0020) /* Sample Input Pins */ |
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372 | #define SCC_PMSR_LCW ((unsigned short)0x0010) /* Late collision window */ |
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373 | #define SCC_PMSR_NIB22 ((unsigned short)0x000a) /* Start frame search */ |
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374 | #define SCC_PMSR_FDE ((unsigned short)0x0001) /* Full duplex enable */ |
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375 | |
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376 | /* Buffer descriptor control/status used by Ethernet receive. |
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377 | */ |
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378 | #define BD_ENET_RX_EMPTY ((unsigned short)0x8000) |
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379 | #define BD_ENET_RX_WRAP ((unsigned short)0x2000) |
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380 | #define BD_ENET_RX_INTR ((unsigned short)0x1000) |
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381 | #define BD_ENET_RX_LAST ((unsigned short)0x0800) |
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382 | #define BD_ENET_RX_FIRST ((unsigned short)0x0400) |
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383 | #define BD_ENET_RX_MISS ((unsigned short)0x0100) |
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384 | #define BD_ENET_RX_LG ((unsigned short)0x0020) |
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385 | #define BD_ENET_RX_NO ((unsigned short)0x0010) |
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386 | #define BD_ENET_RX_SH ((unsigned short)0x0008) |
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387 | #define BD_ENET_RX_CR ((unsigned short)0x0004) |
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388 | #define BD_ENET_RX_OV ((unsigned short)0x0002) |
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389 | #define BD_ENET_RX_CL ((unsigned short)0x0001) |
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390 | #define BD_ENET_RX_STATS ((unsigned short)0x013f) /* All status bits */ |
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391 | |
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392 | /* Buffer descriptor control/status used by Ethernet transmit. |
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393 | */ |
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394 | #define BD_ENET_TX_READY ((unsigned short)0x8000) |
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395 | #define BD_ENET_TX_PAD ((unsigned short)0x4000) |
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396 | #define BD_ENET_TX_WRAP ((unsigned short)0x2000) |
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397 | #define BD_ENET_TX_INTR ((unsigned short)0x1000) |
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398 | #define BD_ENET_TX_LAST ((unsigned short)0x0800) |
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399 | #define BD_ENET_TX_TC ((unsigned short)0x0400) |
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400 | #define BD_ENET_TX_DEF ((unsigned short)0x0200) |
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401 | #define BD_ENET_TX_HB ((unsigned short)0x0100) |
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402 | #define BD_ENET_TX_LC ((unsigned short)0x0080) |
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403 | #define BD_ENET_TX_RL ((unsigned short)0x0040) |
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404 | #define BD_ENET_TX_RCMASK ((unsigned short)0x003c) |
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405 | #define BD_ENET_TX_UN ((unsigned short)0x0002) |
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406 | #define BD_ENET_TX_CSL ((unsigned short)0x0001) |
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407 | #define BD_ENET_TX_STATS ((unsigned short)0x03ff) /* All status bits */ |
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408 | |
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409 | /* SCC as UART |
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410 | */ |
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411 | typedef struct scc_uart { |
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412 | sccp_t scc_genscc; |
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413 | unsigned int scc_res1; /* Reserved */ |
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414 | unsigned int scc_res2; /* Reserved */ |
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415 | unsigned short scc_maxidl; /* Maximum idle chars */ |
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416 | unsigned short scc_idlc; /* temp idle counter */ |
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417 | unsigned short scc_brkcr; /* Break count register */ |
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418 | unsigned short scc_parec; /* receive parity error counter */ |
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419 | unsigned short scc_frmec; /* receive framing error counter */ |
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420 | unsigned short scc_nosec; /* receive noise counter */ |
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421 | unsigned short scc_brkec; /* receive break condition counter */ |
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422 | unsigned short scc_brkln; /* last received break length */ |
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423 | unsigned short scc_uaddr1; /* UART address character 1 */ |
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424 | unsigned short scc_uaddr2; /* UART address character 2 */ |
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425 | unsigned short scc_rtemp; /* Temp storage */ |
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426 | unsigned short scc_toseq; /* Transmit out of sequence char */ |
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427 | unsigned short scc_char1; /* control character 1 */ |
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428 | unsigned short scc_char2; /* control character 2 */ |
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429 | unsigned short scc_char3; /* control character 3 */ |
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430 | unsigned short scc_char4; /* control character 4 */ |
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431 | unsigned short scc_char5; /* control character 5 */ |
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432 | unsigned short scc_char6; /* control character 6 */ |
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433 | unsigned short scc_char7; /* control character 7 */ |
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434 | unsigned short scc_char8; /* control character 8 */ |
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435 | unsigned short scc_rccm; /* receive control character mask */ |
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436 | unsigned short scc_rccr; /* receive control character register */ |
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437 | unsigned short scc_rlbc; /* receive last break character */ |
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438 | } scc_uart_t; |
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439 | |
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440 | /* SCC Event and Mask registers when it is used as a UART. |
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441 | */ |
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442 | #define UART_SCCM_GLR ((unsigned short)0x1000) |
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443 | #define UART_SCCM_GLT ((unsigned short)0x0800) |
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444 | #define UART_SCCM_AB ((unsigned short)0x0200) |
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445 | #define UART_SCCM_IDL ((unsigned short)0x0100) |
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446 | #define UART_SCCM_GRA ((unsigned short)0x0080) |
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447 | #define UART_SCCM_BRKE ((unsigned short)0x0040) |
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448 | #define UART_SCCM_BRKS ((unsigned short)0x0020) |
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449 | #define UART_SCCM_CCR ((unsigned short)0x0008) |
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450 | #define UART_SCCM_BSY ((unsigned short)0x0004) |
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451 | #define UART_SCCM_TX ((unsigned short)0x0002) |
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452 | #define UART_SCCM_RX ((unsigned short)0x0001) |
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453 | |
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454 | /* The SCC PMSR when used as a UART. |
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455 | */ |
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456 | #define SCU_PMSR_FLC ((unsigned short)0x8000) |
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457 | #define SCU_PMSR_SL ((unsigned short)0x4000) |
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458 | #define SCU_PMSR_CL ((unsigned short)0x3000) |
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459 | #define SCU_PMSR_UM ((unsigned short)0x0c00) |
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460 | #define SCU_PMSR_FRZ ((unsigned short)0x0200) |
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461 | #define SCU_PMSR_RZS ((unsigned short)0x0100) |
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462 | #define SCU_PMSR_SYN ((unsigned short)0x0080) |
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463 | #define SCU_PMSR_DRT ((unsigned short)0x0040) |
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464 | #define SCU_PMSR_PEN ((unsigned short)0x0010) |
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465 | #define SCU_PMSR_RPM ((unsigned short)0x000c) |
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466 | #define SCU_PMSR_REVP ((unsigned short)0x0008) |
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467 | #define SCU_PMSR_TPM ((unsigned short)0x0003) |
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468 | #define SCU_PMSR_TEVP ((unsigned short)0x0003) |
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469 | |
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470 | /* CPM Transparent mode SCC. |
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471 | */ |
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472 | typedef struct scc_trans { |
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473 | sccp_t st_genscc; |
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474 | unsigned int st_cpres; /* Preset CRC */ |
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475 | unsigned int st_cmask; /* Constant mask for CRC */ |
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476 | } scc_trans_t; |
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477 | |
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478 | /* CPM interrupts. There are nearly 32 interrupts generated by CPM |
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479 | * channels or devices. All of these are presented to the PPC core |
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480 | * as a single interrupt. The CPM interrupt handler dispatches its |
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481 | * own handlers, in a similar fashion to the PPC core handler. We |
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482 | * use the table as defined in the manuals (i.e. no special high |
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483 | * priority and SCC1 == SCCa, etc...). |
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484 | */ |
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485 | #define CPMVEC_NR 32 |
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486 | #define CPMVEC_PIO_PC15 ((unsigned short)0x1f) |
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487 | #define CPMVEC_SCC1 ((unsigned short)0x1e) |
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488 | #define CPMVEC_SCC2 ((unsigned short)0x1d) |
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489 | #define CPMVEC_SCC3 ((unsigned short)0x1c) |
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490 | #define CPMVEC_SCC4 ((unsigned short)0x1b) |
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491 | #define CPMVEC_PIO_PC14 ((unsigned short)0x1a) |
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492 | #define CPMVEC_TIMER1 ((unsigned short)0x19) |
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493 | #define CPMVEC_PIO_PC13 ((unsigned short)0x18) |
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494 | #define CPMVEC_PIO_PC12 ((unsigned short)0x17) |
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495 | #define CPMVEC_SDMA_CB_ERR ((unsigned short)0x16) |
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496 | #define CPMVEC_IDMA1 ((unsigned short)0x15) |
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497 | #define CPMVEC_IDMA2 ((unsigned short)0x14) |
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498 | #define CPMVEC_TIMER2 ((unsigned short)0x12) |
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499 | #define CPMVEC_RISCTIMER ((unsigned short)0x11) |
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500 | #define CPMVEC_I2C ((unsigned short)0x10) |
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501 | #define CPMVEC_PIO_PC11 ((unsigned short)0x0f) |
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502 | #define CPMVEC_PIO_PC10 ((unsigned short)0x0e) |
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503 | #define CPMVEC_TIMER3 ((unsigned short)0x0c) |
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504 | #define CPMVEC_PIO_PC9 ((unsigned short)0x0b) |
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505 | #define CPMVEC_PIO_PC8 ((unsigned short)0x0a) |
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506 | #define CPMVEC_PIO_PC7 ((unsigned short)0x09) |
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507 | #define CPMVEC_TIMER4 ((unsigned short)0x07) |
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508 | #define CPMVEC_PIO_PC6 ((unsigned short)0x06) |
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509 | #define CPMVEC_SPI ((unsigned short)0x05) |
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510 | #define CPMVEC_SMC1 ((unsigned short)0x04) |
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511 | #define CPMVEC_SMC2 ((unsigned short)0x03) |
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512 | #define CPMVEC_PIO_PC5 ((unsigned short)0x02) |
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513 | #define CPMVEC_PIO_PC4 ((unsigned short)0x01) |
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514 | #define CPMVEC_ERROR ((unsigned short)0x00) |
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515 | |
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516 | extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); |
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517 | |
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518 | /* CPM interrupt configuration vector. |
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519 | */ |
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520 | #define CICR_SCD_SCC4 ((unsigned int)0x00c00000) /* SCC4 @ SCCd */ |
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521 | #define CICR_SCC_SCC3 ((unsigned int)0x00200000) /* SCC3 @ SCCc */ |
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522 | #define CICR_SCB_SCC2 ((unsigned int)0x00040000) /* SCC2 @ SCCb */ |
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523 | #define CICR_SCA_SCC1 ((unsigned int)0x00000000) /* SCC1 @ SCCa */ |
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524 | #define CICR_IRL_MASK ((unsigned int)0x0000e000) /* Core interrrupt */ |
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525 | #define CICR_HP_MASK ((unsigned int)0x00001f00) /* Hi-pri int. */ |
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526 | #define CICR_IEN ((unsigned int)0x00000080) /* Int. enable */ |
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527 | #define CICR_SPS ((unsigned int)0x00000001) /* SCC Spread */ |
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528 | #endif /* __CPM_8XX__ */ |
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