source: rtems/c/src/lib/libbsp/powerpc/mbx8xx/include/commproc.h @ b4a0a8d

4.104.114.84.9
Last change on this file since b4a0a8d was b4a0a8d, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 20, 2005 at 7:37:52 PM

2005-01-20 Joel Sherrill <joel@…>

  • include/commproc.h: The variable cpmp was not used anywhere but console.c and was static in console.c, so should not have been in this file as extern.
  • Property mode set to 100644
File size: 22.8 KB
Line 
1
2/*
3 * MPC8xx Communication Processor Module.
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 *
6 * This file contains structures and information for the communication
7 * processor channels.  Some CPM control and status is available
8 * throught the MPC8xx internal memory map.  See immap.h for details.
9 * This file only contains what I need for the moment, not the total
10 * CPM capabilities.  I (or someone else) will add definitions as they
11 * are needed.  -- Dan
12 *
13 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
14 * bytes of the DP RAM and relocates the I2C parameter area to the
15 * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
16 * or other use.
17 */
18#ifndef __CPM_8XX__
19#define __CPM_8XX__
20
21#include <bsp/8xx_immap.h>
22
23/* CPM Command register.
24*/
25#define CPM_CR_RST      ((unsigned short)0x8000)
26#define CPM_CR_OPCODE   ((unsigned short)0x0f00)
27#define CPM_CR_CHAN     ((unsigned short)0x00f0)
28#define CPM_CR_FLG      ((unsigned short)0x0001)
29
30/* Some commands (there are more...later)
31*/
32#define CPM_CR_INIT_TRX         ((unsigned short)0x0000)
33#define CPM_CR_INIT_RX          ((unsigned short)0x0001)
34#define CPM_CR_INIT_TX          ((unsigned short)0x0002)
35#define CPM_CR_STOP_TX          ((unsigned short)0x0004)
36#define CPM_CR_RESTART_TX       ((unsigned short)0x0006)
37#define CPM_CR_SET_GADDR        ((unsigned short)0x0008)
38
39/* Channel numbers.
40*/
41#define CPM_CR_CH_SCC1  ((unsigned short)0x0000)
42#define CPM_CR_CH_I2C   ((unsigned short)0x0001)        /* I2C and IDMA1 */
43#define CPM_CR_CH_SCC2  ((unsigned short)0x0004)
44#define CPM_CR_CH_SPI   ((unsigned short)0x0005)        /* SPI / IDMA2 / Timers */
45#define CPM_CR_CH_SCC3  ((unsigned short)0x0008)
46#define CPM_CR_CH_SMC1  ((unsigned short)0x0009)        /* SMC1 / DSP1 */
47#define CPM_CR_CH_SCC4  ((unsigned short)0x000c)
48#define CPM_CR_CH_SMC2  ((unsigned short)0x000d)        /* SMC2 / DSP2 */
49
50#define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
51
52/* The dual ported RAM is multi-functional.  Some areas can be (and are
53 * being) used for microcode.  There is an area that can only be used
54 * as data ram for buffer descriptors, which is all we use right now.
55 * Currently the first 512 and last 256 bytes are used for microcode.
56 */
57#define CPM_DATAONLY_BASE       ((unsigned int)0x0800)
58#define CPM_DATAONLY_SIZE       ((unsigned int)0x0700)
59#define CPM_DP_NOSPACE          ((unsigned int)0x7fffffff)
60
61/* Export the base address of the communication processor registers
62 * and dual port ram.
63 */
64unsigned int            m8xx_cpm_dpalloc(unsigned int size);
65unsigned int            m8xx_cpm_hostalloc(unsigned int size);
66void                    m8xx_cpm_setbrg(unsigned int brg, unsigned int rate);
67
68/* Buffer descriptors used by many of the CPM protocols.
69*/
70typedef struct cpm_buf_desc {
71        unsigned short  cbd_sc;         /* Status and Control */
72        unsigned short  cbd_datlen;     /* Data length in buffer */
73        unsigned int    cbd_bufaddr;    /* Buffer address in host memory */
74} cbd_t;
75
76#define BD_SC_EMPTY     ((unsigned short)0x8000)        /* Recieve is empty */
77#define BD_SC_READY     ((unsigned short)0x8000)        /* Transmit is ready */
78#define BD_SC_WRAP      ((unsigned short)0x2000)        /* Last buffer descriptor */
79#define BD_SC_INTRPT    ((unsigned short)0x1000)        /* Interrupt on change */
80#define BD_SC_CM        ((unsigned short)0x0200)        /* Continous mode */
81#define BD_SC_ID        ((unsigned short)0x0100)        /* Rec'd too many idles */
82#define BD_SC_P         ((unsigned short)0x0100)        /* xmt preamble */
83#define BD_SC_BR        ((unsigned short)0x0020)        /* Break received */
84#define BD_SC_FR        ((unsigned short)0x0010)        /* Framing error */
85#define BD_SC_PR        ((unsigned short)0x0008)        /* Parity error */
86#define BD_SC_OV        ((unsigned short)0x0002)        /* Overrun */
87#define BD_SC_CD        ((unsigned short)0x0001)        /* ?? */
88
89/* Parameter RAM offsets.
90*/
91#define PROFF_SCC1      ((unsigned int)0x0000)
92#define PROFF_SCC2      ((unsigned int)0x0100)
93#define PROFF_SCC3      ((unsigned int)0x0200)
94#define PROFF_SMC1      ((unsigned int)0x0280)
95#define PROFF_SCC4      ((unsigned int)0x0300)
96#define PROFF_SMC2      ((unsigned int)0x0380)
97
98/* Define enough so I can at least use the serial port as a UART.
99 */
100typedef struct smc_uart {
101        unsigned short  smc_rbase;      /* Rx Buffer descriptor base address */
102        unsigned short  smc_tbase;      /* Tx Buffer descriptor base address */
103        unsigned char   smc_rfcr;       /* Rx function code */
104        unsigned char   smc_tfcr;       /* Tx function code */
105        unsigned short  smc_mrblr;      /* Max receive buffer length */
106        unsigned int    smc_rstate;     /* Internal */
107        unsigned int    smc_idp;        /* Internal */
108        unsigned short  smc_rbptr;      /* Internal */
109        unsigned short  smc_ibc;        /* Internal */
110        unsigned int    smc_rxtmp;      /* Internal */
111        unsigned int    smc_tstate;     /* Internal */
112        unsigned int    smc_tdp;        /* Internal */
113        unsigned short  smc_tbptr;      /* Internal */
114        unsigned short  smc_tbc;        /* Internal */
115        unsigned int    smc_txtmp;      /* Internal */
116        unsigned short  smc_maxidl;     /* Maximum idle characters */
117        unsigned short  smc_tmpidl;     /* Temporary idle counter */
118        unsigned short  smc_brklen;     /* Last received break length */
119        unsigned short  smc_brkec;      /* rcv'd break condition counter */
120        unsigned short  smc_brkcr;      /* xmt break count register */
121        unsigned short  smc_rmask;      /* Temporary bit mask */
122} smc_uart_t;
123
124/* Function code bits.
125*/
126#define SMC_EB  ((unsigned char)0x10)   /* Set big endian byte order */
127
128/* SMC uart mode register.
129*/
130#define SMCMR_REN       ((unsigned short)0x0001)
131#define SMCMR_TEN       ((unsigned short)0x0002)
132#define SMCMR_DM        ((unsigned short)0x000c)
133#define SMCMR_SM_GCI    ((unsigned short)0x0000)
134#define SMCMR_SM_UART   ((unsigned short)0x0020)
135#define SMCMR_SM_TRANS  ((unsigned short)0x0030)
136#define SMCMR_SM_MASK   ((unsigned short)0x0030)
137#define SMCMR_PM_EVEN   ((unsigned short)0x0100)        /* Even parity, else odd */
138#define SMCMR_PEN       ((unsigned short)0x0200)        /* Parity enable */
139#define SMCMR_SL        ((unsigned short)0x0400)        /* Two stops, else one */
140#define SMCR_CLEN_MASK  ((unsigned short)0x7800)        /* Character length */
141#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
142
143/* SMC Event and Mask register.
144*/
145#define SMCM_TXE        ((unsigned char)0x10)
146#define SMCM_BSY        ((unsigned char)0x04)
147#define SMCM_TX         ((unsigned char)0x02)
148#define SMCM_RX         ((unsigned char)0x01)
149
150/* Baud rate generators.
151*/
152#define CPM_BRG_RST             ((unsigned int)0x00020000)
153#define CPM_BRG_EN              ((unsigned int)0x00010000)
154#define CPM_BRG_EXTC_INT        ((unsigned int)0x00000000)
155#define CPM_BRG_EXTC_CLK2       ((unsigned int)0x00004000)
156#define CPM_BRG_EXTC_CLK6       ((unsigned int)0x00008000)
157#define CPM_BRG_ATB             ((unsigned int)0x00002000)
158#define CPM_BRG_CD_MASK         ((unsigned int)0x00001ffe)
159#define CPM_BRG_DIV16           ((unsigned int)0x00000001)
160
161/* SCCs.
162*/
163#define SCC_GSMRH_IRP           ((unsigned int)0x00040000)
164#define SCC_GSMRH_GDE           ((unsigned int)0x00010000)
165#define SCC_GSMRH_TCRC_CCITT    ((unsigned int)0x00008000)
166#define SCC_GSMRH_TCRC_BISYNC   ((unsigned int)0x00004000)
167#define SCC_GSMRH_TCRC_HDLC     ((unsigned int)0x00000000)
168#define SCC_GSMRH_REVD          ((unsigned int)0x00002000)
169#define SCC_GSMRH_TRX           ((unsigned int)0x00001000)
170#define SCC_GSMRH_TTX           ((unsigned int)0x00000800)
171#define SCC_GSMRH_CDP           ((unsigned int)0x00000400)
172#define SCC_GSMRH_CTSP          ((unsigned int)0x00000200)
173#define SCC_GSMRH_CDS           ((unsigned int)0x00000100)
174#define SCC_GSMRH_CTSS          ((unsigned int)0x00000080)
175#define SCC_GSMRH_TFL           ((unsigned int)0x00000040)
176#define SCC_GSMRH_RFW           ((unsigned int)0x00000020)
177#define SCC_GSMRH_TXSY          ((unsigned int)0x00000010)
178#define SCC_GSMRH_SYNL16        ((unsigned int)0x0000000c)
179#define SCC_GSMRH_SYNL8         ((unsigned int)0x00000008)
180#define SCC_GSMRH_SYNL4         ((unsigned int)0x00000004)
181#define SCC_GSMRH_RTSM          ((unsigned int)0x00000002)
182#define SCC_GSMRH_RSYN          ((unsigned int)0x00000001)
183
184#define SCC_GSMRL_SIR           ((unsigned int)0x80000000)      /* SCC2 only */
185#define SCC_GSMRL_EDGE_NONE     ((unsigned int)0x60000000)
186#define SCC_GSMRL_EDGE_NEG      ((unsigned int)0x40000000)
187#define SCC_GSMRL_EDGE_POS      ((unsigned int)0x20000000)
188#define SCC_GSMRL_EDGE_BOTH     ((unsigned int)0x00000000)
189#define SCC_GSMRL_TCI           ((unsigned int)0x10000000)
190#define SCC_GSMRL_TSNC_3        ((unsigned int)0x0c000000)
191#define SCC_GSMRL_TSNC_4        ((unsigned int)0x08000000)
192#define SCC_GSMRL_TSNC_14       ((unsigned int)0x04000000)
193#define SCC_GSMRL_TSNC_INF      ((unsigned int)0x00000000)
194#define SCC_GSMRL_RINV          ((unsigned int)0x02000000)
195#define SCC_GSMRL_TINV          ((unsigned int)0x01000000)
196#define SCC_GSMRL_TPL_128       ((unsigned int)0x00c00000)
197#define SCC_GSMRL_TPL_64        ((unsigned int)0x00a00000)
198#define SCC_GSMRL_TPL_48        ((unsigned int)0x00800000)
199#define SCC_GSMRL_TPL_32        ((unsigned int)0x00600000)
200#define SCC_GSMRL_TPL_16        ((unsigned int)0x00400000)
201#define SCC_GSMRL_TPL_8         ((unsigned int)0x00200000)
202#define SCC_GSMRL_TPL_NONE      ((unsigned int)0x00000000)
203#define SCC_GSMRL_TPP_ALL1      ((unsigned int)0x00180000)
204#define SCC_GSMRL_TPP_01        ((unsigned int)0x00100000)
205#define SCC_GSMRL_TPP_10        ((unsigned int)0x00080000)
206#define SCC_GSMRL_TPP_ZEROS     ((unsigned int)0x00000000)
207#define SCC_GSMRL_TEND          ((unsigned int)0x00040000)
208#define SCC_GSMRL_TDCR_32       ((unsigned int)0x00030000)
209#define SCC_GSMRL_TDCR_16       ((unsigned int)0x00020000)
210#define SCC_GSMRL_TDCR_8        ((unsigned int)0x00010000)
211#define SCC_GSMRL_TDCR_1        ((unsigned int)0x00000000)
212#define SCC_GSMRL_RDCR_32       ((unsigned int)0x0000c000)
213#define SCC_GSMRL_RDCR_16       ((unsigned int)0x00008000)
214#define SCC_GSMRL_RDCR_8        ((unsigned int)0x00004000)
215#define SCC_GSMRL_RDCR_1        ((unsigned int)0x00000000)
216#define SCC_GSMRL_RENC_DFMAN    ((unsigned int)0x00003000)
217#define SCC_GSMRL_RENC_MANCH    ((unsigned int)0x00002000)
218#define SCC_GSMRL_RENC_FM0      ((unsigned int)0x00001000)
219#define SCC_GSMRL_RENC_NRZI     ((unsigned int)0x00000800)
220#define SCC_GSMRL_RENC_NRZ      ((unsigned int)0x00000000)
221#define SCC_GSMRL_TENC_DFMAN    ((unsigned int)0x00000600)
222#define SCC_GSMRL_TENC_MANCH    ((unsigned int)0x00000400)
223#define SCC_GSMRL_TENC_FM0      ((unsigned int)0x00000200)
224#define SCC_GSMRL_TENC_NRZI     ((unsigned int)0x00000100)
225#define SCC_GSMRL_TENC_NRZ      ((unsigned int)0x00000000)
226#define SCC_GSMRL_DIAG_LE       ((unsigned int)0x000000c0)      /* Loop and echo */
227#define SCC_GSMRL_DIAG_ECHO     ((unsigned int)0x00000080)
228#define SCC_GSMRL_DIAG_LOOP     ((unsigned int)0x00000040)
229#define SCC_GSMRL_DIAG_NORM     ((unsigned int)0x00000000)
230#define SCC_GSMRL_ENR           ((unsigned int)0x00000020)
231#define SCC_GSMRL_ENT           ((unsigned int)0x00000010)
232#define SCC_GSMRL_MODE_ENET     ((unsigned int)0x0000000c)
233#define SCC_GSMRL_MODE_DDCMP    ((unsigned int)0x00000009)
234#define SCC_GSMRL_MODE_BISYNC   ((unsigned int)0x00000008)
235#define SCC_GSMRL_MODE_V14      ((unsigned int)0x00000007)
236#define SCC_GSMRL_MODE_AHDLC    ((unsigned int)0x00000006)
237#define SCC_GSMRL_MODE_PROFIBUS ((unsigned int)0x00000005)
238#define SCC_GSMRL_MODE_UART     ((unsigned int)0x00000004)
239#define SCC_GSMRL_MODE_SS7      ((unsigned int)0x00000003)
240#define SCC_GSMRL_MODE_ATALK    ((unsigned int)0x00000002)
241#define SCC_GSMRL_MODE_HDLC     ((unsigned int)0x00000000)
242
243#define SCC_TODR_TOD            ((unsigned short)0x8000)
244
245/* SCC Event and Mask register.
246*/
247#define SCCM_TXE        ((unsigned char)0x10)
248#define SCCM_BSY        ((unsigned char)0x04)
249#define SCCM_TX         ((unsigned char)0x02)
250#define SCCM_RX         ((unsigned char)0x01)
251
252typedef struct scc_param {
253        unsigned short  scc_rbase;      /* Rx Buffer descriptor base address */
254        unsigned short  scc_tbase;      /* Tx Buffer descriptor base address */
255        unsigned char   scc_rfcr;       /* Rx function code */
256        unsigned char   scc_tfcr;       /* Tx function code */
257        unsigned short  scc_mrblr;      /* Max receive buffer length */
258        unsigned int    scc_rstate;     /* Internal */
259        unsigned int    scc_idp;        /* Internal */
260        unsigned short  scc_rbptr;      /* Internal */
261        unsigned short  scc_ibc;        /* Internal */
262        unsigned int    scc_rxtmp;      /* Internal */
263        unsigned int    scc_tstate;     /* Internal */
264        unsigned int    scc_tdp;        /* Internal */
265        unsigned short  scc_tbptr;      /* Internal */
266        unsigned short  scc_tbc;        /* Internal */
267        unsigned int    scc_txtmp;      /* Internal */
268        unsigned int    scc_rcrc;       /* Internal */
269        unsigned int    scc_tcrc;       /* Internal */
270} sccp_t;
271
272/* Function code bits.
273*/
274#define SCC_EB  ((unsigned char)0x10)   /* Set big endian byte order */
275
276/* CPM Ethernet through SCC1.
277 */
278typedef struct scc_enet {
279        sccp_t  sen_genscc;
280        unsigned int    sen_cpres;      /* Preset CRC */
281        unsigned int    sen_cmask;      /* Constant mask for CRC */
282        unsigned int    sen_crcec;      /* CRC Error counter */
283        unsigned int    sen_alec;       /* alignment error counter */
284        unsigned int    sen_disfc;      /* discard frame counter */
285        unsigned short  sen_pads;       /* Tx short frame pad character */
286        unsigned short  sen_retlim;     /* Retry limit threshold */
287        unsigned short  sen_retcnt;     /* Retry limit counter */
288        unsigned short  sen_maxflr;     /* maximum frame length register */
289        unsigned short  sen_minflr;     /* minimum frame length register */
290        unsigned short  sen_maxd1;      /* maximum DMA1 length */
291        unsigned short  sen_maxd2;      /* maximum DMA2 length */
292        unsigned short  sen_maxd;       /* Rx max DMA */
293        unsigned short  sen_dmacnt;     /* Rx DMA counter */
294        unsigned short  sen_maxb;       /* Max BD byte count */
295        unsigned short  sen_gaddr1;     /* Group address filter */
296        unsigned short  sen_gaddr2;
297        unsigned short  sen_gaddr3;
298        unsigned short  sen_gaddr4;
299        unsigned int    sen_tbuf0data0; /* Save area 0 - current frame */
300        unsigned int    sen_tbuf0data1; /* Save area 1 - current frame */
301        unsigned int    sen_tbuf0rba;   /* Internal */
302        unsigned int    sen_tbuf0crc;   /* Internal */
303        unsigned short  sen_tbuf0bcnt;  /* Internal */
304        unsigned short  sen_paddrh;     /* physical address (MSB) */
305        unsigned short  sen_paddrm;
306        unsigned short  sen_paddrl;     /* physical address (LSB) */
307        unsigned short  sen_pper;       /* persistence */
308        unsigned short  sen_rfbdptr;    /* Rx first BD pointer */
309        unsigned short  sen_tfbdptr;    /* Tx first BD pointer */
310        unsigned short  sen_tlbdptr;    /* Tx last BD pointer */
311        unsigned int    sen_tbuf1data0; /* Save area 0 - current frame */
312        unsigned int    sen_tbuf1data1; /* Save area 1 - current frame */
313        unsigned int    sen_tbuf1rba;   /* Internal */
314        unsigned int    sen_tbuf1crc;   /* Internal */
315        unsigned short  sen_tbuf1bcnt;  /* Internal */
316        unsigned short  sen_txlen;      /* Tx Frame length counter */
317        unsigned short  sen_iaddr1;     /* Individual address filter */
318        unsigned short  sen_iaddr2;
319        unsigned short  sen_iaddr3;
320        unsigned short  sen_iaddr4;
321        unsigned short  sen_boffcnt;    /* Backoff counter */
322
323        /* NOTE: Some versions of the manual have the following items
324         * incorrectly documented.  Below is the proper order.
325         */
326        unsigned short  sen_taddrh;     /* temp address (MSB) */
327        unsigned short  sen_taddrm;
328        unsigned short  sen_taddrl;     /* temp address (LSB) */
329} scc_enet_t;
330
331/* Bits in parallel I/O port registers that have to be set/cleared
332 * to configure the pins for SCC1 use.  The TCLK and RCLK seem unique
333 * to the MBX860 board.  Any two of the four available clocks could be
334 * used, and the MPC860 cookbook manual has an example using different
335 * clock pins.
336 */
337#define PA_ENET_RXD     ((unsigned short)0x0001)
338#define PA_ENET_TXD     ((unsigned short)0x0002)
339#define PA_ENET_TCLK    ((unsigned short)0x0200)
340#define PA_ENET_RCLK    ((unsigned short)0x0800)
341#define PC_ENET_TENA    ((unsigned short)0x0001)
342#define PC_ENET_CLSN    ((unsigned short)0x0010)
343#define PC_ENET_RENA    ((unsigned short)0x0020)
344
345/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
346 * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
347 */
348#define SICR_ENET_MASK  ((unsigned int)0x000000ff)
349#define SICR_ENET_CLKRT ((unsigned int)0x0000003d)
350
351/* SCC Event register as used by Ethernet.
352*/
353#define SCCE_ENET_GRA   ((unsigned short)0x0080)        /* Graceful stop complete */
354#define SCCE_ENET_TXE   ((unsigned short)0x0010)        /* Transmit Error */
355#define SCCE_ENET_RXF   ((unsigned short)0x0008)        /* Full frame received */
356#define SCCE_ENET_BSY   ((unsigned short)0x0004)        /* All incoming buffers full */
357#define SCCE_ENET_TXB   ((unsigned short)0x0002)        /* A buffer was transmitted */
358#define SCCE_ENET_RXB   ((unsigned short)0x0001)        /* A buffer was received */
359
360/* SCC Mode Register (PMSR) as used by Ethernet.
361*/
362#define SCC_PMSR_HBC    ((unsigned short)0x8000)        /* Enable heartbeat */
363#define SCC_PMSR_FC     ((unsigned short)0x4000)        /* Force collision */
364#define SCC_PMSR_RSH    ((unsigned short)0x2000)        /* Receive short frames */
365#define SCC_PMSR_IAM    ((unsigned short)0x1000)        /* Check individual hash */
366#define SCC_PMSR_ENCRC  ((unsigned short)0x0800)        /* Ethernet CRC mode */
367#define SCC_PMSR_PRO    ((unsigned short)0x0200)        /* Promiscuous mode */
368#define SCC_PMSR_BRO    ((unsigned short)0x0100)        /* Catch broadcast pkts */
369#define SCC_PMSR_SBT    ((unsigned short)0x0080)        /* Special backoff timer */
370#define SCC_PMSR_LPB    ((unsigned short)0x0040)        /* Set Loopback mode */
371#define SCC_PMSR_SIP    ((unsigned short)0x0020)        /* Sample Input Pins */
372#define SCC_PMSR_LCW    ((unsigned short)0x0010)        /* Late collision window */
373#define SCC_PMSR_NIB22  ((unsigned short)0x000a)        /* Start frame search */
374#define SCC_PMSR_FDE    ((unsigned short)0x0001)        /* Full duplex enable */
375
376/* Buffer descriptor control/status used by Ethernet receive.
377*/
378#define BD_ENET_RX_EMPTY        ((unsigned short)0x8000)
379#define BD_ENET_RX_WRAP         ((unsigned short)0x2000)
380#define BD_ENET_RX_INTR         ((unsigned short)0x1000)
381#define BD_ENET_RX_LAST         ((unsigned short)0x0800)
382#define BD_ENET_RX_FIRST        ((unsigned short)0x0400)
383#define BD_ENET_RX_MISS         ((unsigned short)0x0100)
384#define BD_ENET_RX_LG           ((unsigned short)0x0020)
385#define BD_ENET_RX_NO           ((unsigned short)0x0010)
386#define BD_ENET_RX_SH           ((unsigned short)0x0008)
387#define BD_ENET_RX_CR           ((unsigned short)0x0004)
388#define BD_ENET_RX_OV           ((unsigned short)0x0002)
389#define BD_ENET_RX_CL           ((unsigned short)0x0001)
390#define BD_ENET_RX_STATS        ((unsigned short)0x013f)        /* All status bits */
391
392/* Buffer descriptor control/status used by Ethernet transmit.
393*/
394#define BD_ENET_TX_READY        ((unsigned short)0x8000)
395#define BD_ENET_TX_PAD          ((unsigned short)0x4000)
396#define BD_ENET_TX_WRAP         ((unsigned short)0x2000)
397#define BD_ENET_TX_INTR         ((unsigned short)0x1000)
398#define BD_ENET_TX_LAST         ((unsigned short)0x0800)
399#define BD_ENET_TX_TC           ((unsigned short)0x0400)
400#define BD_ENET_TX_DEF          ((unsigned short)0x0200)
401#define BD_ENET_TX_HB           ((unsigned short)0x0100)
402#define BD_ENET_TX_LC           ((unsigned short)0x0080)
403#define BD_ENET_TX_RL           ((unsigned short)0x0040)
404#define BD_ENET_TX_RCMASK       ((unsigned short)0x003c)
405#define BD_ENET_TX_UN           ((unsigned short)0x0002)
406#define BD_ENET_TX_CSL          ((unsigned short)0x0001)
407#define BD_ENET_TX_STATS        ((unsigned short)0x03ff)        /* All status bits */
408
409/* SCC as UART
410*/
411typedef struct scc_uart {
412        sccp_t  scc_genscc;
413        unsigned int    scc_res1;       /* Reserved */
414        unsigned int    scc_res2;       /* Reserved */
415        unsigned short  scc_maxidl;     /* Maximum idle chars */
416        unsigned short  scc_idlc;       /* temp idle counter */
417        unsigned short  scc_brkcr;      /* Break count register */
418        unsigned short  scc_parec;      /* receive parity error counter */
419        unsigned short  scc_frmec;      /* receive framing error counter */
420        unsigned short  scc_nosec;      /* receive noise counter */
421        unsigned short  scc_brkec;      /* receive break condition counter */
422        unsigned short  scc_brkln;      /* last received break length */
423        unsigned short  scc_uaddr1;     /* UART address character 1 */
424        unsigned short  scc_uaddr2;     /* UART address character 2 */
425        unsigned short  scc_rtemp;      /* Temp storage */
426        unsigned short  scc_toseq;      /* Transmit out of sequence char */
427        unsigned short  scc_char1;      /* control character 1 */
428        unsigned short  scc_char2;      /* control character 2 */
429        unsigned short  scc_char3;      /* control character 3 */
430        unsigned short  scc_char4;      /* control character 4 */
431        unsigned short  scc_char5;      /* control character 5 */
432        unsigned short  scc_char6;      /* control character 6 */
433        unsigned short  scc_char7;      /* control character 7 */
434        unsigned short  scc_char8;      /* control character 8 */
435        unsigned short  scc_rccm;       /* receive control character mask */
436        unsigned short  scc_rccr;       /* receive control character register */
437        unsigned short  scc_rlbc;       /* receive last break character */
438} scc_uart_t;
439
440/* SCC Event and Mask registers when it is used as a UART.
441*/
442#define UART_SCCM_GLR           ((unsigned short)0x1000)
443#define UART_SCCM_GLT           ((unsigned short)0x0800)
444#define UART_SCCM_AB            ((unsigned short)0x0200)
445#define UART_SCCM_IDL           ((unsigned short)0x0100)
446#define UART_SCCM_GRA           ((unsigned short)0x0080)
447#define UART_SCCM_BRKE          ((unsigned short)0x0040)
448#define UART_SCCM_BRKS          ((unsigned short)0x0020)
449#define UART_SCCM_CCR           ((unsigned short)0x0008)
450#define UART_SCCM_BSY           ((unsigned short)0x0004)
451#define UART_SCCM_TX            ((unsigned short)0x0002)
452#define UART_SCCM_RX            ((unsigned short)0x0001)
453
454/* The SCC PMSR when used as a UART.
455*/
456#define SCU_PMSR_FLC            ((unsigned short)0x8000)
457#define SCU_PMSR_SL             ((unsigned short)0x4000)
458#define SCU_PMSR_CL             ((unsigned short)0x3000)
459#define SCU_PMSR_UM             ((unsigned short)0x0c00)
460#define SCU_PMSR_FRZ            ((unsigned short)0x0200)
461#define SCU_PMSR_RZS            ((unsigned short)0x0100)
462#define SCU_PMSR_SYN            ((unsigned short)0x0080)
463#define SCU_PMSR_DRT            ((unsigned short)0x0040)
464#define SCU_PMSR_PEN            ((unsigned short)0x0010)
465#define SCU_PMSR_RPM            ((unsigned short)0x000c)
466#define SCU_PMSR_REVP           ((unsigned short)0x0008)
467#define SCU_PMSR_TPM            ((unsigned short)0x0003)
468#define SCU_PMSR_TEVP           ((unsigned short)0x0003)
469
470/* CPM Transparent mode SCC.
471 */
472typedef struct scc_trans {
473        sccp_t  st_genscc;
474        unsigned int    st_cpres;       /* Preset CRC */
475        unsigned int    st_cmask;       /* Constant mask for CRC */
476} scc_trans_t;
477
478/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
479 * channels or devices.  All of these are presented to the PPC core
480 * as a single interrupt.  The CPM interrupt handler dispatches its
481 * own handlers, in a similar fashion to the PPC core handler.  We
482 * use the table as defined in the manuals (i.e. no special high
483 * priority and SCC1 == SCCa, etc...).
484 */
485#define CPMVEC_NR               32
486#define CPMVEC_PIO_PC15         ((unsigned short)0x1f)
487#define CPMVEC_SCC1             ((unsigned short)0x1e)
488#define CPMVEC_SCC2             ((unsigned short)0x1d)
489#define CPMVEC_SCC3             ((unsigned short)0x1c)
490#define CPMVEC_SCC4             ((unsigned short)0x1b)
491#define CPMVEC_PIO_PC14         ((unsigned short)0x1a)
492#define CPMVEC_TIMER1           ((unsigned short)0x19)
493#define CPMVEC_PIO_PC13         ((unsigned short)0x18)
494#define CPMVEC_PIO_PC12         ((unsigned short)0x17)
495#define CPMVEC_SDMA_CB_ERR      ((unsigned short)0x16)
496#define CPMVEC_IDMA1            ((unsigned short)0x15)
497#define CPMVEC_IDMA2            ((unsigned short)0x14)
498#define CPMVEC_TIMER2           ((unsigned short)0x12)
499#define CPMVEC_RISCTIMER        ((unsigned short)0x11)
500#define CPMVEC_I2C              ((unsigned short)0x10)
501#define CPMVEC_PIO_PC11         ((unsigned short)0x0f)
502#define CPMVEC_PIO_PC10         ((unsigned short)0x0e)
503#define CPMVEC_TIMER3           ((unsigned short)0x0c)
504#define CPMVEC_PIO_PC9          ((unsigned short)0x0b)
505#define CPMVEC_PIO_PC8          ((unsigned short)0x0a)
506#define CPMVEC_PIO_PC7          ((unsigned short)0x09)
507#define CPMVEC_TIMER4           ((unsigned short)0x07)
508#define CPMVEC_PIO_PC6          ((unsigned short)0x06)
509#define CPMVEC_SPI              ((unsigned short)0x05)
510#define CPMVEC_SMC1             ((unsigned short)0x04)
511#define CPMVEC_SMC2             ((unsigned short)0x03)
512#define CPMVEC_PIO_PC5          ((unsigned short)0x02)
513#define CPMVEC_PIO_PC4          ((unsigned short)0x01)
514#define CPMVEC_ERROR            ((unsigned short)0x00)
515
516extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
517
518/* CPM interrupt configuration vector.
519*/
520#define CICR_SCD_SCC4           ((unsigned int)0x00c00000)      /* SCC4 @ SCCd */
521#define CICR_SCC_SCC3           ((unsigned int)0x00200000)      /* SCC3 @ SCCc */
522#define CICR_SCB_SCC2           ((unsigned int)0x00040000)      /* SCC2 @ SCCb */
523#define CICR_SCA_SCC1           ((unsigned int)0x00000000)      /* SCC1 @ SCCa */
524#define CICR_IRL_MASK           ((unsigned int)0x0000e000)      /* Core interrrupt */
525#define CICR_HP_MASK            ((unsigned int)0x00001f00)      /* Hi-pri int. */
526#define CICR_IEN                ((unsigned int)0x00000080)      /* Int. enable */
527#define CICR_SPS                ((unsigned int)0x00000001)      /* SCC Spread */
528#endif /* __CPM_8XX__ */
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