1 | |
---|
2 | /* |
---|
3 | * MPC8xx Internal Memory Map |
---|
4 | * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) |
---|
5 | * |
---|
6 | * The I/O on the MPC860 is comprised of blocks of special registers |
---|
7 | * and the dual port ram for the Communication Processor Module. |
---|
8 | * Within this space are functional units such as the SIU, memory |
---|
9 | * controller, system timers, and other control functions. It is |
---|
10 | * a combination that I found difficult to separate into logical |
---|
11 | * functional files.....but anyone else is welcome to try. -- Dan |
---|
12 | */ |
---|
13 | #ifndef __IMMAP_8XX__ |
---|
14 | #define __IMMAP_8XX__ |
---|
15 | |
---|
16 | /* System configuration registers. |
---|
17 | */ |
---|
18 | typedef struct sys_conf { |
---|
19 | unsigned int sc_siumcr; |
---|
20 | unsigned int sc_sypcr; |
---|
21 | unsigned int sc_swt; |
---|
22 | char res1[2]; |
---|
23 | unsigned short sc_swsr; |
---|
24 | unsigned int sc_sipend; |
---|
25 | unsigned int sc_simask; |
---|
26 | unsigned int sc_siel; |
---|
27 | unsigned int sc_sivec; |
---|
28 | unsigned int sc_tesr; |
---|
29 | char res2[0xc]; |
---|
30 | unsigned int sc_sdcr; |
---|
31 | char res3[0x4c]; |
---|
32 | } sysconf8xx_t; |
---|
33 | |
---|
34 | /* PCMCIA configuration registers. |
---|
35 | */ |
---|
36 | typedef struct pcmcia_conf { |
---|
37 | unsigned int pcmc_pbr0; |
---|
38 | unsigned int pcmc_por0; |
---|
39 | unsigned int pcmc_pbr1; |
---|
40 | unsigned int pcmc_por1; |
---|
41 | unsigned int pcmc_pbr2; |
---|
42 | unsigned int pcmc_por2; |
---|
43 | unsigned int pcmc_pbr3; |
---|
44 | unsigned int pcmc_por3; |
---|
45 | unsigned int pcmc_pbr4; |
---|
46 | unsigned int pcmc_por4; |
---|
47 | unsigned int pcmc_pbr5; |
---|
48 | unsigned int pcmc_por5; |
---|
49 | unsigned int pcmc_pbr6; |
---|
50 | unsigned int pcmc_por6; |
---|
51 | unsigned int pcmc_pbr7; |
---|
52 | unsigned int pcmc_por7; |
---|
53 | char res1[0x20]; |
---|
54 | unsigned int pcmc_pgcra; |
---|
55 | unsigned int pcmc_pgcrb; |
---|
56 | unsigned int pcmc_pscr; |
---|
57 | char res2[4]; |
---|
58 | unsigned int pcmc_pipr; |
---|
59 | char res3[4]; |
---|
60 | unsigned int pcmc_per; |
---|
61 | char res4[4]; |
---|
62 | } pcmconf8xx_t; |
---|
63 | |
---|
64 | /* Memory controller registers. |
---|
65 | */ |
---|
66 | typedef struct mem_ctlr { |
---|
67 | unsigned int memc_br0; |
---|
68 | unsigned int memc_or0; |
---|
69 | unsigned int memc_br1; |
---|
70 | unsigned int memc_or1; |
---|
71 | unsigned int memc_br2; |
---|
72 | unsigned int memc_or2; |
---|
73 | unsigned int memc_br3; |
---|
74 | unsigned int memc_or3; |
---|
75 | unsigned int memc_br4; |
---|
76 | unsigned int memc_or4; |
---|
77 | unsigned int memc_br5; |
---|
78 | unsigned int memc_or5; |
---|
79 | unsigned int memc_br6; |
---|
80 | unsigned int memc_or6; |
---|
81 | unsigned int memc_br7; |
---|
82 | unsigned int memc_or7; |
---|
83 | char res1[0x24]; |
---|
84 | unsigned int memc_mar; |
---|
85 | unsigned int memc_mcr; |
---|
86 | char res2[4]; |
---|
87 | unsigned int memc_mamr; |
---|
88 | unsigned int memc_mbmr; |
---|
89 | unsigned short memc_mstat; |
---|
90 | unsigned short memc_mptpr; |
---|
91 | unsigned int memc_mdr; |
---|
92 | char res3[0x80]; |
---|
93 | } memctl8xx_t; |
---|
94 | |
---|
95 | /* System Integration Timers. |
---|
96 | */ |
---|
97 | typedef struct sys_int_timers { |
---|
98 | unsigned short sit_tbscr; |
---|
99 | unsigned int sit_tbreff0; |
---|
100 | unsigned int sit_tbreff1; |
---|
101 | char res1[0x14]; |
---|
102 | unsigned short sit_rtcsc; |
---|
103 | unsigned int sit_rtc; |
---|
104 | unsigned int sit_rtsec; |
---|
105 | unsigned int sit_rtcal; |
---|
106 | char res2[0x10]; |
---|
107 | unsigned short sit_piscr; |
---|
108 | char res3[2]; |
---|
109 | unsigned int sit_pitc; |
---|
110 | unsigned int sit_pitr; |
---|
111 | char res4[0x34]; |
---|
112 | } sit8xx_t; |
---|
113 | |
---|
114 | #define TBSCR_TBIRQ_MASK ((unsigned short)0xff00) |
---|
115 | #define TBSCR_REFA ((unsigned short)0x0080) |
---|
116 | #define TBSCR_REFB ((unsigned short)0x0040) |
---|
117 | #define TBSCR_REFAE ((unsigned short)0x0008) |
---|
118 | #define TBSCR_REFBE ((unsigned short)0x0004) |
---|
119 | #define TBSCR_TBF ((unsigned short)0x0002) |
---|
120 | #define TBSCR_TBE ((unsigned short)0x0001) |
---|
121 | |
---|
122 | #define RTCSC_RTCIRQ_MASK ((unsigned short)0xff00) |
---|
123 | #define RTCSC_SEC ((unsigned short)0x0080) |
---|
124 | #define RTCSC_ALR ((unsigned short)0x0040) |
---|
125 | #define RTCSC_38K ((unsigned short)0x0010) |
---|
126 | #define RTCSC_SIE ((unsigned short)0x0008) |
---|
127 | #define RTCSC_ALE ((unsigned short)0x0004) |
---|
128 | #define RTCSC_RTF ((unsigned short)0x0002) |
---|
129 | #define RTCSC_RTE ((unsigned short)0x0001) |
---|
130 | |
---|
131 | #define PISCR_PIRQ_MASK ((unsigned short)0xff00) |
---|
132 | #define PISCR_PS ((unsigned short)0x0080) |
---|
133 | #define PISCR_PIE ((unsigned short)0x0004) |
---|
134 | #define PISCR_PTF ((unsigned short)0x0002) |
---|
135 | #define PISCR_PTE ((unsigned short)0x0001) |
---|
136 | |
---|
137 | /* Clocks and Reset. |
---|
138 | */ |
---|
139 | typedef struct clk_and_reset { |
---|
140 | unsigned int car_sccr; |
---|
141 | unsigned int car_plprcr; |
---|
142 | unsigned int car_rsr; |
---|
143 | char res[0x74]; /* Reserved area */ |
---|
144 | } car8xx_t; |
---|
145 | |
---|
146 | /* System Integration Timers keys. |
---|
147 | */ |
---|
148 | typedef struct sitk { |
---|
149 | unsigned int sitk_tbscrk; |
---|
150 | unsigned int sitk_tbreff0k; |
---|
151 | unsigned int sitk_tbreff1k; |
---|
152 | unsigned int sitk_tbk; |
---|
153 | char res1[0x10]; |
---|
154 | unsigned int sitk_rtcsck; |
---|
155 | unsigned int sitk_rtck; |
---|
156 | unsigned int sitk_rtseck; |
---|
157 | unsigned int sitk_rtcalk; |
---|
158 | char res2[0x10]; |
---|
159 | unsigned int sitk_piscrk; |
---|
160 | unsigned int sitk_pitck; |
---|
161 | char res3[0x38]; |
---|
162 | } sitk8xx_t; |
---|
163 | |
---|
164 | /* Clocks and reset keys. |
---|
165 | */ |
---|
166 | typedef struct cark { |
---|
167 | unsigned int cark_sccrk; |
---|
168 | unsigned int cark_plprcrk; |
---|
169 | unsigned int cark_rsrk; |
---|
170 | char res[0x474]; |
---|
171 | } cark8xx_t; |
---|
172 | |
---|
173 | /* The key to unlock registers maintained by keep-alive power. |
---|
174 | */ |
---|
175 | #define KAPWR_KEY ((unsigned int)0x55ccaa33) |
---|
176 | |
---|
177 | /* LCD interface. MPC821 Only. |
---|
178 | */ |
---|
179 | typedef struct lcd { |
---|
180 | unsigned short lcd_lcolr[16]; |
---|
181 | char res[0x20]; |
---|
182 | unsigned int lcd_lccr; |
---|
183 | unsigned int lcd_lchcr; |
---|
184 | unsigned int lcd_lcvcr; |
---|
185 | char res2[4]; |
---|
186 | unsigned int lcd_lcfaa; |
---|
187 | unsigned int lcd_lcfba; |
---|
188 | char lcd_lcsr; |
---|
189 | char res3[0x7]; |
---|
190 | } lcd8xx_t; |
---|
191 | |
---|
192 | /* I2C |
---|
193 | */ |
---|
194 | typedef struct i2c { |
---|
195 | unsigned char i2c_i2mod; |
---|
196 | char res1[3]; |
---|
197 | unsigned char i2c_i2add; |
---|
198 | char res2[3]; |
---|
199 | unsigned char i2c_i2brg; |
---|
200 | char res3[3]; |
---|
201 | unsigned char i2c_i2com; |
---|
202 | char res4[3]; |
---|
203 | unsigned char i2c_i2cer; |
---|
204 | char res5[3]; |
---|
205 | unsigned char i2c_i2cmr; |
---|
206 | char res6[0x8b]; |
---|
207 | } i2c8xx_t; |
---|
208 | |
---|
209 | /* DMA control/status registers. |
---|
210 | */ |
---|
211 | typedef struct sdma_csr { |
---|
212 | char res1[4]; |
---|
213 | unsigned int sdma_sdar; |
---|
214 | unsigned char sdma_sdsr; |
---|
215 | char res3[3]; |
---|
216 | unsigned char sdma_sdmr; |
---|
217 | char res4[3]; |
---|
218 | unsigned char sdma_idsr1; |
---|
219 | char res5[3]; |
---|
220 | unsigned char sdma_idmr1; |
---|
221 | char res6[3]; |
---|
222 | unsigned char sdma_idsr2; |
---|
223 | char res7[3]; |
---|
224 | unsigned char sdma_idmr2; |
---|
225 | char res8[0x13]; |
---|
226 | } sdma8xx_t; |
---|
227 | |
---|
228 | /* Communication Processor Module Interrupt Controller. |
---|
229 | */ |
---|
230 | typedef struct cpm_ic { |
---|
231 | unsigned short cpic_civr; |
---|
232 | char res[0xe]; |
---|
233 | unsigned int cpic_cicr; |
---|
234 | unsigned int cpic_cipr; |
---|
235 | unsigned int cpic_cimr; |
---|
236 | unsigned int cpic_cisr; |
---|
237 | } cpic8xx_t; |
---|
238 | |
---|
239 | /* Input/Output Port control/status registers. |
---|
240 | */ |
---|
241 | typedef struct io_port { |
---|
242 | unsigned short iop_padir; |
---|
243 | unsigned short iop_papar; |
---|
244 | unsigned short iop_paodr; |
---|
245 | unsigned short iop_padat; |
---|
246 | char res1[8]; |
---|
247 | unsigned short iop_pcdir; |
---|
248 | unsigned short iop_pcpar; |
---|
249 | unsigned short iop_pcso; |
---|
250 | unsigned short iop_pcdat; |
---|
251 | unsigned short iop_pcint; |
---|
252 | char res2[6]; |
---|
253 | unsigned short iop_pddir; |
---|
254 | unsigned short iop_pdpar; |
---|
255 | char res3[2]; |
---|
256 | unsigned short iop_pddat; |
---|
257 | char res4[8]; |
---|
258 | } iop8xx_t; |
---|
259 | |
---|
260 | /* Communication Processor Module Timers |
---|
261 | */ |
---|
262 | typedef struct cpm_timers { |
---|
263 | unsigned short cpmt_tgcr; |
---|
264 | char res1[0xe]; |
---|
265 | unsigned short cpmt_tmr1; |
---|
266 | unsigned short cpmt_tmr2; |
---|
267 | unsigned short cpmt_trr1; |
---|
268 | unsigned short cpmt_trr2; |
---|
269 | unsigned short cpmt_tcr1; |
---|
270 | unsigned short cpmt_tcr2; |
---|
271 | unsigned short cpmt_tcn1; |
---|
272 | unsigned short cpmt_tcn2; |
---|
273 | unsigned short cpmt_tmr3; |
---|
274 | unsigned short cpmt_tmr4; |
---|
275 | unsigned short cpmt_trr3; |
---|
276 | unsigned short cpmt_trr4; |
---|
277 | unsigned short cpmt_tcr3; |
---|
278 | unsigned short cpmt_tcr4; |
---|
279 | unsigned short cpmt_tcn3; |
---|
280 | unsigned short cpmt_tcn4; |
---|
281 | unsigned short cpmt_ter1; |
---|
282 | unsigned short cpmt_ter2; |
---|
283 | unsigned short cpmt_ter3; |
---|
284 | unsigned short cpmt_ter4; |
---|
285 | char res2[8]; |
---|
286 | } cpmtimer8xx_t; |
---|
287 | |
---|
288 | /* Finally, the Communication Processor stuff..... |
---|
289 | */ |
---|
290 | typedef struct scc { /* Serial communication channels */ |
---|
291 | unsigned int scc_gsmrl; |
---|
292 | unsigned int scc_gsmrh; |
---|
293 | unsigned short scc_pmsr; |
---|
294 | char res1[2]; |
---|
295 | unsigned short scc_todr; |
---|
296 | unsigned short scc_dsr; |
---|
297 | unsigned short scc_scce; |
---|
298 | char res2[2]; |
---|
299 | unsigned short scc_sccm; |
---|
300 | char res3; |
---|
301 | unsigned char scc_sccs; |
---|
302 | char res4[8]; |
---|
303 | } scc_t; |
---|
304 | |
---|
305 | typedef struct smc { /* Serial management channels */ |
---|
306 | char res1[2]; |
---|
307 | unsigned short smc_smcmr; |
---|
308 | char res2[2]; |
---|
309 | unsigned char smc_smce; |
---|
310 | char res3[3]; |
---|
311 | unsigned char smc_smcm; |
---|
312 | char res4[5]; |
---|
313 | } smc_t; |
---|
314 | |
---|
315 | /* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but |
---|
316 | * it fits within the address space. |
---|
317 | */ |
---|
318 | typedef struct fec { |
---|
319 | unsigned int fec_addr_low; /* LS 32 bits of station address */ |
---|
320 | unsigned short fec_addr_high; /* MS 16 bits of address */ |
---|
321 | unsigned short res1; |
---|
322 | unsigned int fec_hash_table_high; |
---|
323 | unsigned int fec_hash_table_low; |
---|
324 | unsigned int fec_r_des_start; |
---|
325 | unsigned int fec_x_des_start; |
---|
326 | unsigned int fec_r_buff_size; |
---|
327 | unsigned int res2[9]; |
---|
328 | unsigned int fec_ecntrl; |
---|
329 | unsigned int fec_ievent; |
---|
330 | unsigned int fec_imask; |
---|
331 | unsigned int fec_ivec; |
---|
332 | unsigned int fec_r_des_active; |
---|
333 | unsigned int fec_x_des_active; |
---|
334 | unsigned int res3[10]; |
---|
335 | unsigned int fec_mii_data; |
---|
336 | unsigned int fec_mii_speed; |
---|
337 | unsigned int res4[17]; |
---|
338 | unsigned int fec_r_bound; |
---|
339 | unsigned int fec_r_fstart; |
---|
340 | unsigned int res5[6]; |
---|
341 | unsigned int fec_x_fstart; |
---|
342 | unsigned int res6[17]; |
---|
343 | unsigned int fec_fun_code; |
---|
344 | unsigned int res7[3]; |
---|
345 | unsigned int fec_r_cntrl; |
---|
346 | unsigned int fec_r_hash; |
---|
347 | unsigned int res8[14]; |
---|
348 | unsigned int fec_x_cntrl; |
---|
349 | unsigned int res9[0x1e]; |
---|
350 | } fec_t; |
---|
351 | |
---|
352 | typedef struct comm_proc { |
---|
353 | /* General control and status registers. |
---|
354 | */ |
---|
355 | unsigned short cp_cpcr; |
---|
356 | char res1[2]; |
---|
357 | unsigned short cp_rccr; |
---|
358 | char res2[6]; |
---|
359 | unsigned short cp_cpmcr1; |
---|
360 | unsigned short cp_cpmcr2; |
---|
361 | unsigned short cp_cpmcr3; |
---|
362 | unsigned short cp_cpmcr4; |
---|
363 | char res3[2]; |
---|
364 | unsigned short cp_rter; |
---|
365 | char res4[2]; |
---|
366 | unsigned short cp_rtmr; |
---|
367 | char res5[0x14]; |
---|
368 | |
---|
369 | /* Baud rate generators. |
---|
370 | */ |
---|
371 | unsigned int cp_brgc1; |
---|
372 | unsigned int cp_brgc2; |
---|
373 | unsigned int cp_brgc3; |
---|
374 | unsigned int cp_brgc4; |
---|
375 | |
---|
376 | /* Serial Communication Channels. |
---|
377 | */ |
---|
378 | scc_t cp_scc[4]; |
---|
379 | |
---|
380 | /* Serial Management Channels. |
---|
381 | */ |
---|
382 | smc_t cp_smc[2]; |
---|
383 | |
---|
384 | /* Serial Peripheral Interface. |
---|
385 | */ |
---|
386 | unsigned short cp_spmode; |
---|
387 | char res6[4]; |
---|
388 | unsigned char cp_spie; |
---|
389 | char res7[3]; |
---|
390 | unsigned char cp_spim; |
---|
391 | char res8[2]; |
---|
392 | unsigned char cp_spcom; |
---|
393 | char res9[2]; |
---|
394 | |
---|
395 | /* Parallel Interface Port. |
---|
396 | */ |
---|
397 | char res10[2]; |
---|
398 | unsigned short cp_pipc; |
---|
399 | char res11[2]; |
---|
400 | unsigned short cp_ptpr; |
---|
401 | unsigned int cp_pbdir; |
---|
402 | unsigned int cp_pbpar; |
---|
403 | char res12[2]; |
---|
404 | unsigned short cp_pbodr; |
---|
405 | unsigned int cp_pbdat; |
---|
406 | char res13[0x18]; |
---|
407 | |
---|
408 | /* Serial Interface and Time Slot Assignment. |
---|
409 | */ |
---|
410 | unsigned int cp_simode; |
---|
411 | unsigned char cp_sigmr; |
---|
412 | char res14; |
---|
413 | unsigned char cp_sistr; |
---|
414 | unsigned char cp_sicmr; |
---|
415 | char res15[4]; |
---|
416 | unsigned int cp_sicr; |
---|
417 | unsigned int cp_sirp; |
---|
418 | char res16[0x10c]; |
---|
419 | unsigned char cp_siram[0x200]; |
---|
420 | |
---|
421 | /* The fast ethernet controller is not really part of the CPM, |
---|
422 | * but it resides in the address space. |
---|
423 | */ |
---|
424 | fec_t cp_fec; |
---|
425 | char res18[0x1000]; |
---|
426 | |
---|
427 | /* Dual Ported RAM follows. |
---|
428 | * There are many different formats for this memory area |
---|
429 | * depending upon the devices used and options chosen. |
---|
430 | */ |
---|
431 | unsigned char cp_dpmem[0x1000]; /* BD / Data / ucode */ |
---|
432 | unsigned char res19[0xc00]; |
---|
433 | unsigned char cp_dparam[0x400]; /* Parameter RAM */ |
---|
434 | } cpm8xx_t; |
---|
435 | |
---|
436 | /* Internal memory map. |
---|
437 | */ |
---|
438 | typedef struct immap { |
---|
439 | sysconf8xx_t im_siu_conf; /* SIU Configuration */ |
---|
440 | pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */ |
---|
441 | memctl8xx_t im_memctl; /* Memory Controller */ |
---|
442 | sit8xx_t im_sit; /* System integration timers */ |
---|
443 | car8xx_t im_clkrst; /* Clocks and reset */ |
---|
444 | sitk8xx_t im_sitk; /* Sys int timer keys */ |
---|
445 | cark8xx_t im_clkrstk; /* Clocks and reset keys */ |
---|
446 | lcd8xx_t im_lcd; /* LCD (821 only) */ |
---|
447 | i2c8xx_t im_i2c; /* I2C control/status */ |
---|
448 | sdma8xx_t im_sdma; /* SDMA control/status */ |
---|
449 | cpic8xx_t im_cpic; /* CPM Interrupt Controller */ |
---|
450 | iop8xx_t im_ioport; /* IO Port control/status */ |
---|
451 | cpmtimer8xx_t im_cpmtimer; /* CPM timers */ |
---|
452 | cpm8xx_t im_cpm; /* Communication processor */ |
---|
453 | } immap_t; |
---|
454 | |
---|
455 | #endif /* __IMMAP_8XX__ */ |
---|