source: rtems/c/src/lib/libbsp/powerpc/helas403/startup/linkcmds @ be4284d0

4.104.114.84.95
Last change on this file since be4284d0 was be4284d0, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 30, 1998 at 9:50:42 PM

BSP submitted by Thomas Doerfler <td@…>:

Finally I am through: I have found the last bugs that made RTEMS-
4.0-beta3 start on my ppc403 board from ROM. So now the '403
support is up to date again.

Roughly I have added the following features:

  • support for the on-chip interrupt controller (in a separate module)
  • interrupt support for the console device
  • termios support for the console device

==============================================
Since the BSP behaivour changed in some details (console no
longer is polling, other memory layout etc) I have created a new
BSP "helas403" rather than changing the "papyrus" BSP. The old
"polled" console driver still sticks around in "console.c.polled"
To get the BSP up and running, I had to create the new BSP files
(derived from papyrus). Besides that, the following source areas
have been changed:

  • c/src/lib/libcpu/powerpc/ppc403: changes to console driver, small changes to clock driver, new "ictrl" interrupt controller driver
  • c/src/exec/score/cpu/powerpc/ppc.h: some small changes (added ppc403 characteristics like a exception vector prefix register, some special register definitions). I am quite sure, they are compatible with the existing sources, although I did not check
  • c/src/exec/score/cpu/powerpc/cpu.c: There is one severe limitation in the exception entries: Due to the current code arrangement, the "branch absolute" to the ISR handler may only jump to the first 128MByte or the last 128MByte of the 4GByte address range. When the ppc403 is running out of ROM, the ROM functions are located in the last 128MByte (0xFFF00000 and up). These addresses were not handled correctly (sign reduced) in "install_raw_handler". The change I added should work on existing ppc BSPs aswell...
  • c/src/lib/libc/termios.c: During my tests, I added one change you sent me, so this patch will already be incorporated in the current source tree.

There are some smaller changes, see the attached diff file.

=========================================
Concerning the GNU toolchain:

I tried several tool chains. Finally I almost succeeded with

egcs-1.0.3a with patch egcs-1.0.3-rtems-diff-19980527

I had to add the following lines to the egcs files. Without them
configure complaint that the cross compiler could not generate
executable output.

  • additional lines needed in egcs distribution in file gcc/config/rs6000/rtems.h:

+++ lines start
#undef STARTFILE_DEFAULT_SPEC
#define STARTFILE_DEFAULT_SPEC "ecrti.o%s"

#undef ENDFILE_DEFAULT_SPEC
#define ENDFILE_DEFAULT_SPEC "ecrtn.o%s"
++++ lines end

As far as I have seen in the Changelog of egcs, you have recently
sent two patches affecting the powerpc support, but they were
added in the wrong order.... :-(

egcs-19980628 with patch egcs-19980628-rtems-diff-19980707 does
not work!

I used binutils 2.9.1 with patch binutils-2.9.1-rtems-diff-19980515

(binutils 2.8.1 does not work, internal error in gas)

and newlib-1.8.0 with patch newlib-1.8.0-rtems-diff-19980707

Finally I had to poke a line in the "bit" script, since, on my LINUX
machine, the GNU make is only available as "make", not as
"gmake"...

For all the tools and newlib I selected configuration "powerpc-
rtems".


IMD Ingenieurbuero fuer Microcomputertechnik
Thomas Doerfler Herbststrasse 8
D-82178 Puchheim Germany
email: td@…

  • Property mode set to 100644
File size: 4.3 KB
Line 
1/*
2 *  This file contains directives for the GNU linker which are specific
3 *  to the helas-403
4 *  This file is intended to be used together with flashentry.s
5 *  it will generate a ROM that can be started directly after powerup reset
6 *  $Id$
7 */
8
9OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
10              "elf32-powerpc")
11OUTPUT_ARCH(powerpc)
12 SEARCH_DIR(/usr/local/powerpc-rtems/lib);
13 
14ENTRY(flash_entry)
15 
16MEMORY
17  {
18        RAM : ORIGIN = 0, LENGTH = 8M
19        FLASH : ORIGIN = 0xFFF00000, LENGTH = 512K
20  }
21
22  /* DIRTY TRICK: repeat addresses here, so we can work with them... */
23  flash.start = 0xFFF00000;
24  flash.size  = 512K;
25
26SECTIONS
27{
28  .entry :
29  {
30     *(.entry)
31  } > FLASH /* this is ROM for flash_entry */
32  .text :
33  {
34     text.start = . ;
35     *(.entry2)
36     *(.text)
37     *(.rodata)
38     *(.rodata1)
39     *(.descriptors)
40     *(rom_ver)
41     etext = ALIGN(0x10);
42     _etext = .;
43
44
45     __CTOR_LIST__ = .;
46     LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
47     *(.ctors)
48     LONG(0)
49     __CTOR_END__ = .;
50
51     __DTOR_LIST__ = .;
52     LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
53     *(.dtors)
54     LONG(0)
55     __DTOR_END__ = .;
56
57     *(.lit)
58     *(.shdata)
59     *(.init)
60     *(.fini)
61     . = ALIGN(0x10);
62     _endtext = .;
63     text.end = .;
64     copy.src = .;
65     copy.tmptop.txt = .;
66  } > FLASH /* this is ROM for flash_entry */
67
68  text.size = text.end - text.start;
69
70  /* R/W Data */
71  /* place vectors to start at offset 0x100... */
72  /* IMPORTANT: sections ".fill" and ".vectors" must be the first in RAM!!*/
73  .fill 0x00010000 :
74  {
75    . = . + 0x0100;
76  } > RAM
77 
78  .vectors :              AT (copy.src)
79  {
80    copy.dest = .;
81    *(.vectors)
82    . = ALIGN(0x10);
83    copy.tmptop.vec = .;
84  } > RAM
85
86  .data :                 AT (copy.tmptop.vec - copy.dest + copy.src)
87  {
88    *(.data)
89    *(.data1)
90    PROVIDE (__SDATA_START__ = .);
91    *(.sdata)
92    . = ALIGN(0x10);
93    copy.tmptop.dat = .;
94  } > RAM
95 
96  PROVIDE (__EXCEPT_START__ = .);
97  .gcc_except_table   :   AT (copy.tmptop.dat - copy.dest + copy.src)
98  {
99    *(.gcc_except_table)
100    . = ALIGN(0x10);
101    copy.tmptop.exc = .;
102  } >RAM
103  PROVIDE (__EXCEPT_END__ = .);
104
105  __GOT_START__ = .;
106  .got :                  AT (copy.tmptop.exc - copy.dest + copy.src)
107  {
108    s.got = .;
109    *(.got.plt) *(.got)
110    . = ALIGN(0x10);
111    copy.tmptop.got = .;
112  } > RAM
113  __GOT_END__ = .;
114
115  .got1 :                 AT (copy.tmptop.got - copy.dest + copy.src)
116  {
117    *(.got1)           
118    . = ALIGN(0x10);
119    copy.tmptop.gt1 = .;
120  } >RAM
121
122  PROVIDE (__GOT2_START__ = .);
123  PROVIDE (_GOT2_START_ = .);
124  .got2           :       AT (copy.tmptop.gt1 - copy.dest + copy.src)
125  {
126    *(.got2)   
127    . = ALIGN(0x10);
128    copy.tmptop.gt2 = .;
129  } >RAM
130  PROVIDE (__GOT2_END__ = .);
131  PROVIDE (_GOT2_END_ = .);
132
133  PROVIDE (__FIXUP_START__ = .);
134  PROVIDE (_FIXUP_START_ = .);
135  .fixup          :       AT (copy.tmptop.gt2 - copy.dest + copy.src)
136  {
137    *(.fixup)   
138    . = ALIGN(0x10);
139    copy.tmptop.fix = .;
140  } >RAM
141  PROVIDE (_FIXUP_END_ = .);
142  PROVIDE (__FIXUP_END__ = .);
143 
144  PROVIDE (__SDATA2_START__ = .);
145  .sdata2         :       AT (copy.tmptop.fix - copy.dest + copy.src)
146  {
147    *(.sdata2) 
148    . = ALIGN(0x10);
149    copy.tmptop.sda = .;
150  } >RAM
151
152  copy.size = copy.tmptop.sda - copy.dest;
153
154  .sbss2          :
155  {
156    *(.sbss2)   
157  } >RAM
158  PROVIDE (__SBSS2_END__ = .);
159
160  __SBSS_START__ = .;
161  .bss :
162  {
163    bss.start = .;
164    *(.bss) *(.sbss) *(COMMON)
165    bss.end = ALIGN(4);
166  } > RAM
167  __SBSS_END__ = .;
168 
169  bss.size = bss.end - bss.start;
170
171  /* reserve 16KByte for stack... */
172  stack.end = bss.end + 16K;
173  PROVIDE(_end = stack.end);
174
175  .line 0 : { *(.line) }
176  .debug 0 : { *(.debug) }
177  .debug_sfnames 0 : { *(.debug_sfnames) }
178  .debug_srcinfo 0 : { *(.debug_srcinfo) }
179  .debug_pubnames 0 : { *(.debug_pubnames) }
180  .debug_aranges 0 : { *(.debug_aranges) }
181  .debug_aregion 0 : { *(.debug_aregion) }
182  .debug_macinfo 0 : { *(.debug_macinfo) }
183  .stab 0 : { *(.stab) }
184  .stabstr 0 : { *(.stabstr) }
185
186  /*
187   * place reset instruction into last word of FLASH
188   * NOTE: after reset, PPC403 starts executing from address
189   * 0xFFFFFFFC
190   * The reset section is placed in ROM at 0xF7FFFFFC instead,
191   * but a mirror of this address exists at 0xFFFFFFFC due to
192   * the initial memory controller setup
193   */
194  .reset  flash.start - 4 + flash.size :
195  {
196    *(.reset)
197  } > FLASH
198}
199
200
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