source: rtems/c/src/lib/libbsp/powerpc/helas403/startup/linkcmds @ b221cd3d

4.104.114.84.95
Last change on this file since b221cd3d was b221cd3d, checked in by Joel Sherrill <joel.sherrill@…>, on Jun 14, 2002 at 5:27:26 PM

2002-06-14 Joel Sherrill <joel@…>

  • startup/linkcmds: Fixed typo and added gnu.linkonce.t and gnu.linkonce.r sections.
  • Property mode set to 100644
File size: 5.4 KB
Line 
1/*
2 *  This file contains directives for the GNU linker which are specific
3 *  to the helas-403
4 *  This file is intended to be used together with flashentry.s
5 *  it will generate a ROM that can be started directly after powerup reset
6 *  $Id$
7 */
8
9OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
10              "elf32-powerpc")
11OUTPUT_ARCH(powerpc)
12 SEARCH_DIR(/usr/local/powerpc-rtems/lib);
13 
14ENTRY(flash_entry)
15 
16MEMORY
17  {
18        RAM : ORIGIN = 0, LENGTH = 8M
19        FLASH : ORIGIN = 0xFFF00000, LENGTH = 512K
20  }
21
22  /* DIRTY TRICK: repeat addresses here, so we can work with them... */
23  flash.start = 0xFFF00000;
24  flash.size  = 512K;
25
26SECTIONS
27{
28  .entry :
29  {
30     *(.entry)
31  } > FLASH /* this is ROM for flash_entry */
32  .text :
33  {
34     text.start = . ;
35     *(.entry2)
36     *(.text)
37     *(.gnu.linkonce.t.*)
38     *(.rodata*)
39     *(.gnu.linkonce.r.*)
40     *(.rodata1)
41     *(.eh_frame)
42     *(.descriptors)
43     *(rom_ver)
44     etext = ALIGN(0x10);
45     _etext = .;
46
47
48     __CTOR_LIST__ = .;
49     LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
50     *(.ctors)
51     LONG(0)
52     __CTOR_END__ = .;
53
54     __DTOR_LIST__ = .;
55     LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
56     *(.dtors)
57     LONG(0)
58     __DTOR_END__ = .;
59
60     *(.lit)
61     *(.shdata)
62     _init = .; *(.init)
63     _fini = .; *(.fini)
64     . = ALIGN(0x10);
65     _endtext = .;
66     text.end = .;
67     copy.src = .;
68     copy.tmptop.txt = .;
69  } > FLASH /* this is ROM for flash_entry */
70
71  text.size = text.end - text.start;
72
73  /* R/W Data */
74  /* place vectors to start at offset 0x100... */
75  /* IMPORTANT: sections ".fill" and ".vectors" must be the first in RAM!!*/
76  .fill 0x00010000 :
77  {
78    . = . + 0x0100;
79  } > RAM
80 
81  .vectors :              AT (copy.src)
82  {
83    copy.dest = .;
84    *(.vectors)
85    . = ALIGN(0x10);
86    copy.tmptop.vec = .;
87  } > RAM
88
89  .data :                 AT (copy.tmptop.vec - copy.dest + copy.src)
90  {
91    *(.data)
92    *(.data1)
93    *(.gnu.linkonce.d*)
94    PROVIDE (__SDATA_START__ = .);
95    *(.sdata)
96    *(.gnu.linkonce.s.*)
97    . = ALIGN(0x10);
98    copy.tmptop.dat = .;
99  } > RAM
100 
101  PROVIDE (__EXCEPT_START__ = .);
102  .gcc_except_table   :   AT (copy.tmptop.dat - copy.dest + copy.src)
103  {
104    *(.gcc_except_table)
105    . = ALIGN(0x10);
106    copy.tmptop.exc = .;
107  } >RAM
108  PROVIDE (__EXCEPT_END__ = .);
109
110  __GOT_START__ = .;
111  .got :                  AT (copy.tmptop.exc - copy.dest + copy.src)
112  {
113    s.got = .;
114    *(.got.plt) *(.got)
115    . = ALIGN(0x10);
116    copy.tmptop.got = .;
117  } > RAM
118  __GOT_END__ = .;
119
120  .got1 :                 AT (copy.tmptop.got - copy.dest + copy.src)
121  {
122    *(.got1)           
123    . = ALIGN(0x10);
124    copy.tmptop.gt1 = .;
125  } >RAM
126
127  PROVIDE (__GOT2_START__ = .);
128  PROVIDE (_GOT2_START_ = .);
129  .got2           :       AT (copy.tmptop.gt1 - copy.dest + copy.src)
130  {
131    *(.got2)   
132    . = ALIGN(0x10);
133    copy.tmptop.gt2 = .;
134  } >RAM
135  PROVIDE (__GOT2_END__ = .);
136  PROVIDE (_GOT2_END_ = .);
137
138  PROVIDE (__FIXUP_START__ = .);
139  PROVIDE (_FIXUP_START_ = .);
140  .fixup          :       AT (copy.tmptop.gt2 - copy.dest + copy.src)
141  {
142    *(.fixup)   
143    . = ALIGN(0x10);
144    copy.tmptop.fix = .;
145  } >RAM
146  PROVIDE (_FIXUP_END_ = .);
147  PROVIDE (__FIXUP_END__ = .);
148 
149  PROVIDE (__SDATA2_START__ = .);
150  .sdata2         :       AT (copy.tmptop.fix - copy.dest + copy.src)
151  {
152    *(.sdata2) 
153    . = ALIGN(0x10);
154    copy.tmptop.sda = .;
155  } >RAM
156
157  copy.size = copy.tmptop.sda - copy.dest;
158
159  .sbss2          :
160  {
161    *(.sbss2)   
162  } >RAM
163  PROVIDE (__SBSS2_END__ = .);
164
165  __SBSS_START__ = .;
166  .bss :
167  {
168    bss.start = .;
169    *(.bss) *(.sbss) *(COMMON)
170    bss.end = ALIGN(4);
171  } > RAM
172  __SBSS_END__ = .;
173 
174  bss.size = bss.end - bss.start;
175
176  /* reserve 16KByte for stack... */
177  stack.end = bss.end + 16K;
178  PROVIDE(_end = stack.end);
179
180
181  /* Stabs debugging sections.  */
182  .stab 0 : { *(.stab) }
183  .stabstr 0 : { *(.stabstr) }
184  .stab.excl 0 : { *(.stab.excl) }
185  .stab.exclstr 0 : { *(.stab.exclstr) }
186  .stab.index 0 : { *(.stab.index) }
187  .stab.indexstr 0 : { *(.stab.indexstr) }
188  .comment 0 : { *(.comment) }
189
190  /* DWARF debug sections.
191     Symbols in the DWARF debugging sections are relative to the beginning
192     of the section so we begin them at 0.  */
193  /* DWARF 1 */
194  .debug          0 : { *(.debug) }
195  .line           0 : { *(.line) }
196 
197  /* GNU DWARF 1 extensions */
198  .debug_srcinfo  0 : { *(.debug_srcinfo) }
199  .debug_sfnames  0 : { *(.debug_sfnames) }
200 
201  /* DWARF 1.1 and DWARF 2 */
202  .debug_aranges  0 : { *(.debug_aranges) }
203  .debug_pubnames 0 : { *(.debug_pubnames) }
204 
205  /* DWARF 2 */
206  .debug_info     0 : { *(.debug_info) }
207  .debug_abbrev   0 : { *(.debug_abbrev) }
208  .debug_line     0 : { *(.debug_line) }
209  .debug_frame    0 : { *(.debug_frame) }
210  .debug_str      0 : { *(.debug_str) }
211  .debug_loc      0 : { *(.debug_loc) }
212  .debug_macinfo  0 : { *(.debug_macinfo) }
213 
214  /* SGI/MIPS DWARF 2 extensions */
215  .debug_weaknames 0 : { *(.debug_weaknames) }
216  .debug_funcnames 0 : { *(.debug_funcnames) }
217  .debug_typenames 0 : { *(.debug_typenames) }
218  .debug_varnames  0 : { *(.debug_varnames) }
219
220  /* These must appear regardless of  .  */
221  /*
222   * place reset instruction into last word of FLASH
223   * NOTE: after reset, PPC403 starts executing from address
224   * 0xFFFFFFFC
225   * The reset section is placed in ROM at 0xF7FFFFFC instead,
226   * but a mirror of this address exists at 0xFFFFFFFC due to
227   * the initial memory controller setup
228   */
229  .reset  flash.start - 4 + flash.size :
230  {
231    *(.reset)
232  } > FLASH
233}
234
235
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