source: rtems/c/src/lib/libbsp/powerpc/helas403/startup/linkcmds @ 85c92574

4.104.114.84.95
Last change on this file since 85c92574 was 85c92574, checked in by Joel Sherrill <joel.sherrill@…>, on May 9, 2002 at 9:37:30 PM

2001-05-09 Joel Sherrill <joel@…>

  • startup/linkcmds: In support of gcc 3.1, added one of more of the sections .jcr, .rodata*, .data.*, .gnu.linkonce.s2.*, .gnu.linkonce.sb2.*, and .gnu.linkonce.s.*. Spacing corrections and direction of segments to memory regions may also have been addressed. This was a sweep across all BSPs.
  • Property mode set to 100644
File size: 5.3 KB
Line 
1/*
2 *  This file contains directives for the GNU linker which are specific
3 *  to the helas-403
4 *  This file is intended to be used together with flashentry.s
5 *  it will generate a ROM that can be started directly after powerup reset
6 *  $Id$
7 */
8
9OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
10              "elf32-powerpc")
11OUTPUT_ARCH(powerpc)
12 SEARCH_DIR(/usr/local/powerpc-rtems/lib);
13 
14ENTRY(flash_entry)
15 
16MEMORY
17  {
18        RAM : ORIGIN = 0, LENGTH = 8M
19        FLASH : ORIGIN = 0xFFF00000, LENGTH = 512K
20  }
21
22  /* DIRTY TRICK: repeat addresses here, so we can work with them... */
23  flash.start = 0xFFF00000;
24  flash.size  = 512K;
25
26SECTIONS
27{
28  .entry :
29  {
30     *(.entry)
31  } > FLASH /* this is ROM for flash_entry */
32  .text :
33  {
34     text.start = . ;
35     *(.entry2)
36     *(.text)
37     *(.rodata*)
38     *(.rodata1)
39     *.(eh_frame)
40     *(.descriptors)
41     *(rom_ver)
42     etext = ALIGN(0x10);
43     _etext = .;
44
45
46     __CTOR_LIST__ = .;
47     LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
48     *(.ctors)
49     LONG(0)
50     __CTOR_END__ = .;
51
52     __DTOR_LIST__ = .;
53     LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
54     *(.dtors)
55     LONG(0)
56     __DTOR_END__ = .;
57
58     *(.lit)
59     *(.shdata)
60     _init = .; *(.init)
61     _fini = .; *(.fini)
62     . = ALIGN(0x10);
63     _endtext = .;
64     text.end = .;
65     copy.src = .;
66     copy.tmptop.txt = .;
67  } > FLASH /* this is ROM for flash_entry */
68
69  text.size = text.end - text.start;
70
71  /* R/W Data */
72  /* place vectors to start at offset 0x100... */
73  /* IMPORTANT: sections ".fill" and ".vectors" must be the first in RAM!!*/
74  .fill 0x00010000 :
75  {
76    . = . + 0x0100;
77  } > RAM
78 
79  .vectors :              AT (copy.src)
80  {
81    copy.dest = .;
82    *(.vectors)
83    . = ALIGN(0x10);
84    copy.tmptop.vec = .;
85  } > RAM
86
87  .data :                 AT (copy.tmptop.vec - copy.dest + copy.src)
88  {
89    *(.data)
90    *(.data1)
91    PROVIDE (__SDATA_START__ = .);
92    *(.sdata)
93    *(.gnu.linkonce.s.*)
94    . = ALIGN(0x10);
95    copy.tmptop.dat = .;
96  } > RAM
97 
98  PROVIDE (__EXCEPT_START__ = .);
99  .gcc_except_table   :   AT (copy.tmptop.dat - copy.dest + copy.src)
100  {
101    *(.gcc_except_table)
102    . = ALIGN(0x10);
103    copy.tmptop.exc = .;
104  } >RAM
105  PROVIDE (__EXCEPT_END__ = .);
106
107  __GOT_START__ = .;
108  .got :                  AT (copy.tmptop.exc - copy.dest + copy.src)
109  {
110    s.got = .;
111    *(.got.plt) *(.got)
112    . = ALIGN(0x10);
113    copy.tmptop.got = .;
114  } > RAM
115  __GOT_END__ = .;
116
117  .got1 :                 AT (copy.tmptop.got - copy.dest + copy.src)
118  {
119    *(.got1)           
120    . = ALIGN(0x10);
121    copy.tmptop.gt1 = .;
122  } >RAM
123
124  PROVIDE (__GOT2_START__ = .);
125  PROVIDE (_GOT2_START_ = .);
126  .got2           :       AT (copy.tmptop.gt1 - copy.dest + copy.src)
127  {
128    *(.got2)   
129    . = ALIGN(0x10);
130    copy.tmptop.gt2 = .;
131  } >RAM
132  PROVIDE (__GOT2_END__ = .);
133  PROVIDE (_GOT2_END_ = .);
134
135  PROVIDE (__FIXUP_START__ = .);
136  PROVIDE (_FIXUP_START_ = .);
137  .fixup          :       AT (copy.tmptop.gt2 - copy.dest + copy.src)
138  {
139    *(.fixup)   
140    . = ALIGN(0x10);
141    copy.tmptop.fix = .;
142  } >RAM
143  PROVIDE (_FIXUP_END_ = .);
144  PROVIDE (__FIXUP_END__ = .);
145 
146  PROVIDE (__SDATA2_START__ = .);
147  .sdata2         :       AT (copy.tmptop.fix - copy.dest + copy.src)
148  {
149    *(.sdata2) 
150    . = ALIGN(0x10);
151    copy.tmptop.sda = .;
152  } >RAM
153
154  copy.size = copy.tmptop.sda - copy.dest;
155
156  .sbss2          :
157  {
158    *(.sbss2)   
159  } >RAM
160  PROVIDE (__SBSS2_END__ = .);
161
162  __SBSS_START__ = .;
163  .bss :
164  {
165    bss.start = .;
166    *(.bss) *(.sbss) *(COMMON)
167    bss.end = ALIGN(4);
168  } > RAM
169  __SBSS_END__ = .;
170 
171  bss.size = bss.end - bss.start;
172
173  /* reserve 16KByte for stack... */
174  stack.end = bss.end + 16K;
175  PROVIDE(_end = stack.end);
176
177
178  /* Stabs debugging sections.  */
179  .stab 0 : { *(.stab) }
180  .stabstr 0 : { *(.stabstr) }
181  .stab.excl 0 : { *(.stab.excl) }
182  .stab.exclstr 0 : { *(.stab.exclstr) }
183  .stab.index 0 : { *(.stab.index) }
184  .stab.indexstr 0 : { *(.stab.indexstr) }
185  .comment 0 : { *(.comment) }
186
187  /* DWARF debug sections.
188     Symbols in the DWARF debugging sections are relative to the beginning
189     of the section so we begin them at 0.  */
190  /* DWARF 1 */
191  .debug          0 : { *(.debug) }
192  .line           0 : { *(.line) }
193 
194  /* GNU DWARF 1 extensions */
195  .debug_srcinfo  0 : { *(.debug_srcinfo) }
196  .debug_sfnames  0 : { *(.debug_sfnames) }
197 
198  /* DWARF 1.1 and DWARF 2 */
199  .debug_aranges  0 : { *(.debug_aranges) }
200  .debug_pubnames 0 : { *(.debug_pubnames) }
201 
202  /* DWARF 2 */
203  .debug_info     0 : { *(.debug_info) }
204  .debug_abbrev   0 : { *(.debug_abbrev) }
205  .debug_line     0 : { *(.debug_line) }
206  .debug_frame    0 : { *(.debug_frame) }
207  .debug_str      0 : { *(.debug_str) }
208  .debug_loc      0 : { *(.debug_loc) }
209  .debug_macinfo  0 : { *(.debug_macinfo) }
210 
211  /* SGI/MIPS DWARF 2 extensions */
212  .debug_weaknames 0 : { *(.debug_weaknames) }
213  .debug_funcnames 0 : { *(.debug_funcnames) }
214  .debug_typenames 0 : { *(.debug_typenames) }
215  .debug_varnames  0 : { *(.debug_varnames) }
216
217  /* These must appear regardless of  .  */
218  /*
219   * place reset instruction into last word of FLASH
220   * NOTE: after reset, PPC403 starts executing from address
221   * 0xFFFFFFFC
222   * The reset section is placed in ROM at 0xF7FFFFFC instead,
223   * but a mirror of this address exists at 0xFFFFFFFC due to
224   * the initial memory controller setup
225   */
226  .reset  flash.start - 4 + flash.size :
227  {
228    *(.reset)
229  } > FLASH
230}
231
232
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