[be4284d0] | 1 | /* |
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| 2 | * This file contains directives for the GNU linker which are specific |
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| 3 | * to the helas-403 |
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| 4 | * This file is intended to be used together with flashentry.s |
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| 5 | * it will generate a ROM that can be started directly after powerup reset |
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| 6 | * $Id$ |
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| 7 | */ |
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| 8 | |
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| 9 | OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc", |
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| 10 | "elf32-powerpc") |
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| 11 | OUTPUT_ARCH(powerpc) |
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| 12 | SEARCH_DIR(/usr/local/powerpc-rtems/lib); |
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| 13 | |
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| 14 | ENTRY(flash_entry) |
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| 15 | |
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| 16 | MEMORY |
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| 17 | { |
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| 18 | RAM : ORIGIN = 0, LENGTH = 8M |
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| 19 | FLASH : ORIGIN = 0xFFF00000, LENGTH = 512K |
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| 20 | } |
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| 21 | |
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| 22 | /* DIRTY TRICK: repeat addresses here, so we can work with them... */ |
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| 23 | flash.start = 0xFFF00000; |
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| 24 | flash.size = 512K; |
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| 25 | |
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| 26 | SECTIONS |
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| 27 | { |
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| 28 | .entry : |
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| 29 | { |
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| 30 | *(.entry) |
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| 31 | } > FLASH /* this is ROM for flash_entry */ |
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| 32 | .text : |
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| 33 | { |
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| 34 | text.start = . ; |
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| 35 | *(.entry2) |
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| 36 | *(.text) |
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[b221cd3d] | 37 | *(.gnu.linkonce.t.*) |
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[85c92574] | 38 | *(.rodata*) |
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[b221cd3d] | 39 | *(.gnu.linkonce.r.*) |
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[be4284d0] | 40 | *(.rodata1) |
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[9c1133e] | 41 | |
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| 42 | /* |
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| 43 | * Special FreeBSD sysctl sections. |
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| 44 | */ |
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| 45 | . = ALIGN (16); |
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| 46 | __start_set_sysctl_set = .; |
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| 47 | *(set_sysctl_*); |
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| 48 | __stop_set_sysctl_set = ABSOLUTE(.); |
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| 49 | *(set_domain_*); |
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| 50 | *(set_pseudo_*); |
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| 51 | |
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[b221cd3d] | 52 | *(.eh_frame) |
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[be4284d0] | 53 | *(.descriptors) |
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| 54 | *(rom_ver) |
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| 55 | etext = ALIGN(0x10); |
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| 56 | _etext = .; |
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| 57 | |
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| 58 | |
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| 59 | __CTOR_LIST__ = .; |
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| 60 | LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2) |
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| 61 | *(.ctors) |
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| 62 | LONG(0) |
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| 63 | __CTOR_END__ = .; |
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| 64 | |
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| 65 | __DTOR_LIST__ = .; |
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| 66 | LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2) |
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| 67 | *(.dtors) |
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| 68 | LONG(0) |
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| 69 | __DTOR_END__ = .; |
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| 70 | |
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| 71 | *(.lit) |
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| 72 | *(.shdata) |
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[ac9253e] | 73 | _init = .; *(.init) |
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| 74 | _fini = .; *(.fini) |
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[be4284d0] | 75 | . = ALIGN(0x10); |
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| 76 | _endtext = .; |
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| 77 | text.end = .; |
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| 78 | copy.src = .; |
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| 79 | copy.tmptop.txt = .; |
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| 80 | } > FLASH /* this is ROM for flash_entry */ |
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| 81 | |
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| 82 | text.size = text.end - text.start; |
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| 83 | |
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| 84 | /* R/W Data */ |
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| 85 | /* place vectors to start at offset 0x100... */ |
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| 86 | /* IMPORTANT: sections ".fill" and ".vectors" must be the first in RAM!!*/ |
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| 87 | .fill 0x00010000 : |
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| 88 | { |
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| 89 | . = . + 0x0100; |
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| 90 | } > RAM |
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| 91 | |
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| 92 | .vectors : AT (copy.src) |
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| 93 | { |
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| 94 | copy.dest = .; |
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| 95 | *(.vectors) |
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| 96 | . = ALIGN(0x10); |
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| 97 | copy.tmptop.vec = .; |
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| 98 | } > RAM |
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| 99 | |
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| 100 | .data : AT (copy.tmptop.vec - copy.dest + copy.src) |
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| 101 | { |
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| 102 | *(.data) |
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| 103 | *(.data1) |
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[7c2239fe] | 104 | *(.data.* .gnu.linkonce.d*) |
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[be4284d0] | 105 | PROVIDE (__SDATA_START__ = .); |
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| 106 | *(.sdata) |
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[85c92574] | 107 | *(.gnu.linkonce.s.*) |
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[be4284d0] | 108 | . = ALIGN(0x10); |
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| 109 | copy.tmptop.dat = .; |
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| 110 | } > RAM |
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| 111 | |
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| 112 | PROVIDE (__EXCEPT_START__ = .); |
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| 113 | .gcc_except_table : AT (copy.tmptop.dat - copy.dest + copy.src) |
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| 114 | { |
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| 115 | *(.gcc_except_table) |
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| 116 | . = ALIGN(0x10); |
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| 117 | copy.tmptop.exc = .; |
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| 118 | } >RAM |
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| 119 | PROVIDE (__EXCEPT_END__ = .); |
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| 120 | |
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| 121 | __GOT_START__ = .; |
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| 122 | .got : AT (copy.tmptop.exc - copy.dest + copy.src) |
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| 123 | { |
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| 124 | s.got = .; |
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| 125 | *(.got.plt) *(.got) |
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| 126 | . = ALIGN(0x10); |
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| 127 | copy.tmptop.got = .; |
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| 128 | } > RAM |
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| 129 | __GOT_END__ = .; |
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| 130 | |
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| 131 | .got1 : AT (copy.tmptop.got - copy.dest + copy.src) |
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| 132 | { |
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| 133 | *(.got1) |
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| 134 | . = ALIGN(0x10); |
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| 135 | copy.tmptop.gt1 = .; |
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| 136 | } >RAM |
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| 137 | |
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| 138 | PROVIDE (__GOT2_START__ = .); |
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| 139 | PROVIDE (_GOT2_START_ = .); |
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| 140 | .got2 : AT (copy.tmptop.gt1 - copy.dest + copy.src) |
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| 141 | { |
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| 142 | *(.got2) |
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| 143 | . = ALIGN(0x10); |
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| 144 | copy.tmptop.gt2 = .; |
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| 145 | } >RAM |
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| 146 | PROVIDE (__GOT2_END__ = .); |
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| 147 | PROVIDE (_GOT2_END_ = .); |
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| 148 | |
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| 149 | PROVIDE (__FIXUP_START__ = .); |
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| 150 | PROVIDE (_FIXUP_START_ = .); |
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| 151 | .fixup : AT (copy.tmptop.gt2 - copy.dest + copy.src) |
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| 152 | { |
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| 153 | *(.fixup) |
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| 154 | . = ALIGN(0x10); |
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| 155 | copy.tmptop.fix = .; |
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| 156 | } >RAM |
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| 157 | PROVIDE (_FIXUP_END_ = .); |
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| 158 | PROVIDE (__FIXUP_END__ = .); |
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| 159 | |
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| 160 | PROVIDE (__SDATA2_START__ = .); |
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| 161 | .sdata2 : AT (copy.tmptop.fix - copy.dest + copy.src) |
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| 162 | { |
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| 163 | *(.sdata2) |
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| 164 | . = ALIGN(0x10); |
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| 165 | copy.tmptop.sda = .; |
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| 166 | } >RAM |
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| 167 | |
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| 168 | copy.size = copy.tmptop.sda - copy.dest; |
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| 169 | |
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| 170 | .sbss2 : |
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| 171 | { |
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| 172 | *(.sbss2) |
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| 173 | } >RAM |
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| 174 | PROVIDE (__SBSS2_END__ = .); |
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| 175 | |
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| 176 | __SBSS_START__ = .; |
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| 177 | .bss : |
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| 178 | { |
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| 179 | bss.start = .; |
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| 180 | *(.bss) *(.sbss) *(COMMON) |
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| 181 | bss.end = ALIGN(4); |
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| 182 | } > RAM |
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| 183 | __SBSS_END__ = .; |
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| 184 | |
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| 185 | bss.size = bss.end - bss.start; |
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| 186 | |
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| 187 | /* reserve 16KByte for stack... */ |
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| 188 | stack.end = bss.end + 16K; |
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| 189 | PROVIDE(_end = stack.end); |
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| 190 | |
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[4cb5d29] | 191 | |
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| 192 | /* Stabs debugging sections. */ |
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[be4284d0] | 193 | .stab 0 : { *(.stab) } |
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| 194 | .stabstr 0 : { *(.stabstr) } |
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[4cb5d29] | 195 | .stab.excl 0 : { *(.stab.excl) } |
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| 196 | .stab.exclstr 0 : { *(.stab.exclstr) } |
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| 197 | .stab.index 0 : { *(.stab.index) } |
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| 198 | .stab.indexstr 0 : { *(.stab.indexstr) } |
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| 199 | .comment 0 : { *(.comment) } |
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| 200 | |
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| 201 | /* DWARF debug sections. |
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| 202 | Symbols in the DWARF debugging sections are relative to the beginning |
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| 203 | of the section so we begin them at 0. */ |
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| 204 | /* DWARF 1 */ |
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| 205 | .debug 0 : { *(.debug) } |
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| 206 | .line 0 : { *(.line) } |
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| 207 | |
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| 208 | /* GNU DWARF 1 extensions */ |
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| 209 | .debug_srcinfo 0 : { *(.debug_srcinfo) } |
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| 210 | .debug_sfnames 0 : { *(.debug_sfnames) } |
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| 211 | |
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| 212 | /* DWARF 1.1 and DWARF 2 */ |
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| 213 | .debug_aranges 0 : { *(.debug_aranges) } |
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| 214 | .debug_pubnames 0 : { *(.debug_pubnames) } |
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| 215 | |
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| 216 | /* DWARF 2 */ |
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| 217 | .debug_info 0 : { *(.debug_info) } |
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| 218 | .debug_abbrev 0 : { *(.debug_abbrev) } |
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| 219 | .debug_line 0 : { *(.debug_line) } |
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| 220 | .debug_frame 0 : { *(.debug_frame) } |
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| 221 | .debug_str 0 : { *(.debug_str) } |
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| 222 | .debug_loc 0 : { *(.debug_loc) } |
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| 223 | .debug_macinfo 0 : { *(.debug_macinfo) } |
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| 224 | |
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| 225 | /* SGI/MIPS DWARF 2 extensions */ |
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| 226 | .debug_weaknames 0 : { *(.debug_weaknames) } |
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| 227 | .debug_funcnames 0 : { *(.debug_funcnames) } |
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| 228 | .debug_typenames 0 : { *(.debug_typenames) } |
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| 229 | .debug_varnames 0 : { *(.debug_varnames) } |
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[be4284d0] | 230 | |
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[4cb5d29] | 231 | /* These must appear regardless of . */ |
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[be4284d0] | 232 | /* |
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| 233 | * place reset instruction into last word of FLASH |
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| 234 | * NOTE: after reset, PPC403 starts executing from address |
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| 235 | * 0xFFFFFFFC |
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| 236 | * The reset section is placed in ROM at 0xF7FFFFFC instead, |
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| 237 | * but a mirror of this address exists at 0xFFFFFFFC due to |
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| 238 | * the initial memory controller setup |
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| 239 | */ |
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| 240 | .reset flash.start - 4 + flash.size : |
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| 241 | { |
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| 242 | *(.reset) |
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| 243 | } > FLASH |
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| 244 | } |
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| 245 | |
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| 246 | |
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