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flashentry.s @ be4284d0

4.104.114.84.95

Last change on this file since be4284d0 was be4284d0, checked in by Joel Sherrill <joel.sherrill@…>, on 09/30/98 at 21:50:42

BSP submitted by Thomas Doerfler <td@…>:

Finally I am through: I have found the last bugs that made RTEMS-
4.0-beta3 start on my ppc403 board from ROM. So now the '403
support is up to date again.

Roughly I have added the following features:

support for the on-chip interrupt controller (in a separate module)
interrupt support for the console device
termios support for the console device

==============================================
Since the BSP behaivour changed in some details (console no
longer is polling, other memory layout etc) I have created a new
BSP "helas403" rather than changing the "papyrus" BSP. The old
"polled" console driver still sticks around in "console.c.polled"
To get the BSP up and running, I had to create the new BSP files
(derived from papyrus). Besides that, the following source areas
have been changed:

c/src/lib/libcpu/powerpc/ppc403: changes to console driver, small changes to clock driver, new "ictrl" interrupt controller driver

c/src/exec/score/cpu/powerpc/ppc.h: some small changes (added ppc403 characteristics like a exception vector prefix register, some special register definitions). I am quite sure, they are compatible with the existing sources, although I did not check

c/src/exec/score/cpu/powerpc/cpu.c: There is one severe limitation in the exception entries: Due to the current code arrangement, the "branch absolute" to the ISR handler may only jump to the first 128MByte or the last 128MByte of the 4GByte address range. When the ppc403 is running out of ROM, the ROM functions are located in the last 128MByte (0xFFF00000 and up). These addresses were not handled correctly (sign reduced) in "install_raw_handler". The change I added should work on existing ppc BSPs aswell...

c/src/lib/libc/termios.c: During my tests, I added one change you sent me, so this patch will already be incorporated in the current source tree.

There are some smaller changes, see the attached diff file.

=========================================
Concerning the GNU toolchain:

I tried several tool chains. Finally I almost succeeded with

egcs-1.0.3a with patch egcs-1.0.3-rtems-diff-19980527

I had to add the following lines to the egcs files. Without them
configure complaint that the cross compiler could not generate
executable output.

additional lines needed in egcs distribution in file gcc/config/rs6000/rtems.h:

+++ lines start
#undef STARTFILE_DEFAULT_SPEC
#define STARTFILE_DEFAULT_SPEC "ecrti.o%s"

#undef ENDFILE_DEFAULT_SPEC
#define ENDFILE_DEFAULT_SPEC "ecrtn.o%s"
++++ lines end

As far as I have seen in the Changelog of egcs, you have recently
sent two patches affecting the powerpc support, but they were
added in the wrong order.... :-(

egcs-19980628 with patch egcs-19980628-rtems-diff-19980707 does
not work!

I used binutils 2.9.1 with patch binutils-2.9.1-rtems-diff-19980515

(binutils 2.8.1 does not work, internal error in gas)

and newlib-1.8.0 with patch newlib-1.8.0-rtems-diff-19980707

Finally I had to poke a line in the "bit" script, since, on my LINUX
machine, the GNU make is only available as "make", not as
"gmake"...

For all the tools and newlib I selected configuration "powerpc-
rtems".

IMD Ingenieurbuero fuer Microcomputertechnik
Thomas Doerfler Herbststrasse 8
D-82178 Puchheim Germany
email: td@…

Property mode set to 100644

File size: 19.8 KB

Line
1	/* flashentry.s
2	*
3	* This file contains the entry code for RTEMS programs starting
4	* directly from Flash.
5	*
6	* Author: Thomas Doerfler <td@imd.m.isar.de>
7	* IMD Ingenieurbuero fuer Microcomputertechnik
8	*
9	* COPYRIGHT (c) 1998 by IMD
10	*
11	* Changes from IMD are covered by the original distributions terms.
12	* This file has been derived from the papyrus BSP:
13	*
14	* This file contains the entry veneer for RTEMS programs
15	* stored in Papyrus' flash ROM.
16	*
17	* Author: Andrew Bray <andy@i-cubed.co.uk>
18	*
19	* COPYRIGHT (c) 1995 by i-cubed ltd.
20	*
21	* To anyone who acknowledges that this file is provided "AS IS"
22	* without any express or implied warranty:
23	* permission to use, copy, modify, and distribute this file
24	* for any purpose is hereby granted without fee, provided that
25	* the above copyright notice and this notice appears in all
26	* copies, and that the name of i-cubed limited not be used in
27	* advertising or publicity pertaining to distribution of the
28	* software without specific, written prior permission.
29	* i-cubed limited makes no representations about the suitability
30	* of this software for any purpose.
31	*
32	* $Id$
33	*/
34
35	#include "asm.h"
36	#include <rtems/score/ppc.h>
37
38	/*----------------------------------------------------------------------------
39	* Reset_entry.
40	---------------------------------------------------------------------------/
41	#if PPC_ASM == PPC_ASM_ELF
42	.section .reset,"ax",@progbits
43	/* this section MUST be located at absolute address 0xFFFFFFFC
44	or last word of EPROM */
45	#else
46	.csect .text[PR]
47	#endif
48
49	ba flash_entry /* this is the first instruction after reset */
50
51	.previous
52
53	/*----------------------------------------------------------------------------
54	* ROM Vector area.
55	---------------------------------------------------------------------------/
56	#if PPC_ASM == PPC_ASM_ELF
57	.section .entry,"ax",@progbits
58	#else
59	.csect .text[PR]
60	#endif
61	PUBLIC_VAR (flash_entry)
62	SYM (flash_entry):
63	bl .startup /* call startup, link reg points to base_addr */
64	base_addr:
65	/*----------------------------------------------------------------------------
66	* Parameters from linker
67	---------------------------------------------------------------------------/
68	toc_pointer:
69	#if PPC_ASM == PPC_ASM_ELF
70	.long s.got
71	#else
72	.long TOC[tc0]
73	#endif
74	text_length:
75	.long text.size
76	text_addr:
77	.long text.start
78	copy_src:
79	.long copy.src
80	copy_length:
81	.long copy.size
82	copy_dest:
83	.long copy.dest
84	bss_length:
85	.long bss.size
86	bss_addr:
87	.long bss.start
88	stack_top:
89	.long stack.end
90
91	/*----------------------------------------------------------------------------
92	* from Reset_entry.
93	---------------------------------------------------------------------------/
94	.startup:
95	/* Get start address, r1 points to label base_addr */
96	mflr r1
97
98	/* Set up Bank regs, cache etc. */
99	/* set up bank register BR0 for Flash-EPROM:
100	* NOTE: bank size should stay 1MByte, this is standard size
101	* after RESET
102	* base addr = Fffxxxxx -> 0b11111111........................
103	* bank size = 1 MByte -> 0b........000..................... (std)
104	* bank use = readonly -> 0b...........01...................
105	* seq. fill = targ frst-> 0b.............0..................
106	* burst mode= enable -> 0b..............1.................
107	* bus width = 8 bit -> 0b...............00...............
108	* ready pin = disable -> 0b.................0..............
109	* first wait= 2 clocks -> 0b..................0010..........
110	* burst wait= 2 clocks -> 0b......................10........
111	* CSon time = 0 clocks -> 0b........................0.......
112	* OEon time = 0 clocks -> 0b.........................0......
113	* WBon time = 1 clocks -> 0b..........................1.....
114	* WBoff time= 0 clocks -> 0b...........................0....
115	* Hold time = 1 clocks -> 0b............................001.
116	* ram type = SRAM(ign)-> 0b...............................1
117	* value 0b11111111000010100000101000100011
118	* 0x F F 0 A 0 A 2 3
119	*/
120	lis r2,0xFF0A
121	ori r2,r2,0x0A23
122
123	mtdcr br0,r2 /* write to DCR BR0 */
124
125
126	/*--------------------------------------------------------------------
127	* test various RAM configurations (from big to small per bank)
128	------------------------------------------------------------------/
129	/*--------------------------------------------------------------------
130	* test RAM config 16 MByte (1x4Mx32Bit)
131	------------------------------------------------------------------/
132	/* set up bank register BR7 for DRAM:
133	* base addr = 000xxxxx -> 0b00000000........................
134	* bank size = 16MByte -> 0b........100.....................
135	* bank use = readwrite-> 0b...........11...................
136	* seq. fill = targ.frst-> 0b.............0..................
137	* early RAS = disabled -> 0b..............0.................
138	* bus width = 32bit -> 0b...............10...............
139	* adr mux = internal -> 0b.................0..............
140	* RAS to CAS= 2 clocks -> 0b..................1.............
141	* Alt. Rfrsh= normal -> 0b...................0............
142	* page mode = enabled -> 0b....................1...........
143	* first wait= 1 clocks -> 0b.....................01.........
144	* burst wait= 1 clocks -> 0b.......................01.......
145	* precharge = 1 clocks -> 0b.........................0......
146	* RAS Rfrsh = 2 clocks -> 0b..........................1.....
147	* Rfrsh Itvl= 512 clks -> 0b...........................1000.
148	* ram type = DRAM -> 0b...............................0
149	* value 0b00000000100110010010101010110000
150	* 0x 0 0 9 9 2 A B 0
151	*/
152	lis r2,0x0099
153	ori r2,r2,0x2AB0
154	mtdcr br7,r2 /* write to DCR BR7*/
155
156	lis r2,0x0000 /* start address = 0x00000000 */
157	lis r3,0x0100 /* size 16 MB = 0x01000000 */
158	bl ramacc /* test memory accessibility */
159	cmpi 0,0,r4,0 /* memory ok? else test smaller size */
160	bne ramcfgt18
161
162	/*--------------------------------------------------------------------
163	* test RAM config 32 MByte (2x4Mx32Bit)
164	------------------------------------------------------------------/
165	/* set up bank register BR7 like above
166	* set up bank register BR6 for DRAM:
167	* base addr = 010xxxxx -> 0b00010000........................
168	* bank size = 16MByte -> 0b........100..................... (for now)
169	* bank use = readwrite-> 0b...........11...................
170	* seq. fill = targ.frst-> 0b.............0..................
171	* early RAS = disabled -> 0b..............0.................
172	* bus width = 32bit -> 0b...............10...............
173	* adr mux = internal -> 0b.................0..............
174	* RAS to CAS= 2 clocks -> 0b..................1.............
175	* Alt. Rfrsh= normal -> 0b...................0............
176	* page mode = enabled -> 0b....................1...........
177	* first wait= 1 clocks -> 0b.....................01.........
178	* burst wait= 1 clocks -> 0b.......................01.......
179	* precharge = 1 clocks -> 0b.........................0......
180	* RAS Rfrsh = 2 clocks -> 0b..........................1.....
181	* Rfrsh Itvl= 512 clks -> 0b...........................1000.
182	* ram type = DRAM -> 0b...............................0
183	* value 0b00010000100110010010101010110000
184	* 0x 1 0 9 9 2 A B 0
185	*/
186	lis r2,0x1099
187	ori r2,r2,0x2AB0
188	mtdcr br6,r2 /* write to DCR BR6*/
189
190	lis r2,0x0100 /* start address = 0x01000000 */
191	lis r3,0x0100 /* size 16 MB = 0x01000000 */
192	bl ramacc /* test memory accessibility */
193	cmpi 0,0,r4,0 /* memory ok? else test smaller size */
194	beq ramcfgok /* ok, we found configuration... +/
195
196	lis r2,0x0000 /* disable BR6, config not ok */
197	mtdcr br6,r2 /* write to DCR BR6*/
198	b ramcfgok /* and finish configuration */
199
200	ramcfgt18:
201	/*--------------------------------------------------------------------
202	* test RAM config 8 MByte (1x2Mx32Bit)
203	------------------------------------------------------------------/
204	/* set up bank register BR7 for DRAM:
205	* base addr = 000xxxxx -> 0b00000000........................
206	* bank size = 8MByte -> 0b........011.....................
207	* bank use = readwrite-> 0b...........11...................
208	* seq. fill = targ.frst-> 0b.............0..................
209	* early RAS = disabled -> 0b..............0.................
210	* bus width = 32bit -> 0b...............10...............
211	* adr mux = internal -> 0b.................0..............
212	* RAS to CAS= 2 clocks -> 0b..................1.............
213	* Alt. Rfrsh= normal -> 0b...................0............
214	* page mode = enabled -> 0b....................1...........
215	* first wait= 1 clocks -> 0b.....................01.........
216	* burst wait= 1 clocks -> 0b.......................01.......
217	* precharge = 1 clocks -> 0b.........................0......
218	* RAS Rfrsh = 2 clocks -> 0b..........................1.....
219	* Rfrsh Itvl= 512 clks -> 0b...........................1000.
220	* ram type = DRAM -> 0b...............................0
221	* value 0b00000000011110010010101010110000
222	* 0x 0 0 7 9 2 A B 0
223	*/
224	lis r2,0x0079
225	ori r2,r2,0x2AB0
226	mtdcr br7,r2 /* write to DCR BR7 */
227
228	lis r2,0x0000 /* start address = 0x00000000 */
229	lis r3,0x0080 /* size 8 MB = 0x00800000 */
230	bl ramacc /* test memory accessibility */
231	cmpi 0,0,r4,0 /* memory ok? else test smaller size */
232	bne ramcfgt14
233
234	/*--------------------------------------------------------------------
235	* test RAM config 16 MByte (2x2Mx32Bit)
236	------------------------------------------------------------------/
237	/* set up bank register BR7 like above
238	* set up bank register BR6 for DRAM:
239	* base addr = 008xxxxx -> 0b00001000........................
240	* bank size = 08MByte -> 0b........011..................... (for now)
241	* bank use = readwrite-> 0b...........11...................
242	* seq. fill = targ.frst-> 0b.............0..................
243	* early RAS = disabled -> 0b..............0.................
244	* bus width = 32bit -> 0b...............10...............
245	* adr mux = internal -> 0b.................0..............
246	* RAS to CAS= 2 clocks -> 0b..................1.............
247	* Alt. Rfrsh= normal -> 0b...................0............
248	* page mode = enabled -> 0b....................1...........
249	* first wait= 1 clocks -> 0b.....................01.........
250	* burst wait= 1 clocks -> 0b.......................01.......
251	* precharge = 1 clocks -> 0b.........................0......
252	* RAS Rfrsh = 2 clocks -> 0b..........................1.....
253	* Rfrsh Itvl= 512 clks -> 0b...........................1000.
254	* ram type = DRAM -> 0b...............................0
255	* value 0b00001000011110010010101010110000
256	* 0x 0 8 7 9 2 A B 0
257	*/
258	lis r2,0x0879
259	ori r2,r2,0x2AB0
260	mtdcr br6,r2 /* write to DCR BR6*/
261
262	lis r2,0x0080 /* start address = 0x00800000 */
263	lis r3,0x0080 /* size 8 MB = 0x00800000 */
264	bl ramacc /* test memory accessibility */
265	cmpi 0,0,r4,0 /* memory ok? else test smaller size */
266	beq ramcfgok /* ok, we found configuration... +/
267
268	lis r2,0x0000 /* disable BR6, config not ok */
269	mtdcr br6,r2 /* write to DCR BR6*/
270	b ramcfgok /* and finish configuration */
271
272	ramcfgt14:
273	/*--------------------------------------------------------------------
274	* test RAM config 4 MByte (1x1Mx32Bit)
275	------------------------------------------------------------------/
276	/* set up bank register BR7 for DRAM:
277	* base addr = 000xxxxx -> 0b00000000........................
278	* bank size = 4MByte -> 0b........010.....................
279	* bank use = readwrite-> 0b...........11...................
280	* seq. fill = targ.frst-> 0b.............0..................
281	* early RAS = disabled -> 0b..............0.................
282	* bus width = 32bit -> 0b...............10...............
283	* adr mux = internal -> 0b.................0..............
284	* RAS to CAS= 2 clocks -> 0b..................1.............
285	* Alt. Rfrsh= normal -> 0b...................0............
286	* page mode = enabled -> 0b....................1...........
287	* first wait= 1 clocks -> 0b.....................01.........
288	* burst wait= 1 clocks -> 0b.......................01.......
289	* precharge = 1 clocks -> 0b.........................0......
290	* RAS Rfrsh = 2 clocks -> 0b..........................1.....
291	* Rfrsh Itvl= 512 clks -> 0b...........................1000.
292	* ram type = DRAM -> 0b...............................0
293	* value 0b00000000010110010010101010110000
294	* 0x 0 0 5 9 2 A B 0
295	*/
296	/*
297	* FIXME: this is the minimum size supported, should test and
298	* report error, when failed
299	*/
300	lis r2,0x0059
301	ori r2,r2,0x2AB0
302	mtdcr br7,r2 /* write to DCR BR7*/
303
304	/*--------------------------------------------------------------------
305	* test RAM config 8 MByte (2x1Mx32Bit)
306	------------------------------------------------------------------/
307	/* set up bank register BR7 like above
308	* set up bank register BR6 for DRAM:
309	* base addr = 004xxxxx -> 0b00000100........................
310	* bank size = 4MByte -> 0b........010..................... (for now)
311	* bank use = readwrite-> 0b...........11...................
312	* seq. fill = targ.frst-> 0b.............0..................
313	* early RAS = disabled -> 0b..............0.................
314	* bus width = 32bit -> 0b...............10...............
315	* adr mux = internal -> 0b.................0..............
316	* RAS to CAS= 2 clocks -> 0b..................1.............
317	* Alt. Rfrsh= normal -> 0b...................0............
318	* page mode = enabled -> 0b....................1...........
319	* first wait= 1 clocks -> 0b.....................01.........
320	* burst wait= 1 clocks -> 0b.......................01.......
321	* precharge = 1 clocks -> 0b.........................0......
322	* RAS Rfrsh = 2 clocks -> 0b..........................1.....
323	* Rfrsh Itvl= 512 clks -> 0b...........................1000.
324	* ram type = DRAM -> 0b...............................0
325	* value 0b00000100010110010010101010110000
326	* 0x 0 4 5 9 2 A B 0
327	*/
328	lis r2,0x0459
329	ori r2,r2,0x2AB0
330	mtdcr br6,r2 /* write to DCR BR6*/
331
332	lis r2,0x0040 /* start address = 0x00400000 */
333	lis r3,0x0040 /* size 4 MB = 0x00400000 */
334	bl ramacc /* test memory accessibility */
335	cmpi 0,0,r4,0 /* memory ok? else test smaller size */
336	beq ramcfgok /* ok, we found configuration... +/
337
338	lis r2,0x0000 /* disable BR6, config not ok */
339	mtdcr br6,r2 /* write to DCR BR6*/
340	b ramcfgok /* and finish configuration */
341
342	ramcfgok:
343	/*--------------------------------------------------------------------
344	* init the DRAM where STACK+ DATA+ BBS will be placed. If this is OK
345	* we will return here.
346	-------------------------------------------------------------------/
347	bl rom2ram
348
349	/* clear caches */
350	addi r2,0,PPC_I_CACHE/PPC_CACHE_ALIGNMENT
351	mtctr r2 /* count the loops needed... */
352	xor r2,r2,r2 /* start at adr zero */
353	icinvlp:
354	iccci 0,r2
355	addi r2,r2,PPC_CACHE_ALIGNMENT
356	bdnz icinvlp
357
358	addi r2,r0,PPC_D_CACHE/PPC_CACHE_ALIGNMENT
359	mtctr r2 /* count the loops needed... */
360	xor r2,r2,r2 /* start at adr 0 */
361	dcinvlp:
362	dccci 0,r2
363	addi r2,r2,PPC_CACHE_ALIGNMENT
364	bdnz dcinvlp
365	/*--------------------------------------------------------------------
366	* Enable two 128MB cachable regions.
367	* FEPROM is cachable at 0xFFF00000..0xFFFFFFFF
368	* DRAM is cachable at 0x00000000..0x00FFFFFF
369	* FEPROM is noncachable at 0x7FF00000..0x7FFFFFFF
370	* DRAM is noncachable at 0x80000000..0x80FFFFFF
371	-------------------------------------------------------------------/
372	addis r2,r0,0x8000
373	addi r2,r2,0x0001
374
375	mtspr iccr, r2 /* ICCR */
376	mtspr dccr, r2 /* DCCR */
377
378	.extern SYM(__vectors)
379
380	lis r2,__vectors@h /* set EVPR exc. vector prefix */
381	mtspr evpr,r2
382
383	lis r2,0x0000
384	ori r2,r2,0x0000
385	mtmsr r2 /* set default msr */
386	lis r2,0x0000 /* do not allow critical IRQ */
387	ori r2,r2,0x0000
388	mtdcr exier, r2 /* disable all external IRQs */
389
390	addi r2,r0,-1 /* r2 = 0xffffffff */
391	mtdcr exisr, r2 /* clear all pendingdisable IRQs */
392
393	/*--------------------------------------------------------------------
394	* C_setup.
395	-------------------------------------------------------------------/
396
397	lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */
398	lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */
399
400	addi r1,r1,-56 /* start stack at data_addr - 56 */
401	addi r3,r0,0x0 /* clear r3 */
402	stw r3, 0(r1) /* Clear stack chain */
403	stw r3, 4(r1)
404	stw r3, 8(r1)
405	stw r3, 12(r1)
406	.extern SYM (boot_card)
407	b SYM (boot_card) /* call the first C routine */
408
409	/*----------------------------------------------------------------------------
410	* Rom2ram.
411	---------------------------------------------------------------------------/
412	rom2ram:
413	lwz r2,copy_dest-base_addr(r1) /* start of data set by loader */
414	lwz r3,copy_length-base_addr(r1) /* data length */
415	rlwinm r3,r3,30,0x3FFFFFFF /* form length/4 */
416	mtctr r3 /* set ctr reg */
417	/*--------------------------------------------------------------------
418	* Calculate offset of data in image.
419	-------------------------------------------------------------------/
420	lwz r4,copy_src-base_addr(r1) /* get start of copy area */
421	move_data:
422	lswi r6,r4,0x4 /* load r6 */
423	stswi r6,r2,0x4 /* store r6 */
424	addi r4,r4,0x4 /* update r4 */
425	addi r2,r2,0x4 /* update r2 */
426	bdnz move_data /* decrement counter and loop */
427	/*--------------------------------------------------------------------
428	* Data move finished, zero out bss.
429	-------------------------------------------------------------------/
430	lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */
431	lwz r3,bss_length-base_addr(r1) /* bss length */
432	rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */
433	beqlr /* no bss */
434	mtctr r3 /* set ctr reg */
435	xor r6,r6,r6 /* r6 = 0 */
436	clear_bss:
437	stswi r6,r2,0x4 /* store r6 */
438	addi r2,r2,0x4 /* update r2 */
439	bdnz clear_bss /* decrement counter and loop */
440	blr /* return */
441
442	/*----------------------------------------------------------------------------
443	* ramacc test accessibility of RAM
444	* input: r2 = start address, r3 = length (in byte)
445	* output: r4 = 0 -> ok, !=0 -> fail
446	---------------------------------------------------------------------------/
447	ramacc:
448	xor r4,r4,r4 /* r4 = 0 */
449	stw r4,0(r2) /* init ram at start address */
450	addi r4,r0,0x04 /* set start shift */
451	ramaccf1:
452	cmp 0,0,r4,r3 /* compare with length */
453	bge ramaccfx /* r4 >= r3? then finished */
454	add r5,r4,r2 /* get next address to fill */
455	stw r4,0(r5) /* store new pattern */
456	add r4,r4,r4 /* r4 = r42 /
457	b ramaccf1 /* and then next loop */
458
459	ramaccfx:
460	lwz r4,0(r2) /* get memory at start adr */
461	blr
462
463
464	#if PPC_ABI == PPC_ABI_POWEROPEN
465	DESCRIPTOR (startup)
466	#endif
467
468
469

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