| 1 | /* flashentry.s |
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| 2 | * |
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| 3 | * This file contains the entry code for RTEMS programs starting |
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| 4 | * directly from Flash. |
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| 5 | * |
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| 6 | * Author: Thomas Doerfler <td@imd.m.isar.de> |
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| 7 | * IMD Ingenieurbuero fuer Microcomputertechnik |
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| 8 | * |
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| 9 | * COPYRIGHT (c) 1998 by IMD |
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| 10 | * |
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| 11 | * Changes from IMD are covered by the original distributions terms. |
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| 12 | * This file has been derived from the papyrus BSP: |
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| 13 | * |
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| 14 | * This file contains the entry veneer for RTEMS programs |
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| 15 | * stored in Papyrus' flash ROM. |
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| 16 | * |
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| 17 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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| 18 | * |
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| 19 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 20 | * |
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| 21 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 22 | * without any express or implied warranty: |
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| 23 | * permission to use, copy, modify, and distribute this file |
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| 24 | * for any purpose is hereby granted without fee, provided that |
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| 25 | * the above copyright notice and this notice appears in all |
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| 26 | * copies, and that the name of i-cubed limited not be used in |
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| 27 | * advertising or publicity pertaining to distribution of the |
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| 28 | * software without specific, written prior permission. |
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| 29 | * i-cubed limited makes no representations about the suitability |
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| 30 | * of this software for any purpose. |
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| 31 | * |
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| 32 | * $Id$ |
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| 33 | */ |
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| 34 | |
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| 35 | #include "asm.h" |
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| 36 | #include <rtems/score/ppc.h> |
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| 37 | |
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| 38 | /*---------------------------------------------------------------------------- |
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| 39 | * Reset_entry. |
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| 40 | *---------------------------------------------------------------------------*/ |
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| 41 | #if PPC_ASM == PPC_ASM_ELF |
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| 42 | .section .reset,"ax",@progbits |
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| 43 | /* this section MUST be located at absolute address 0xFFFFFFFC |
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| 44 | or last word of EPROM */ |
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| 45 | #else |
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| 46 | .csect .text[PR] |
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| 47 | #endif |
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| 48 | |
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| 49 | ba flash_entry /* this is the first instruction after reset */ |
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| 50 | |
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| 51 | .previous |
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| 52 | |
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| 53 | /*---------------------------------------------------------------------------- |
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| 54 | * ROM Vector area. |
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| 55 | *---------------------------------------------------------------------------*/ |
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| 56 | #if PPC_ASM == PPC_ASM_ELF |
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| 57 | .section .entry,"ax",@progbits |
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| 58 | #else |
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| 59 | .csect .text[PR] |
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| 60 | #endif |
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| 61 | PUBLIC_VAR (flash_entry) |
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| 62 | SYM (flash_entry): |
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| 63 | bl .startup /* call startup, link reg points to base_addr */ |
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| 64 | base_addr: |
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| 65 | /*---------------------------------------------------------------------------- |
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| 66 | * Parameters from linker |
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| 67 | *---------------------------------------------------------------------------*/ |
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| 68 | toc_pointer: |
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| 69 | #if PPC_ASM == PPC_ASM_ELF |
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| 70 | .long s.got |
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| 71 | #else |
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| 72 | .long TOC[tc0] |
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| 73 | #endif |
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| 74 | text_length: |
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| 75 | .long text.size |
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| 76 | text_addr: |
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| 77 | .long text.start |
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| 78 | copy_src: |
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| 79 | .long copy.src |
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| 80 | copy_length: |
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| 81 | .long copy.size |
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| 82 | copy_dest: |
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| 83 | .long copy.dest |
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| 84 | bss_length: |
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| 85 | .long bss.size |
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| 86 | bss_addr: |
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| 87 | .long bss.start |
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| 88 | stack_top: |
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| 89 | .long stack.end |
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| 90 | |
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| 91 | /*---------------------------------------------------------------------------- |
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| 92 | * from Reset_entry. |
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| 93 | *---------------------------------------------------------------------------*/ |
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| 94 | .startup: |
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| 95 | /* Get start address, r1 points to label base_addr */ |
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| 96 | mflr r1 |
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| 97 | |
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| 98 | /* Set up Bank regs, cache etc. */ |
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| 99 | /* set up bank register BR0 for Flash-EPROM: |
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| 100 | * NOTE: bank size should stay 1MByte, this is standard size |
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| 101 | * after RESET |
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| 102 | * base addr = Fffxxxxx -> 0b11111111........................ |
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| 103 | * bank size = 1 MByte -> 0b........000..................... (std) |
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| 104 | * bank use = readonly -> 0b...........01................... |
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| 105 | * seq. fill = targ frst-> 0b.............0.................. |
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| 106 | * burst mode= enable -> 0b..............1................. |
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| 107 | * bus width = 8 bit -> 0b...............00............... |
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| 108 | * ready pin = disable -> 0b.................0.............. |
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| 109 | * first wait= 2 clocks -> 0b..................0010.......... |
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| 110 | * burst wait= 2 clocks -> 0b......................10........ |
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| 111 | * CSon time = 0 clocks -> 0b........................0....... |
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| 112 | * OEon time = 0 clocks -> 0b.........................0...... |
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| 113 | * WBon time = 1 clocks -> 0b..........................1..... |
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| 114 | * WBoff time= 0 clocks -> 0b...........................0.... |
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| 115 | * Hold time = 1 clocks -> 0b............................001. |
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| 116 | * ram type = SRAM(ign)-> 0b...............................1 |
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| 117 | * value 0b11111111000010100000101000100011 |
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| 118 | * 0x F F 0 A 0 A 2 3 |
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| 119 | */ |
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| 120 | lis r2,0xFF0A |
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| 121 | ori r2,r2,0x0A23 |
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| 122 | |
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| 123 | mtdcr br0,r2 /* write to DCR BR0 */ |
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| 124 | |
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| 125 | |
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| 126 | /*-------------------------------------------------------------------- |
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| 127 | * test various RAM configurations (from big to small per bank) |
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| 128 | *------------------------------------------------------------------*/ |
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| 129 | /*-------------------------------------------------------------------- |
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| 130 | * test RAM config 16 MByte (1x4Mx32Bit) |
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| 131 | *------------------------------------------------------------------*/ |
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| 132 | /* set up bank register BR7 for DRAM: |
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| 133 | * base addr = 000xxxxx -> 0b00000000........................ |
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| 134 | * bank size = 16MByte -> 0b........100..................... |
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| 135 | * bank use = readwrite-> 0b...........11................... |
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| 136 | * seq. fill = targ.frst-> 0b.............0.................. |
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| 137 | * early RAS = disabled -> 0b..............0................. |
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| 138 | * bus width = 32bit -> 0b...............10............... |
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| 139 | * adr mux = internal -> 0b.................0.............. |
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| 140 | * RAS to CAS= 2 clocks -> 0b..................1............. |
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| 141 | * Alt. Rfrsh= normal -> 0b...................0............ |
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| 142 | * page mode = enabled -> 0b....................1........... |
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| 143 | * first wait= 1 clocks -> 0b.....................01......... |
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| 144 | * burst wait= 1 clocks -> 0b.......................01....... |
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| 145 | * precharge = 1 clocks -> 0b.........................0...... |
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| 146 | * RAS Rfrsh = 2 clocks -> 0b..........................1..... |
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| 147 | * Rfrsh Itvl= 512 clks -> 0b...........................1000. |
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| 148 | * ram type = DRAM -> 0b...............................0 |
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| 149 | * value 0b00000000100110010010101010110000 |
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| 150 | * 0x 0 0 9 9 2 A B 0 |
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| 151 | */ |
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| 152 | lis r2,0x0099 |
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| 153 | ori r2,r2,0x2AB0 |
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| 154 | mtdcr br7,r2 /* write to DCR BR7*/ |
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| 155 | |
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| 156 | lis r2,0x0000 /* start address = 0x00000000 */ |
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| 157 | lis r3,0x0100 /* size 16 MB = 0x01000000 */ |
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| 158 | bl ramacc /* test memory accessibility */ |
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| 159 | cmpi 0,0,r4,0 /* memory ok? else test smaller size */ |
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| 160 | bne ramcfgt18 |
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| 161 | |
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| 162 | /*-------------------------------------------------------------------- |
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| 163 | * test RAM config 32 MByte (2x4Mx32Bit) |
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| 164 | *------------------------------------------------------------------*/ |
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| 165 | /* set up bank register BR7 like above |
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| 166 | * set up bank register BR6 for DRAM: |
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| 167 | * base addr = 010xxxxx -> 0b00010000........................ |
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| 168 | * bank size = 16MByte -> 0b........100..................... (for now) |
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| 169 | * bank use = readwrite-> 0b...........11................... |
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| 170 | * seq. fill = targ.frst-> 0b.............0.................. |
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| 171 | * early RAS = disabled -> 0b..............0................. |
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| 172 | * bus width = 32bit -> 0b...............10............... |
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| 173 | * adr mux = internal -> 0b.................0.............. |
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| 174 | * RAS to CAS= 2 clocks -> 0b..................1............. |
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| 175 | * Alt. Rfrsh= normal -> 0b...................0............ |
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| 176 | * page mode = enabled -> 0b....................1........... |
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| 177 | * first wait= 1 clocks -> 0b.....................01......... |
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| 178 | * burst wait= 1 clocks -> 0b.......................01....... |
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| 179 | * precharge = 1 clocks -> 0b.........................0...... |
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| 180 | * RAS Rfrsh = 2 clocks -> 0b..........................1..... |
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| 181 | * Rfrsh Itvl= 512 clks -> 0b...........................1000. |
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| 182 | * ram type = DRAM -> 0b...............................0 |
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| 183 | * value 0b00010000100110010010101010110000 |
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| 184 | * 0x 1 0 9 9 2 A B 0 |
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| 185 | */ |
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| 186 | lis r2,0x1099 |
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| 187 | ori r2,r2,0x2AB0 |
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| 188 | mtdcr br6,r2 /* write to DCR BR6*/ |
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| 189 | |
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| 190 | lis r2,0x0100 /* start address = 0x01000000 */ |
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| 191 | lis r3,0x0100 /* size 16 MB = 0x01000000 */ |
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| 192 | bl ramacc /* test memory accessibility */ |
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| 193 | cmpi 0,0,r4,0 /* memory ok? else test smaller size */ |
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| 194 | beq ramcfgok /* ok, we found configuration... +/ |
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| 195 | |
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| 196 | lis r2,0x0000 /* disable BR6, config not ok */ |
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| 197 | mtdcr br6,r2 /* write to DCR BR6*/ |
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| 198 | b ramcfgok /* and finish configuration */ |
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| 199 | |
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| 200 | ramcfgt18: |
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| 201 | /*-------------------------------------------------------------------- |
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| 202 | * test RAM config 8 MByte (1x2Mx32Bit) |
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| 203 | *------------------------------------------------------------------*/ |
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| 204 | /* set up bank register BR7 for DRAM: |
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| 205 | * base addr = 000xxxxx -> 0b00000000........................ |
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| 206 | * bank size = 8MByte -> 0b........011..................... |
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| 207 | * bank use = readwrite-> 0b...........11................... |
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| 208 | * seq. fill = targ.frst-> 0b.............0.................. |
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| 209 | * early RAS = disabled -> 0b..............0................. |
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| 210 | * bus width = 32bit -> 0b...............10............... |
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| 211 | * adr mux = internal -> 0b.................0.............. |
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| 212 | * RAS to CAS= 2 clocks -> 0b..................1............. |
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| 213 | * Alt. Rfrsh= normal -> 0b...................0............ |
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| 214 | * page mode = enabled -> 0b....................1........... |
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| 215 | * first wait= 1 clocks -> 0b.....................01......... |
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| 216 | * burst wait= 1 clocks -> 0b.......................01....... |
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| 217 | * precharge = 1 clocks -> 0b.........................0...... |
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| 218 | * RAS Rfrsh = 2 clocks -> 0b..........................1..... |
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| 219 | * Rfrsh Itvl= 512 clks -> 0b...........................1000. |
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| 220 | * ram type = DRAM -> 0b...............................0 |
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| 221 | * value 0b00000000011110010010101010110000 |
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| 222 | * 0x 0 0 7 9 2 A B 0 |
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| 223 | */ |
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| 224 | lis r2,0x0079 |
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| 225 | ori r2,r2,0x2AB0 |
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| 226 | mtdcr br7,r2 /* write to DCR BR7 */ |
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| 227 | |
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| 228 | lis r2,0x0000 /* start address = 0x00000000 */ |
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| 229 | lis r3,0x0080 /* size 8 MB = 0x00800000 */ |
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| 230 | bl ramacc /* test memory accessibility */ |
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| 231 | cmpi 0,0,r4,0 /* memory ok? else test smaller size */ |
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| 232 | bne ramcfgt14 |
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| 233 | |
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| 234 | /*-------------------------------------------------------------------- |
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| 235 | * test RAM config 16 MByte (2x2Mx32Bit) |
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| 236 | *------------------------------------------------------------------*/ |
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| 237 | /* set up bank register BR7 like above |
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| 238 | * set up bank register BR6 for DRAM: |
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| 239 | * base addr = 008xxxxx -> 0b00001000........................ |
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| 240 | * bank size = 08MByte -> 0b........011..................... (for now) |
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| 241 | * bank use = readwrite-> 0b...........11................... |
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| 242 | * seq. fill = targ.frst-> 0b.............0.................. |
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| 243 | * early RAS = disabled -> 0b..............0................. |
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| 244 | * bus width = 32bit -> 0b...............10............... |
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| 245 | * adr mux = internal -> 0b.................0.............. |
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| 246 | * RAS to CAS= 2 clocks -> 0b..................1............. |
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| 247 | * Alt. Rfrsh= normal -> 0b...................0............ |
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| 248 | * page mode = enabled -> 0b....................1........... |
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| 249 | * first wait= 1 clocks -> 0b.....................01......... |
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| 250 | * burst wait= 1 clocks -> 0b.......................01....... |
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| 251 | * precharge = 1 clocks -> 0b.........................0...... |
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| 252 | * RAS Rfrsh = 2 clocks -> 0b..........................1..... |
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| 253 | * Rfrsh Itvl= 512 clks -> 0b...........................1000. |
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| 254 | * ram type = DRAM -> 0b...............................0 |
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| 255 | * value 0b00001000011110010010101010110000 |
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| 256 | * 0x 0 8 7 9 2 A B 0 |
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| 257 | */ |
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| 258 | lis r2,0x0879 |
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| 259 | ori r2,r2,0x2AB0 |
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| 260 | mtdcr br6,r2 /* write to DCR BR6*/ |
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| 261 | |
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| 262 | lis r2,0x0080 /* start address = 0x00800000 */ |
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| 263 | lis r3,0x0080 /* size 8 MB = 0x00800000 */ |
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| 264 | bl ramacc /* test memory accessibility */ |
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| 265 | cmpi 0,0,r4,0 /* memory ok? else test smaller size */ |
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| 266 | beq ramcfgok /* ok, we found configuration... +/ |
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| 267 | |
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| 268 | lis r2,0x0000 /* disable BR6, config not ok */ |
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| 269 | mtdcr br6,r2 /* write to DCR BR6*/ |
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| 270 | b ramcfgok /* and finish configuration */ |
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| 271 | |
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| 272 | ramcfgt14: |
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| 273 | /*-------------------------------------------------------------------- |
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| 274 | * test RAM config 4 MByte (1x1Mx32Bit) |
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| 275 | *------------------------------------------------------------------*/ |
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| 276 | /* set up bank register BR7 for DRAM: |
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| 277 | * base addr = 000xxxxx -> 0b00000000........................ |
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| 278 | * bank size = 4MByte -> 0b........010..................... |
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| 279 | * bank use = readwrite-> 0b...........11................... |
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| 280 | * seq. fill = targ.frst-> 0b.............0.................. |
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| 281 | * early RAS = disabled -> 0b..............0................. |
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| 282 | * bus width = 32bit -> 0b...............10............... |
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| 283 | * adr mux = internal -> 0b.................0.............. |
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| 284 | * RAS to CAS= 2 clocks -> 0b..................1............. |
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| 285 | * Alt. Rfrsh= normal -> 0b...................0............ |
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| 286 | * page mode = enabled -> 0b....................1........... |
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| 287 | * first wait= 1 clocks -> 0b.....................01......... |
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| 288 | * burst wait= 1 clocks -> 0b.......................01....... |
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| 289 | * precharge = 1 clocks -> 0b.........................0...... |
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| 290 | * RAS Rfrsh = 2 clocks -> 0b..........................1..... |
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| 291 | * Rfrsh Itvl= 512 clks -> 0b...........................1000. |
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| 292 | * ram type = DRAM -> 0b...............................0 |
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| 293 | * value 0b00000000010110010010101010110000 |
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| 294 | * 0x 0 0 5 9 2 A B 0 |
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| 295 | */ |
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| 296 | /* |
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| 297 | * FIXME: this is the minimum size supported, should test and |
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| 298 | * report error, when failed |
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| 299 | */ |
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| 300 | lis r2,0x0059 |
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| 301 | ori r2,r2,0x2AB0 |
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| 302 | mtdcr br7,r2 /* write to DCR BR7*/ |
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| 303 | |
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| 304 | /*-------------------------------------------------------------------- |
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| 305 | * test RAM config 8 MByte (2x1Mx32Bit) |
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| 306 | *------------------------------------------------------------------*/ |
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| 307 | /* set up bank register BR7 like above |
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| 308 | * set up bank register BR6 for DRAM: |
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| 309 | * base addr = 004xxxxx -> 0b00000100........................ |
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| 310 | * bank size = 4MByte -> 0b........010..................... (for now) |
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| 311 | * bank use = readwrite-> 0b...........11................... |
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| 312 | * seq. fill = targ.frst-> 0b.............0.................. |
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| 313 | * early RAS = disabled -> 0b..............0................. |
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| 314 | * bus width = 32bit -> 0b...............10............... |
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| 315 | * adr mux = internal -> 0b.................0.............. |
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| 316 | * RAS to CAS= 2 clocks -> 0b..................1............. |
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| 317 | * Alt. Rfrsh= normal -> 0b...................0............ |
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| 318 | * page mode = enabled -> 0b....................1........... |
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| 319 | * first wait= 1 clocks -> 0b.....................01......... |
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| 320 | * burst wait= 1 clocks -> 0b.......................01....... |
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| 321 | * precharge = 1 clocks -> 0b.........................0...... |
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| 322 | * RAS Rfrsh = 2 clocks -> 0b..........................1..... |
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| 323 | * Rfrsh Itvl= 512 clks -> 0b...........................1000. |
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| 324 | * ram type = DRAM -> 0b...............................0 |
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| 325 | * value 0b00000100010110010010101010110000 |
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| 326 | * 0x 0 4 5 9 2 A B 0 |
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| 327 | */ |
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| 328 | lis r2,0x0459 |
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| 329 | ori r2,r2,0x2AB0 |
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| 330 | mtdcr br6,r2 /* write to DCR BR6*/ |
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| 331 | |
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| 332 | lis r2,0x0040 /* start address = 0x00400000 */ |
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| 333 | lis r3,0x0040 /* size 4 MB = 0x00400000 */ |
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| 334 | bl ramacc /* test memory accessibility */ |
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| 335 | cmpi 0,0,r4,0 /* memory ok? else test smaller size */ |
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| 336 | beq ramcfgok /* ok, we found configuration... +/ |
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| 337 | |
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| 338 | lis r2,0x0000 /* disable BR6, config not ok */ |
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| 339 | mtdcr br6,r2 /* write to DCR BR6*/ |
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| 340 | b ramcfgok /* and finish configuration */ |
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| 341 | |
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| 342 | ramcfgok: |
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| 343 | /*-------------------------------------------------------------------- |
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| 344 | * init the DRAM where STACK+ DATA+ BBS will be placed. If this is OK |
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| 345 | * we will return here. |
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| 346 | *-------------------------------------------------------------------*/ |
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| 347 | bl rom2ram |
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| 348 | |
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| 349 | /* clear caches */ |
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| 350 | addi r2,0,PPC_I_CACHE/PPC_CACHE_ALIGNMENT |
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| 351 | mtctr r2 /* count the loops needed... */ |
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| 352 | xor r2,r2,r2 /* start at adr zero */ |
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| 353 | icinvlp: |
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| 354 | iccci 0,r2 |
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| 355 | addi r2,r2,PPC_CACHE_ALIGNMENT |
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| 356 | bdnz icinvlp |
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| 357 | |
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| 358 | addi r2,r0,PPC_D_CACHE/PPC_CACHE_ALIGNMENT |
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| 359 | mtctr r2 /* count the loops needed... */ |
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| 360 | xor r2,r2,r2 /* start at adr 0 */ |
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| 361 | dcinvlp: |
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| 362 | dccci 0,r2 |
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| 363 | addi r2,r2,PPC_CACHE_ALIGNMENT |
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| 364 | bdnz dcinvlp |
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| 365 | /*-------------------------------------------------------------------- |
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| 366 | * Enable two 128MB cachable regions. |
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| 367 | * FEPROM is cachable at 0xFFF00000..0xFFFFFFFF |
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| 368 | * DRAM is cachable at 0x00000000..0x00FFFFFF |
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| 369 | * FEPROM is noncachable at 0x7FF00000..0x7FFFFFFF |
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| 370 | * DRAM is noncachable at 0x80000000..0x80FFFFFF |
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| 371 | *-------------------------------------------------------------------*/ |
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| 372 | addis r2,r0,0x8000 |
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| 373 | addi r2,r2,0x0001 |
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| 374 | |
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| 375 | mtspr iccr, r2 /* ICCR */ |
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| 376 | mtspr dccr, r2 /* DCCR */ |
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| 377 | |
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| 378 | .extern SYM(__vectors) |
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| 379 | |
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| 380 | lis r2,__vectors@h /* set EVPR exc. vector prefix */ |
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| 381 | mtspr evpr,r2 |
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| 382 | |
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| 383 | lis r2,0x0000 |
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| 384 | ori r2,r2,0x0000 |
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| 385 | mtmsr r2 /* set default msr */ |
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| 386 | lis r2,0x0000 /* do not allow critical IRQ */ |
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| 387 | ori r2,r2,0x0000 |
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| 388 | mtdcr exier, r2 /* disable all external IRQs */ |
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| 389 | |
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| 390 | addi r2,r0,-1 /* r2 = 0xffffffff */ |
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| 391 | mtdcr exisr, r2 /* clear all pendingdisable IRQs */ |
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| 392 | |
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| 393 | /*-------------------------------------------------------------------- |
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| 394 | * C_setup. |
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| 395 | *-------------------------------------------------------------------*/ |
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| 396 | |
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| 397 | lwz r2,toc_pointer-base_addr(r1) /* set r2 to toc */ |
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| 398 | lwz r1,stack_top-base_addr(r1) /* set r1 to stack_top */ |
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| 399 | |
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| 400 | addi r1,r1,-56 /* start stack at data_addr - 56 */ |
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| 401 | addi r3,r0,0x0 /* clear r3 */ |
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| 402 | stw r3, 0(r1) /* Clear stack chain */ |
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| 403 | stw r3, 4(r1) |
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| 404 | stw r3, 8(r1) |
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| 405 | stw r3, 12(r1) |
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| 406 | lis r5,environ@ha |
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| 407 | la r5,environ@l(r5) /* environp */ |
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| 408 | li r4, 0 /* argv */ |
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| 409 | li r3, 0 /* argc */ |
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| 410 | .extern SYM (boot_card) |
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| 411 | b SYM (boot_card) /* call the first C routine */ |
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| 412 | |
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| 413 | /*---------------------------------------------------------------------------- |
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| 414 | * Rom2ram. |
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| 415 | *---------------------------------------------------------------------------*/ |
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| 416 | rom2ram: |
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| 417 | lwz r2,copy_dest-base_addr(r1) /* start of data set by loader */ |
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| 418 | lwz r3,copy_length-base_addr(r1) /* data length */ |
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| 419 | rlwinm r3,r3,30,0x3FFFFFFF /* form length/4 */ |
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| 420 | mtctr r3 /* set ctr reg */ |
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| 421 | /*-------------------------------------------------------------------- |
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| 422 | * Calculate offset of data in image. |
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| 423 | *-------------------------------------------------------------------*/ |
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| 424 | lwz r4,copy_src-base_addr(r1) /* get start of copy area */ |
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| 425 | move_data: |
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| 426 | lswi r6,r4,0x4 /* load r6 */ |
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| 427 | stswi r6,r2,0x4 /* store r6 */ |
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| 428 | addi r4,r4,0x4 /* update r4 */ |
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| 429 | addi r2,r2,0x4 /* update r2 */ |
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| 430 | bdnz move_data /* decrement counter and loop */ |
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| 431 | /*-------------------------------------------------------------------- |
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| 432 | * Data move finished, zero out bss. |
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| 433 | *-------------------------------------------------------------------*/ |
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| 434 | lwz r2,bss_addr-base_addr(r1) /* start of bss set by loader */ |
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| 435 | lwz r3,bss_length-base_addr(r1) /* bss length */ |
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| 436 | rlwinm. r3,r3,30,0x3FFFFFFF /* form length/4 */ |
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| 437 | beqlr /* no bss */ |
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| 438 | mtctr r3 /* set ctr reg */ |
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| 439 | xor r6,r6,r6 /* r6 = 0 */ |
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| 440 | clear_bss: |
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| 441 | stswi r6,r2,0x4 /* store r6 */ |
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| 442 | addi r2,r2,0x4 /* update r2 */ |
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| 443 | bdnz clear_bss /* decrement counter and loop */ |
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| 444 | blr /* return */ |
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| 445 | |
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| 446 | /*---------------------------------------------------------------------------- |
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| 447 | * ramacc test accessibility of RAM |
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| 448 | * input: r2 = start address, r3 = length (in byte) |
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| 449 | * output: r4 = 0 -> ok, !=0 -> fail |
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| 450 | *---------------------------------------------------------------------------*/ |
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| 451 | ramacc: |
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| 452 | xor r4,r4,r4 /* r4 = 0 */ |
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| 453 | stw r4,0(r2) /* init ram at start address */ |
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| 454 | addi r4,r0,0x04 /* set start shift */ |
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| 455 | ramaccf1: |
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| 456 | cmp 0,0,r4,r3 /* compare with length */ |
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| 457 | bge ramaccfx /* r4 >= r3? then finished */ |
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| 458 | add r5,r4,r2 /* get next address to fill */ |
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| 459 | stw r4,0(r5) /* store new pattern */ |
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| 460 | add r4,r4,r4 /* r4 = r4*2 */ |
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| 461 | b ramaccf1 /* and then next loop */ |
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| 462 | |
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| 463 | ramaccfx: |
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| 464 | lwz r4,0(r2) /* get memory at start adr */ |
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| 465 | blr |
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| 466 | |
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| 467 | |
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| 468 | #if PPC_ABI == PPC_ABI_POWEROPEN |
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| 469 | DESCRIPTOR (startup) |
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| 470 | #endif |
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| 471 | |
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| 472 | |
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| 473 | .comm environ,4,4 |
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| 474 | |
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| 475 | |
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